Firestorm: LDRB (pre-index) measurements

Code:

  ldrb w0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1057	7	1	0	0	0	0	152	16	0	0	4	0	1025	0	64	20	9	33	25	2000	1000	1000	1000	1000	52800	45821	1044	1055	700	3	784	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1033	8	1	73	1103	12	0	38	6	104	1093	42	6	101	63	7	45	0	73	1	16	1	1	1018	1000	30	30	8	1000	1000	1056	1052	1052	1052	1041
2004	1055	8	1	0	1	0	0	139	20	1	0	4	12	1038	11	66	10	14	43	25	2000	1000	1000	1000	1000	52800	45822	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1026	8	1	81	1105	7	0	33	16	104	1118	60	7	105	39	7	1	0	73	1	16	1	1	1037	1000	24	18	0	1000	1000	1041	1041	1053	1041	1053
2004	1040	7	1	1	0	0	1	140	18	1	0	4	0	1025	9	65	9	16	32	25	2000	1000	1000	1000	1000	52760	45825	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1076	6	3	100	1092	12	1	23	0	90	1108	37	6	82	63	6	1	0	73	1	16	1	1	1034	1000	31	28	0	1000	1000	1041	1041	1041	1042	1053
2004	1040	7	1	0	0	0	0	144	12	0	0	7	0	1044	10	58	9	10	39	25	2000	1000	1000	1000	1000	52808	45824	1040	1040	699	3	785	2000	1000	1000	1000	1000	1052	46	1	1	1001	1000	1000	2	1036	8	3	59	1102	4	0	34	18	106	1106	52	8	112	47	7	1	0	73	1	16	1	1	1021	1000	28	22	0	1000	1000	1041	1041	1053	1041	1042
2004	1040	8	1	0	1	0	0	132	12	0	0	3	4	1025	6	63	8	18	34	25	2000	1000	1000	1000	1000	52776	45823	1041	1040	699	3	773	2000	1000	1000	1000	1000	1052	46	1	1	1001	1000	1000	0	1034	7	2	76	1114	5	1	24	12	92	1095	48	4	86	47	7	1	0	73	1	16	1	1	1019	1000	25	20	5	1000	1000	1041	1041	1041	1041	1053
2004	1051	8	1	0	0	0	0	161	31	1	4	7	16	1025	0	60	15	16	40	25	2000	1000	1000	1000	1000	52820	45828	1052	1040	700	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1036	8	3	53	1117	7	0	24	6	82	1090	46	5	98	48	7	0	44	73	1	16	1	1	1006	1000	30	25	0	1000	1000	1042	1041	1041	1041	1041
2004	1040	7	1	0	1	0	0	141	0	0	0	2	12	1025	0	60	17	11	40	25	2000	1000	1000	1000	1000	52816	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1042	8	4	89	1123	11	0	29	6	111	1104	40	7	111	54	7	0	0	73	1	16	1	1	1036	1000	21	19	0	1000	1000	1041	1060	1050	1058	1053
2004	1052	8	1	0	0	0	0	137	24	1	0	5	24	1025	21	56	21	9	32	25	2000	1000	1000	1000	1000	52780	45825	1052	1051	701	3	785	2000	1000	1000	1000	1000	1052	46	1	1	1001	1000	1000	2	1032	6	2	84	1091	7	0	61	6	108	1146	31	7	91	63	6	1	0	73	1	16	1	1	1036	1000	21	20	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	1	1	0	0	127	0	0	0	4	0	1025	8	59	9	10	29	25	2000	1000	1000	1000	1000	52816	45823	1040	1040	700	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1018	8	3	61	1092	5	0	12	0	85	1125	46	6	94	63	7	1	0	73	1	16	1	1	1018	1000	21	20	0	1000	1000	1053	1053	1053	1041	1041
2004	1040	8	1	0	0	0	0	150	15	1	0	5	0	1025	10	50	14	14	32	25	2000	1000	1000	1000	1000	52816	45823	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1027	8	2	98	1125	10	0	23	12	81	1087	52	5	107	62	7	1	0	73	1	16	1	1	1036	1000	16	20	0	1000	1000	1041	1041	1041	1041	1053

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.2086

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	19	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72103	539	1	0	1	1	1	0	626	822	1	704	2	164	71915	786	43	1	71763	25	50955	40724	10176	40100	10000	614908	2730196	1	49	69088	71839	71927	65235	0	3	65657	50100	40200	10000	70200	10000	72209	35	1	1	40201	100	99	100	10000	30100	10000	100	10897	3	169	509	10657	264	12	921	48	80	10973	134	43	134	1	0	8	0	2610	2	58	1	1	71791	40688	888	848	915	10000	40100	72031	71950	72004	71994	72280
50204	72132	538	1	0	0	0	0	0	643	819	2	608	1	120	71956	797	43	4	71906	25	50915	40740	10170	40100	10000	615265	2730062	1	49	68975	71908	71951	65544	0	3	65699	50100	40200	10000	70200	10000	72150	35	1	1	40201	100	99	100	10000	30100	10000	100	10887	1	166	495	10641	263	14	921	48	79	10951	122	43	123	3	3	9	0	2610	1	58	1	1	71822	40660	770	822	925	10000	40100	71922	72207	71958	72115	71974
50204	72039	540	1	0	0	0	0	0	628	793	1	720	1	92	72138	804	46	4	71831	25	51025	40828	10149	40100	10000	616399	2737801	0	49	68972	72018	72164	65445	0	3	65577	50100	40200	10000	70200	10000	71990	35	1	1	40201	100	99	100	10000	30100	10000	100	10901	1	167	501	10655	278	14	921	32	76	10950	121	46	122	1	0	3	0	2610	1	49	1	1	72103	40660	908	996	942	10000	40100	72122	72109	72108	72089	72059
50204	72040	541	1	0	1	1	0	0	605	814	1	752	2	108	72128	793	46	4	71874	25	50985	40764	10152	40100	10000	615751	2731524	1	49	69099	72149	72147	65188	0	3	65675	50100	40200	10000	70200	10000	71858	35	1	1	40201	100	99	100	10000	30100	10000	100	10923	1	152	496	10657	255	11	894	32	82	10953	128	46	113	1	3	5	0	2610	1	63	0	1	71995	40632	848	866	970	10000	40100	71967	71882	71960	72220	71992
50204	72324	540	1	0	0	1	0	0	621	815	1	704	1	128	72238	821	46	3	71696	25	50950	40808	10182	40100	10000	616251	2726770	0	49	69056	72141	72233	65536	7	3	65727	50100	40200	10000	70200	10000	72047	35	1	1	40201	100	99	100	10000	30100	10000	100	10901	2	158	508	10671	256	15	924	48	95	10932	107	45	120	1	0	7	0	2610	1	56	1	1	71730	40744	984	956	830	10000	40100	72082	72150	72061	72053	72086
50204	72044	539	1	0	0	0	0	0	664	800	1	720	2	148	72213	803	42	3	71841	25	50910	40848	10167	40100	10000	616019	2737423	1	49	69022	71926	72093	65561	0	3	65822	50100	40200	10000	70200	10000	72113	35	1	1	40201	100	99	100	10000	30100	10000	100	10881	1	155	504	10659	253	13	878	36	80	10958	110	38	110	1	3	5	0	2610	2	57	1	1	71703	40660	728	958	942	10000	40100	72212	71785	71920	72073	71994
50204	71922	540	1	0	1	0	0	0	668	805	1	696	2	100	72092	783	45	6	71862	25	51020	40776	10170	40100	10000	615725	2736041	0	49	69204	72055	72213	65668	0	3	65724	50100	40200	10000	70200	10000	71988	35	1	1	40201	100	99	100	10000	30100	10000	100	10899	1	183	510	10663	281	14	901	92	83	10945	118	48	133	1	3	9	0	2610	1	63	1	2	71975	40728	976	900	958	10000	40100	72134	72142	72025	72114	72118
50204	72060	539	1	0	0	0	0	0	646	833	1	712	3	116	72020	802	44	5	71975	25	50915	40752	10175	40100	10000	617140	2729046	0	49	68911	71869	71934	65422	0	3	65755	50100	40200	10000	70200	10000	71923	35	1	1	40201	100	99	100	10000	30100	10000	100	10893	1	155	509	10683	288	11	888	68	83	10961	124	44	128	1	0	7	0	2610	1	57	1	1	71899	40708	910	1004	964	10000	40100	72148	72117	72050	71983	72074
50204	72217	540	1	0	0	0	0	0	652	793	2	672	1	144	71899	765	45	3	71726	25	50960	40812	10169	40100	10000	616837	2733361	0	49	69019	72027	72236	65549	0	3	65735	50100	40200	10000	70200	10000	72215	35	1	1	40201	100	99	100	10000	30100	10000	100	10903	1	147	502	10662	267	14	886	32	87	10947	119	45	131	1	1	3	0	2610	1	56	1	1	72025	40672	928	912	923	10000	40100	72022	72005	72008	72084	72054
50204	72140	541	1	0	0	0	0	0	628	787	1	712	1	112	72083	784	41	2	71940	25	50905	40808	10173	40100	10000	614518	2731997	0	49	68976	72176	72013	65556	0	3	65980	50100	40200	10000	70200	10000	72245	35	1	1	40201	100	99	100	10000	30100	10000	100	10875	1	152	487	10678	261	12	891	68	71	10931	126	46	116	1	0	3	0	2610	2	58	1	1	71959	40716	884	924	906	10000	40100	72072	72154	71918	72069	72198

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1802

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	19	1e	20	22	29	3a	3e	3f	40	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	71952	538	0	0	1	0	564	827	1	568	0	112	71694	838	71425	25	50680	40566	10123	40010	10000	631081	2718033	3	1	49	68494	71845	71837	65229	3	65434	50010	40020	10000	70020	10000	71745	35	1	1	40021	10	9	10	10000	30010	10000	10	10939	0	157	480	10665	282	12	923	68	36	10906	135	130	0	7	0	0	0	2520	2	65	0	1	2	71585	40540	968	1012	994	10000	40010	71807	71809	71862	71722	71914
50024	71592	538	0	0	0	0	880	841	1	592	0	128	71921	809	71566	25	50725	40586	10128	40010	10000	631200	2716593	2	1	49	68730	71974	71846	65267	3	65466	50010	40020	10000	70020	10000	71877	35	1	1	40021	10	9	10	10000	30010	10000	10	10932	0	134	492	10662	271	10	935	126	36	10960	116	132	0	3	0	0	0	2520	2	65	0	2	1	71737	40556	940	958	986	10000	40010	71830	71829	71813	71853	71728
50024	71591	537	0	0	0	0	526	825	1	720	0	100	71755	819	71675	25	50665	40506	10131	40010	10000	630956	2722312	3	0	49	68546	71935	71875	65231	3	65599	50010	40020	10000	70020	10000	71762	35	1	1	40021	10	9	10	10000	30010	10000	10	10951	0	165	492	10662	245	9	966	176	81	10936	123	125	0	8	0	0	0	2520	2	65	0	2	1	71673	40524	924	954	982	10000	40010	71742	71845	71769	71792	71562
50024	71864	539	0	0	0	0	501	860	1	704	0	92	71746	811	71601	25	50690	40550	10125	40010	10000	631145	2718705	2	0	49	68682	71742	71740	65206	3	65377	50010	40020	10000	70020	10000	71851	35	1	1	40021	10	9	10	10000	30010	10000	10	10935	0	158	491	10658	272	12	935	42	33	11015	124	124	0	3	0	0	0	2520	1	65	1	3	2	71595	40536	998	1000	1006	10000	40010	71669	71647	71930	72001	71881
50024	71599	539	0	1	0	0	569	830	1	768	0	144	71783	872	71513	25	50635	40518	10130	40010	10000	630836	2713615	3	0	49	68614	71748	71784	65261	3	65436	50010	40020	10000	70020	10000	71794	35	1	1	40021	10	9	10	10000	30010	10000	10	10913	0	145	519	10668	275	16	928	44	39	10944	124	145	3	3	0	0	0	2520	1	65	0	1	3	71663	40492	954	886	1026	10000	40010	71705	71633	71762	71883	71734
50024	71840	538	0	0	0	0	617	844	1	728	0	116	71698	806	71535	25	50695	40566	10119	40010	10000	630386	2716696	3	0	49	68750	71821	71722	65295	3	65546	50010	40020	10000	70020	10000	71808	35	1	1	40021	10	9	10	10000	30010	10000	10	10931	0	151	503	10662	280	12	910	52	45	10931	130	128	0	3	0	0	0	2520	1	65	0	2	1	71533	40516	986	926	936	10000	40010	71750	71875	71815	71699	71805
50024	71753	538	0	0	0	0	601	830	1	776	0	116	71737	863	71686	25	50675	40530	10125	40010	10000	630587	2706689	2	0	49	68836	71791	71925	65322	3	65461	50010	40020	10000	70020	10000	71803	35	1	1	40021	10	9	10	10000	30010	10000	10	10954	1	141	512	10688	272	10	931	68	39	10949	133	145	0	9	0	0	0	2520	2	65	0	1	2	71620	40568	940	1004	950	10000	40010	71861	71771	71796	71747	71692
50024	71860	537	0	0	0	0	528	855	1	736	0	124	71817	823	71450	25	50720	40518	10128	40010	10000	630359	2722183	2	0	49	68630	71678	71771	65172	3	65498	50010	40020	10000	70020	10000	71877	35	1	1	40021	10	9	10	10000	30010	10000	10	10985	0	162	495	10652	256	13	936	72	27	10945	134	126	0	3	0	0	0	2520	1	65	0	1	1	71646	40488	970	950	1052	10000	40010	71935	71845	71872	71765	71761
50024	71752	537	0	0	0	0	485	844	1	728	0	140	71720	820	71696	25	50695	40562	10141	40010	10000	630512	2718977	2	0	49	68626	71816	71839	65249	3	65558	50010	40020	10000	70020	10000	71649	35	1	1	40021	10	9	10	10000	30010	10000	10	10947	0	145	494	10670	263	13	925	48	33	10942	137	123	0	9	0	0	0	2520	3	65	0	1	1	71689	40484	958	944	844	10000	40010	71891	71825	71715	71914	71987
50024	71803	539	0	0	0	0	538	826	1	736	0	116	71892	804	71704	25	50665	40562	10139	40010	10000	630459	2716521	3	0	49	68808	71583	71676	65273	3	65616	50010	40020	10000	70020	10000	71843	35	1	1	40021	10	9	10	10000	30010	10000	10	10910	0	146	517	10657	275	14	944	50	21	10909	136	126	0	3	0	0	0	2520	2	65	0	2	1	71383	40488	940	900	932	10000	40010	71733	71803	71764	71970	71799

Test 3: throughput

Count: 8

Code:

  ldrb w0, [x6, #8]!
  ldrb w0, [x7, #8]!
  ldrb w0, [x8, #8]!
  ldrb w0, [x9, #8]!
  ldrb w0, [x10, #8]!
  ldrb w0, [x11, #8]!
  ldrb w0, [x12, #8]!
  ldrb w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3680

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29895	220	0	0	0	0	0	0	6800	831	1	704	110	116	29449	816	361	2042	1911	2131	25	160176	80173	80000	80120	80015	400869	1296318	0	57	49	26483	29284	29437	9542	0	6	9417	160135	80220	80020	80224	80024	29476	35	1	1	80201	100	99	41	100	80000	100	80000	100	80925	20	408	6355	86117	678	22	889	38	5230	86385	796	124	5302	5247	35	0	11	1	1	1	5117	2	16	2	1	29560	25	80076	551	611	119	80000	80100	29400	29581	29428	29523	29342
160204	29344	222	1	0	0	0	0	1	7300	819	1	632	115	104	29353	788	351	2135	1881	2270	25	160165	80174	80000	80120	80015	400843	1293913	0	69	49	26447	29445	29322	9319	0	6	9255	160134	80224	80020	80224	80028	29462	35	1	1	80201	100	99	40	100	80000	100	80000	100	80909	19	409	5855	85635	646	18	915	48	5352	86020	767	140	5404	5130	19	1	7	1	1	1	5117	2	16	4	2	29289	26	80089	623	585	101	80000	80100	29432	29603	29605	29422	29391
160204	29439	220	1	0	1	0	0	1	6946	804	1	688	105	88	29205	779	288	1765	2030	2206	25	160167	80170	80000	80100	80000	400783	1291374	0	63	49	26584	29329	29387	9118	0	3	9497	160100	80200	80000	80200	80000	29481	35	1	1	80201	100	99	31	100	80000	100	80000	100	80938	19	367	5894	85652	650	13	922	56	4910	86218	838	137	5326	5016	19	1	3	0	0	0	5110	3	16	4	4	29485	16	80053	510	554	97	80000	80100	29432	29550	29506	29414	29577
160204	29570	221	1	0	0	0	0	0	7323	787	1	776	130	144	29614	797	367	1771	1824	2066	25	160160	80171	80000	80100	80000	400754	1305364	0	67	49	26383	29357	29510	9369	0	3	9473	160100	80200	80000	80200	80000	29505	35	1	1	80201	100	99	25	100	80000	100	80000	100	80945	19	375	5981	86081	644	14	916	46	5745	86378	773	139	5019	5696	19	0	4	0	0	0	5110	3	16	3	2	29261	33	80064	581	607	106	80000	80100	29311	29744	29298	29336	29527
160204	29468	221	1	0	0	0	0	0	6632	799	1	712	113	132	29428	784	349	1778	2078	1779	25	160168	80157	80000	80100	80000	400776	1299980	0	79	49	26295	29675	29493	9559	0	3	9181	160100	80200	80000	80200	80000	29296	35	1	1	80201	100	99	41	100	80000	100	80000	100	80917	19	378	5712	85460	645	12	888	56	5457	86481	747	135	5068	5366	0	0	6	0	0	0	5110	3	16	2	3	29488	23	80064	455	638	121	80000	80100	29541	29321	29230	29362	29381
160204	29558	221	0	0	0	0	0	1	7224	854	1	776	106	140	29400	781	366	1850	2034	2266	25	160171	80150	80000	80100	80000	400849	1295788	0	68	49	26518	29333	29426	9318	0	3	9351	160100	80200	80000	80200	80000	29446	35	1	1	80201	100	99	35	100	80000	100	80000	100	80939	0	384	6363	85082	661	20	896	84	5629	85948	749	125	5170	4808	0	0	0	0	0	0	5110	3	16	3	3	29568	33	80065	650	553	97	80000	80100	29515	29317	29384	29339	29521
160204	29288	221	0	0	0	0	0	1	6865	807	1	752	120	100	29303	787	316	2064	2028	2087	25	160155	80163	80000	80100	80000	400790	1300906	0	81	49	26213	29469	29490	9333	0	3	9488	160100	80200	80000	80200	80000	29411	35	1	1	80201	100	99	25	100	80000	100	80000	100	80930	19	387	5601	85455	618	15	951	96	5717	86540	819	121	5657	5182	19	5	4	0	0	0	5110	3	26	3	2	29249	31	80063	612	521	105	80000	80100	29654	29632	29416	29533	29447
160204	29488	221	1	0	0	0	0	0	6672	818	1	720	117	88	29672	786	301	1953	1977	2048	25	160157	80159	80000	80100	80000	400777	1297904	0	63	49	26205	29573	29482	9158	0	3	9335	160100	80200	80000	80200	80000	29574	35	1	1	80201	100	99	37	100	80000	100	80000	100	80913	19	333	5529	85452	638	13	909	48	5681	86384	837	138	5375	5424	19	0	2	0	0	0	5110	3	16	3	3	29704	34	80066	652	508	94	80000	80100	29218	29371	29231	29305	29475
160204	29323	220	0	0	0	0	0	1	7325	803	1	736	98	132	29551	796	313	1922	1877	2245	25	160165	80164	80000	80100	80000	400772	1294028	0	78	49	26121	29438	29381	9339	0	3	9587	160100	80200	80000	80200	80000	29257	35	1	1	80201	100	99	39	100	80000	100	80000	100	80948	0	366	5813	85695	694	14	884	36	5093	86371	770	138	5140	5477	0	0	0	0	0	0	5110	4	16	4	4	29352	31	80060	632	559	114	80000	80100	29276	29494	29398	29556	29419
160204	29595	223	0	0	0	0	0	0	7242	798	1	704	107	96	29311	782	356	1785	1953	2142	25	160156	80161	80000	80100	80000	400804	1298167	0	61	49	26481	29559	29403	9121	0	3	9633	160100	80200	80000	80200	80000	29418	35	1	1	80201	100	99	40	100	80000	100	80000	100	80915	0	354	5851	85520	622	17	859	54	5138	86279	749	139	5475	5691	0	0	4	0	0	0	5110	3	16	3	3	29314	28	80058	562	539	118	80000	80100	29278	29408	29488	29645	29400

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3647

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29817	218	1	0	0	1	0	0	0	0	6827	0	798	1	704	99	144	29225	840	315	2023	2142	1888	25	160074	80076	80000	80010	80000	400301	1286314	0	0	0	59	49	26115	29330	29028	8938	0	3	9123	160010	80020	80000	80020	80000	29204	35	1	1	80021	10	9	12	10	80000	10	80000	0	10	80973	34	398	6136	85134	716	23	894	34	5794	86236	822	135	4833	4523	35	0	4	0	5020	0	0	14	16	0	0	11	8	29194	29	80053	352	383	87	80000	80010	29331	29103	29091	29233	29262
160024	29197	220	2	0	0	0	0	1	0	0	6987	0	781	1	680	91	92	29255	758	337	1957	2145	1867	25	160058	80076	80000	80010	80000	400335	1284339	0	0	0	73	49	26069	29365	29146	9099	0	3	9144	160010	80020	80000	80020	80000	29390	35	1	1	80021	10	9	7	10	80000	10	80000	0	10	80908	29	396	5444	85571	704	18	879	32	4852	85525	832	123	5218	4806	34	0	3	0	5020	0	0	8	16	0	0	10	10	29304	31	80048	349	341	87	80000	80010	29054	29145	29044	29228	29180
160024	29271	219	2	0	0	0	0	0	0	0	6666	0	796	1	704	90	124	29001	772	347	2063	1897	1871	25	160072	80065	80000	80010	80000	400360	1301078	0	0	0	67	49	26253	29086	29233	9035	0	3	9210	160010	80020	80000	80020	80000	29362	35	1	1	80021	10	9	5	10	80000	10	80000	0	10	80925	37	393	5477	85146	744	21	901	70	5024	86013	712	124	4755	5098	36	2	0	0	5020	0	0	9	16	0	0	12	7	29067	19	80064	299	368	96	80000	80010	29151	29051	29175	29206	29302
160024	29209	218	2	0	0	0	0	0	0	0	6638	0	845	1	720	106	100	29265	805	331	2136	1930	1827	25	160063	80071	80000	80010	80000	400318	1285501	0	0	0	55	49	26102	29188	29133	8970	0	3	9117	160010	80020	80000	80020	80000	29048	35	1	1	80021	10	9	4	10	80000	10	80000	0	10	80939	34	395	5146	85767	747	17	896	44	5046	86116	880	124	5023	4981	36	0	3	0	5020	0	0	10	16	0	0	9	9	29095	22	80057	349	339	104	80000	80010	29248	29354	29213	29092	29530
160024	29001	218	2	0	0	0	0	0	0	0	6397	0	786	1	688	95	136	29009	759	289	2388	2228	1965	25	160063	80063	80000	80010	80000	400307	1293947	0	0	0	59	49	26029	29264	29238	9053	0	3	9270	160010	80020	80000	80020	80000	29359	35	1	1	80021	10	9	10	10	80000	10	80000	0	10	80878	36	361	5635	85825	744	20	902	44	5313	85732	783	132	5072	5196	37	0	3	0	5020	0	0	7	16	0	0	11	9	29138	36	80068	346	342	81	80000	80010	29366	29155	29212	29191	29400
160024	28923	220	2	0	2	0	0	0	0	0	7416	0	821	1	704	80	156	28945	781	321	1981	1887	1855	25	160074	80064	80000	80010	80000	400372	1291370	0	0	0	54	49	26106	29297	29118	9029	0	3	9124	160010	80020	80000	80020	80000	29180	35	2	1	80021	10	9	7	10	80000	10	80000	0	10	80947	37	345	5458	86097	755	17	903	24	5264	85799	829	124	4929	5147	36	0	9	0	5020	0	0	8	16	0	0	8	9	29025	17	80058	297	279	89	80000	80010	29159	29152	29098	28962	29297
160024	29392	217	2	0	0	0	0	0	0	0	7182	0	812	1	728	89	148	29195	777	330	2106	2056	1928	25	160074	80065	80000	80010	80000	400355	1284127	0	0	0	49	49	26136	29103	29088	9257	0	3	9194	160010	80020	80000	80020	80000	28979	35	1	1	80021	10	9	2	10	80000	10	80000	0	10	80930	17	390	5500	85580	769	25	868	78	5115	85920	857	113	4290	4842	18	0	0	0	5020	0	0	12	16	0	0	9	7	29214	27	80054	308	329	80	80000	80010	29205	29165	28992	29256	28958
160024	29060	218	1	0	1	0	0	0	0	0	6882	0	831	1	768	96	128	29072	780	338	2137	2102	1980	25	160078	80062	80000	80010	80000	400285	1276521	0	0	0	55	49	26250	29098	29301	9160	0	3	9012	160010	80020	80000	80020	80000	29267	35	1	1	80021	10	9	10	10	80000	10	80000	1	10	80859	18	344	5533	85424	708	23	927	28	5062	85801	834	126	4727	5461	18	0	3	0	5020	0	0	8	16	0	0	6	9	28974	22	80062	383	414	95	80000	80010	29139	29282	29086	29137	29208
160024	29354	219	1	1	0	0	0	0	0	0	6830	0	782	1	728	94	136	29141	793	299	2205	1990	1776	25	160090	80068	80000	80010	80000	400332	1281576	0	0	0	64	49	26206	29226	29281	9510	0	3	9189	160010	80020	80000	80020	80000	29059	35	1	1	80021	10	9	15	10	80000	10	80000	0	10	80878	34	356	5427	85884	770	22	875	76	5030	86067	762	123	4652	4916	35	0	5	0	5020	0	0	10	16	0	0	9	7	28976	25	80060	348	337	88	80000	80010	29011	29290	29205	29022	29209
160024	29121	219	2	0	0	0	0	0	0	0	6890	0	807	1	704	93	108	29319	783	305	2230	2139	1913	25	160069	80071	80000	80010	80000	400342	1291831	0	0	0	44	49	26102	29204	29197	9048	0	3	9145	160010	80020	80000	80020	80000	29553	35	1	1	80021	10	9	8	10	80000	10	80000	0	10	80904	39	380	5406	85264	774	24	843	30	4985	85614	799	123	5204	5035	35	2	0	0	5020	0	0	8	16	0	0	7	10	29339	30	80052	366	348	105	80000	80010	28971	29263	29189	29324	29141

LDRB (pre-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations