Firestorm: LDR (unsigned offset, 32-bit) measurements

Code:

  ldr w0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	1	0	0	1	0	0	1	383	2	1	1	0	25	1000	1000	1000	14060	1	398	398	197	3	256	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1000	0	39	1038	6	0	39	43	73	1	16	1	1	371	0	0	0	1000	375	399	399	395	399
1004	374	3	0	0	0	1	0	0	1	383	2	1	0	19	25	1000	1000	1000	15274	1	394	394	221	3	232	1000	1000	1000	398	77	1	1	1001	1000	1000	1	1000	0	1038	1	0	1038	6	1	39	43	73	1	16	1	1	395	14	0	7	1000	375	399	375	395	399
1004	398	2	0	0	44	1	0	0	0	383	2	0	0	19	25	1000	1000	1000	15274	1	398	374	221	3	232	1000	1000	1000	394	56	1	1	1001	1000	1000	0	1000	43	1038	0	39	1000	6	0	39	0	73	1	16	1	1	371	0	14	4	1000	375	399	375	402	395
1004	398	3	0	0	45	0	0	0	1	383	2	1	0	16	25	1000	1000	1000	15037	1	398	398	221	3	232	1000	1000	1000	398	77	1	1	1001	1000	1000	1	1000	0	1038	0	39	1000	0	1	0	44	73	1	16	1	1	371	14	0	0	1000	395	399	399	399	399
1004	398	2	1	0	0	0	0	0	1	383	2	12	1	19	25	1000	1000	1000	14060	1	394	398	221	3	256	1000	1000	1000	374	77	1	1	1001	1000	1000	0	1000	0	1038	0	0	1038	6	1	38	0	73	1	16	1	1	391	14	0	7	1000	399	399	399	395	395
1004	374	3	1	0	45	1	0	0	0	383	2	12	1	19	25	1000	1000	1000	15208	1	398	398	197	3	252	1000	1000	1000	374	56	1	1	1001	1000	1000	0	1000	43	1038	0	0	1000	0	0	38	44	73	1	16	1	1	371	14	14	7	1000	399	399	399	395	375
1004	374	3	0	0	0	0	0	0	1	359	2	0	1	19	25	1000	1000	1000	14060	1	398	398	217	3	256	1000	1000	1000	394	77	1	1	1001	1000	1000	1	1000	0	1000	0	38	1039	0	0	38	0	73	1	16	1	1	395	14	14	0	1000	375	375	395	375	395
1004	398	3	0	0	0	0	0	0	1	359	2	1	1	19	25	1000	1000	1000	14060	1	398	374	197	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1000	0	38	1038	6	1	0	0	73	1	16	2	1	395	0	14	7	1000	399	375	375	395	375
1004	374	3	0	0	44	1	0	0	1	379	2	12	12	19	25	1000	1000	1000	14989	1	398	398	216	3	256	1000	1000	1000	374	56	1	1	1001	1000	1000	0	1000	43	1038	0	0	1038	6	1	39	43	73	1	16	1	1	371	14	14	4	1000	399	375	399	395	395
1004	374	3	1	1	45	1	0	0	0	379	2	1	1	16	25	1000	1000	1000	14989	1	398	374	221	3	256	1000	1000	1000	374	56	1	1	1001	1000	1000	0	1000	0	1038	0	0	1038	6	0	38	43	73	1	16	1	1	391	14	14	7	1000	399	375	399	375	375

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70059	526	1	0	0	0	1	0	197	1	0	70020	69805	59850	25	40108	30106	10002	30100	10000	616041	3342398	1	49	67179	70054	70054	64650	3	64963	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	0	10002	1	0	1	10000	1	0	1	0	0	0	0	2610	2	71	1	2	69820	30006	13	10	0	10000	30100	70055	70055	70052	70036	70052
40204	70051	524	0	0	0	0	0	0	1	0	0	70039	69791	59716	25	40104	30106	10001	30100	10000	616095	3342686	0	49	66980	70060	70060	64637	3	64963	40100	30200	10000	60200	10000	70057	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	0	2610	1	71	1	1	69817	30003	13	10	13	10000	30100	70064	70058	70061	70042	70062
40204	70041	525	1	1	1	0	0	0	1	0	0	70042	69782	59695	25	40104	30100	10000	30100	10000	616041	3341470	0	49	66974	70051	70051	64631	3	64957	40100	30200	10000	60528	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	0	1	1	10000	1	1	1	1	1	0	0	2610	1	71	1	1	69823	30006	13	0	0	10000	30100	70057	70036	70055	70055	70055
40204	70051	525	0	0	0	0	0	0	1	0	0	70039	69702	59719	25	40108	30106	10002	30100	10000	616078	3342686	0	49	66980	70060	70060	64656	3	64963	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	0	0	2610	1	71	1	1	69817	30003	0	13	0	10000	30100	70047	70061	70061	70042	70061
40204	70060	525	1	0	0	0	0	0	11	0	0	70045	69764	59715	49	40104	30103	10001	30100	10000	616014	3342398	0	49	66955	70054	70035	64650	3	64938	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	1	1	10000	0	1	0	1	1	0	0	2610	1	71	1	1	69804	30006	13	0	0	10000	30100	70052	70115	70057	70117	70055
40204	70054	524	0	0	0	0	0	0	6	0	0	70020	69805	59719	25	40108	30106	10002	30100	10000	616068	3341769	0	49	66980	70041	70041	64637	3	64963	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	0	2610	1	71	1	1	69817	30003	0	0	13	10000	30100	70062	70067	70061	70061	70042
40204	70041	525	1	1	1	0	0	0	2	0	0	70045	69787	59695	25	40104	30100	10000	30100	10000	616041	3342398	0	49	66955	70055	70035	64631	3	64938	40100	30200	10000	60200	10000	70038	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10001	3	3	1	10000	1	1	0	1	1	0	0	2610	1	71	1	1	69823	30003	13	13	10	10000	30100	70052	70055	70055	70052	70036
40204	70054	524	0	1	0	0	0	0	0	1	0	70039	69702	59701	25	40108	30106	10002	30100	10000	616095	3341769	0	49	66980	70060	70060	64656	3	64963	40294	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	0	0	2610	1	71	1	1	69814	30003	13	13	13	10000	30100	70061	70058	70058	70061	70061
40204	70060	525	1	0	0	0	0	1	2	0	0	70042	69764	59713	25	40104	30103	10001	30100	10000	616014	3342254	0	49	66974	70054	70051	64647	3	64938	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	1	1	10001	0	0	1	10000	0	1	0	1	0	0	0	2610	1	71	1	1	69823	30006	13	0	0	10000	30100	70052	70036	70036	70036	70055
40204	70054	525	0	0	0	0	0	0	1	0	0	70020	69702	59719	25	40108	30103	10001	30100	10000	616095	3341769	0	49	66961	70041	70057	64656	3	65018	40100	30200	10000	60200	10000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2610	1	71	1	1	69798	30000	0	10	13	10000	30100	70066	70061	70061	70061	70058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0065

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	525	0	0	0	0	0	0	1	1	0	0	70032	69728	59706	25	40010	30013	10002	30010	10000	616979	3342062	1	49	66955	70053	70047	64665	0	3	64980	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	225	10000	1	0	1	0	0	0	2521	3	71	3	3	69810	30003	6	0	6	10000	30010	70048	70048	70051	70048	70054
40024	70108	524	1	1	1	0	0	0	2	0	0	1	70038	69777	59712	25	40018	30016	10002	30010	10000	616988	3342062	1	49	66967	70053	70053	64671	0	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	243	10000	1	0	0	0	0	0	2521	3	71	3	3	69810	30003	6	6	6	10000	30010	70036	70036	70048	70036	70036
40024	70140	525	0	0	0	0	0	0	0	1	0	0	70020	69728	59706	25	40014	30013	10004	30010	10255	617051	3341566	1	49	66967	70047	70035	64665	0	3	64966	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	0	243	10000	1	0	1	0	0	0	2521	3	71	3	4	69810	30003	6	6	0	10000	30010	70036	70036	70036	70048	70048
40024	70123	525	0	0	0	0	0	0	0	1	0	0	70032	69728	59706	25	40014	30013	10002	30010	10000	617063	3342350	1	49	66961	70053	70053	64671	0	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	216	10000	0	0	0	0	0	0	2521	3	71	3	3	69810	30003	0	6	6	10000	30010	70048	70048	70048	70048	70087
40024	70048	525	0	0	0	0	1	1	0	1	0	0	70032	69728	59695	25	40014	30013	10002	30010	10000	617117	3342062	1	49	66967	70035	70047	64659	0	3	64978	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	252	10000	1	0	1	0	0	0	2521	4	71	3	3	69844	30003	6	0	6	10000	30010	70048	70048	70048	70048	70048
40024	70137	525	0	0	0	0	0	0	1	1	0	0	70020	69728	59706	25	40014	30013	10002	30010	10000	620227	3342686	1	49	66967	70053	70047	64665	0	3	64978	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	1	1	10000	0	0	228	10000	1	0	1	0	0	0	2521	3	71	3	3	69816	30006	0	6	6	10000	30010	70054	70054	70054	70054	70054
40024	70147	526	1	0	0	0	1	1	1	1	0	0	70038	69777	59712	25	40018	30016	10002	30010	10000	617018	3342734	1	49	66973	70053	70053	64671	0	3	64966	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	228	10000	1	0	1	0	0	0	2521	3	71	3	3	69810	30003	6	6	6	10000	30010	70036	70048	70048	70048	70048
40024	70129	525	0	0	0	0	0	0	1	1	0	0	70032	69728	59706	25	40010	30013	10001	30010	10000	626193	3342398	1	49	66967	70053	70053	64655	0	3	64978	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	1	0	0	10000	1	0	1	0	0	0	2521	3	71	3	4	69816	30006	6	6	6	10000	30010	70055	70057	70042	70054	70054
40024	70138	525	1	0	0	0	0	0	2	0	0	1	70038	69777	59701	25	40018	30016	10002	30010	10000	617076	3342350	1	49	66973	70053	70047	64659	0	3	64978	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	246	10000	0	0	1	0	0	0	2521	3	71	3	3	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70036
40024	70129	525	0	0	0	0	0	0	2	0	0	1	70026	69777	59712	25	40018	30016	10002	30010	10000	617045	3342350	1	49	66967	70041	70047	64665	0	3	64978	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	201	10000	1	0	1	0	0	0	2521	3	71	3	3	69810	30003	6	6	6	10000	30010	70048	70036	70048	70048	70036

Test 3: throughput

Count: 8

Code:

  ldr w0, [x6, #8]
  ldr w0, [x6, #8]
  ldr w0, [x6, #8]
  ldr w0, [x6, #8]
  ldr w0, [x6, #8]
  ldr w0, [x6, #8]
  ldr w0, [x6, #8]
  ldr w0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26738	200	0	0	0	0	0	66	0	0	26721	3	7	7	49	25	80100	100	80000	100	80000	500	1170981	1	49	23656	26714	26736	16849	3	16672	80100	200	80000	200	80000	26982	85	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	43	80058	0	11	0	147	80039	6	0	19	43	0	0	1	5110	1	16	1	3	26737	10	10	4	80000	100	26728	26708	26708	26728	26732
80204	26731	201	0	0	0	0	0	45	1	0	26712	0	12	0	0	25	80100	100	80000	100	80000	500	1166525	1	49	23627	26707	26727	16630	3	16685	80100	200	80000	200	80000	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	26	0	3	80039	6	1	0	0	0	0	1	5110	1	16	1	1	26704	10	10	4	80000	100	26728	26728	26728	26728	26830
80204	26736	200	0	0	0	0	0	0	1	0	26712	0	12	0	16	25	80100	100	80000	100	80000	500	1177670	1	49	23627	26727	26727	16650	3	16665	80100	200	80000	200	80000	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	1	0	42	80000	6	0	39	0	0	0	0	5110	1	16	1	1	26728	10	10	0	80000	100	26728	26708	26708	26708	26815
80204	26734	200	0	0	0	0	0	45	0	1	26712	2	12	0	16	25	80100	100	80000	100	80000	500	1172729	1	49	23627	26727	26707	16650	3	16685	80100	200	80193	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	2	0	63	80000	6	1	19	43	19	0	0	5110	1	16	1	1	26724	0	0	4	80000	100	26728	26728	26728	26708	26716
80204	26727	200	0	0	0	0	0	45	0	1	26712	2	0	12	16	25	80100	100	80000	100	80000	500	1165789	1	49	23647	26727	26727	16650	3	16665	80100	200	80000	200	80000	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80000	0	2	0	61	80039	6	0	59	43	19	0	0	5110	1	16	1	1	26733	13	13	5	80000	100	26738	26715	26738	26715	26739
80204	26740	200	1	1	0	0	0	45	0	1	26692	0	0	0	2	25	80100	100	80000	100	80000	500	1166525	1	49	23647	26707	26727	16630	3	16685	80100	200	80000	200	80000	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	0	0	42	80039	0	1	39	44	0	0	0	5110	1	16	1	1	26704	10	10	0	80000	100	26728	26728	26728	26728	26708
80204	26727	200	0	0	0	0	1	45	0	0	26712	0	0	0	0	25	80100	100	80000	100	80000	500	1166525	1	49	23647	26727	26707	16650	3	16685	80100	200	80000	200	80000	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	1	0	42	80039	6	1	39	0	0	0	0	5110	1	16	1	1	26704	0	0	4	80000	100	26708	26708	26728	26728	26735
80204	26727	201	0	0	0	0	0	44	0	1	26712	0	0	0	16	25	80100	100	80000	100	80000	500	1167231	1	49	23647	26707	26707	16650	3	16665	80100	200	80000	200	80000	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	5	0	3	80000	0	0	58	0	19	0	0	5110	1	16	2	1	26734	13	13	5	80000	100	26737	26715	26715	26715	26714
80204	26734	200	0	0	0	0	0	0	1	1	26712	2	0	0	16	25	80100	100	80000	100	80000	500	1167162	1	49	23627	26707	26727	16650	3	16665	80100	200	80000	200	80000	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	37	0	45	80000	6	1	39	0	0	0	0	5110	1	16	1	1	26704	10	10	7	80000	100	26708	26728	26728	26729	26733
80204	26727	200	0	0	0	0	0	45	1	0	26730	2	0	12	16	25	80100	100	80000	100	80000	500	1167231	1	49	23627	26727	26727	16630	3	16685	80100	200	80000	200	80000	26707	77	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	0	80039	0	0	0	90	80000	0	0	59	43	19	0	0	5110	1	16	1	1	26711	13	13	5	80000	100	26737	26737	26737	26737	26724

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	200	1	1	0	1	1	1	1	0	0	65	1	0	3	26722	3	7	7	24	25	80010	10	80000	10	80000	50	1171764	1	49	23656	26715	26737	16681	3	16716	80010	20	80000	20	80000	26714	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	0	80058	1	0	1	60	80040	6	0	19	43	19	1	5020	0	25	16	12	24	26712	13	13	5	80000	10	26742	26716	26737	26737	26737
80024	26736	200	0	1	1	0	1	0	0	0	0	69	0	0	2	26722	3	7	7	21	25	80010	10	80000	10	80000	50	1167106	1	49	23656	26736	26736	16682	3	16695	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	19	0	0	80059	0	0	1	61	80040	6	1	19	43	19	0	5020	0	21	16	21	22	26733	13	13	5	80000	10	26744	26746	26854	26738	26737
80024	26736	200	0	1	1	1	1	0	0	0	0	66	0	0	3	26721	3	0	7	20	25	80010	10	80000	10	80000	50	1167298	1	49	23635	26736	26714	16660	3	16717	80010	20	80000	20	80000	26715	85	1	1	80021	10	9	0	10	80000	10	80000	1	10	80020	19	43	0	80059	1	0	0	61	80000	0	0	19	43	19	1	5020	0	25	16	26	26	26711	0	13	5	80000	10	26746	26750	26738	26717	26715
80024	26714	200	0	1	1	0	1	0	1	0	0	66	0	0	2	26700	3	7	7	60	25	80010	10	80000	10	80000	50	1167219	1	49	23635	26736	26715	16660	3	16717	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	20	43	0	80059	1	0	0	21	80040	6	1	59	43	19	2	5020	0	26	16	25	26	26733	0	13	5	80000	10	26743	26737	26715	26715	26805
80024	26715	200	0	1	0	1	1	0	0	0	0	21	1	0	2	26722	2	0	0	19	25	80010	10	80000	10	80000	50	1166960	1	49	23656	26715	26737	16681	3	16716	80010	20	80000	20	80000	26736	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	19	43	0	80019	0	0	0	61	80040	0	0	58	43	19	1	5020	0	19	16	25	12	26734	13	0	5	80000	10	26743	26819	26740	26748	26715
80024	26736	200	0	1	1	1	0	0	0	0	0	21	1	0	3	26699	3	0	0	24	25	80010	10	80000	10	80000	50	1166960	1	49	23657	26715	26736	16683	3	16698	80010	20	80000	20	80000	26736	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	43	0	80059	1	0	1	64	80039	6	0	19	43	19	1	5020	0	25	16	25	25	26711	0	13	0	80000	10	26736	26715	26738	26737	26716
80024	26715	200	0	1	0	0	0	0	0	0	0	67	0	0	3	26721	3	0	7	20	25	80010	10	80000	10	80000	50	1173975	1	49	23656	26737	26736	16681	3	16716	80010	20	80000	20	80000	26737	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	43	0	80059	1	0	1	60	80042	6	1	19	43	19	2	5020	0	27	16	15	26	26735	13	0	0	80000	10	26751	26737	26716	26737	26716
80024	26715	200	0	1	1	0	1	0	0	0	0	67	1	0	3	26722	3	0	7	19	25	80010	10	80000	10	80000	50	1173975	1	49	23656	26737	26714	16659	3	16716	80010	20	80000	20	80000	26737	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	19	45	0	80019	1	0	2	21	80040	6	0	59	0	19	1	5020	0	20	16	24	12	26711	0	13	5	80000	10	26724	26737	26737	26737	26715
80024	26738	200	0	1	0	0	1	0	0	0	0	67	0	0	1	26722	2	0	0	0	25	80010	10	80000	10	80000	50	1168286	1	49	23657	26736	26737	16681	3	16716	80010	20	80000	20	80000	26715	85	1	1	80021	10	9	0	10	80000	10	80000	1	10	80019	19	43	0	80059	1	0	0	61	80042	0	1	59	43	19	0	5020	0	13	16	26	24	26733	13	13	0	80000	10	26747	26741	26728	26716	26737
80024	26736	200	0	1	1	0	1	1	1	0	0	66	0	0	0	26721	3	7	0	20	25	80010	10	80000	10	80000	50	1166960	1	49	23657	26736	26737	16681	3	16718	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	19	43	0	80059	0	0	1	21	80040	6	1	19	0	19	0	5020	0	16	16	26	13	26711	13	13	5	80000	10	26733	26716	26716	26738	26737

LDR (unsigned offset, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations