Firestorm: STRH (register) measurements

Code:

  strh w0, [x6, x7]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	551	4	0	3	0	536	16	16	0	25	1000	1000	1000	22424	1	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1002	0	5	1002	2	34	73	1	16	1	1	547	1000	551	551	552	543	552
1004	551	4	0	3	1	527	16	16	0	25	1000	1000	1000	22424	0	542	550	355	3	400	1000	1000	3000	542	549	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	1	527	16	16	0	25	1000	1000	1000	22424	0	542	542	355	3	400	1000	1000	3000	542	551	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	9	0	527	16	16	0	25	1000	1000	1000	22424	0	542	542	363	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	34	73	1	16	1	1	548	1000	551	552	543	543	543
1004	549	3	0	3	0	527	16	16	0	25	1000	1000	1000	22424	0	542	550	355	3	400	1000	1000	3000	542	549	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	0	535	16	16	0	25	1000	1000	1000	22808	0	542	542	363	3	400	1000	1000	3000	542	550	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	34	73	1	16	1	1	547	1000	552	550	543	543	543
1004	542	4	0	9	1	535	16	16	2	25	1000	1000	1000	22424	0	542	542	363	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1002	0	11	1002	2	34	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	9	0	527	16	16	0	25	1000	1000	1000	22424	0	542	542	363	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	9	0	527	16	16	0	25	1000	1000	1000	22424	1	542	551	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	1	527	16	16	0	25	1000	1000	1000	22424	0	542	550	355	3	400	1000	1000	3000	542	550	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	34	73	1	16	1	1	547	1000	552	543	543	543	543

Count: 8

Code:

  strh w0, [x6, x7]
  strh w0, [x6, x7]
  strh w0, [x6, x7]
  strh w0, [x6, x7]
  strh w0, [x6, x7]
  strh w0, [x6, x7]
  strh w0, [x6, x7]
  strh w0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	l2 tlb miss data (0b)	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	1	0	0	3	1	0	40034	0	16	0	25	80100	100	80000	100	80006	500	1839455	1	49	36962	40042	40040	29959	7	29994	80106	200	80016	200	240048	40042	31993	4	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	0	2	80002	2	34	1	1	1	5118	0	16	40039	80000	100	40051	40043	40050	40041	40050
80204	40042	300	0	0	0	0	0	0	40036	0	16	0	25	80100	100	80000	100	80007	500	1839858	1	49	36962	40042	40040	29959	7	29992	80107	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80000	0	0	12	80000	2	0	1	1	1	5118	0	16	40037	80000	100	40043	40051	40041	40041	40041
80204	40042	300	0	0	0	0	1	0	40027	16	0	0	25	80100	100	80000	100	80007	500	1839378	1	49	36962	40040	40042	29961	7	29994	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	0	0	80000	2	34	1	1	1	5118	0	16	40037	80000	100	40043	40051	40043	40041	40043
80204	40040	299	0	0	0	3	0	0	40035	0	0	0	25	80100	100	80000	100	80007	500	1839455	1	49	36962	40042	40042	29959	7	29994	80107	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80002	0	0	5	80000	2	34	1	1	1	5118	0	16	40039	80000	100	40043	40043	40043	40043	40050
80204	40040	300	0	0	0	6	0	0	40027	16	16	0	25	80100	100	80000	100	80007	500	1839455	1	49	36962	40040	40040	29969	7	29994	80107	200	80016	200	240048	40051	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80000	0	0	0	80000	0	34	1	1	1	5118	0	16	40046	80000	100	40050	40043	40051	40043	40043
80204	40040	300	0	0	0	0	0	0	40034	0	0	0	25	80100	100	80000	100	80006	500	1839378	1	49	36960	40040	40040	29961	7	29992	80107	200	80016	200	240048	40042	40596	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80000	0	0	0	80000	2	34	1	1	1	5118	0	16	40039	80000	100	40041	40041	40043	40043	40050
80204	40042	300	0	0	0	6	1	0	40034	16	0	0	25	80100	100	80000	100	80007	500	1839378	1	49	36962	40049	40049	29959	7	29994	80106	200	80016	200	240048	40043	32004	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80002	0	0	2	80002	2	34	1	1	1	5118	0	16	40039	80000	100	40041	40041	40043	40043	40041
80204	40042	299	0	0	0	0	1	0	40025	0	16	0	25	80100	100	80000	100	80007	500	1839455	1	49	36960	40040	40042	29961	7	30002	80106	200	80016	200	240048	40043	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	0	2	80002	0	34	1	1	1	5118	0	16	40037	80000	100	40051	40043	40051	40041	40041
80204	40040	300	0	0	0	0	1	0	40027	16	0	0	25	80100	100	80000	100	80007	500	1839378	1	49	36971	40042	40040	29959	7	30003	80106	200	80016	200	240048	40043	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80000	0	0	2	80000	2	34	1	1	1	5118	0	16	40037	80000	100	40043	40051	40041	40041	40043
80204	40040	300	0	0	0	0	1	0	40035	0	16	0	25	80100	100	80000	100	80007	500	1839887	1	49	36962	40042	40051	29959	7	29994	80106	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80000	0	0	0	80002	2	34	1	1	1	5118	0	16	40039	80000	100	40043	40041	40043	40041	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40058	300	1	1	1	1	6	20	0	0	1	40043	16	16	2	25	80010	10	80000	10	80000	50	1840220	1	49	36978	40053	40058	29982	3	30038	80010	20	80000	20	240000	40058	40058	1	1	80021	10	9	10	80000	10	80000	10	80016	16	36	0	1	80016	0	1	18	80002	16	36	14	1	0	0	5020	0	6	6	16	2	0	6	3	40044	0	80000	10	40059	40053	40060	40054	40048
80024	40052	300	1	0	0	1	0	19	1	0	1	40035	16	16	3	25	80010	10	80000	10	80000	50	1840316	1	49	36971	40059	40060	29993	3	30032	80010	20	80000	20	240000	40052	40052	1	1	80021	10	9	10	80000	10	80000	10	80015	15	36	0	0	80014	0	2	14	80000	14	36	14	2	0	0	5020	0	5	4	16	0	0	4	3	40050	0	80000	10	40051	40048	40052	40048	40061
80024	40059	299	1	1	0	1	0	19	1	0	1	40044	16	0	5	25	80010	10	80000	10	80000	50	1839692	1	49	36972	40050	40047	29987	3	30039	80010	20	80000	20	240000	40047	40607	1	1	80021	10	9	10	80000	10	80000	10	80015	15	35	0	2	80016	0	1	20	80002	16	36	14	0	0	0	5020	0	5	4	16	0	0	2	4	40055	0	80000	10	40059	40050	40048	40048	40053
80024	40060	300	1	0	1	1	0	19	1	0	1	40037	0	16	2	25	80010	10	80000	10	80000	50	1839692	1	49	36967	40047	40061	29993	3	30032	80010	20	80000	20	240000	40058	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	14	36	0	2	80016	0	1	19	80002	14	36	14	2	0	0	5020	0	5	4	16	0	0	4	2	40044	0	80000	10	40060	40048	40059	40051	40054
80024	40060	300	1	1	1	1	0	21	0	0	1	40043	16	0	5	25	80010	10	80000	10	80000	50	1840244	1	49	36979	40047	40047	29987	3	30039	80010	20	80000	20	240000	40052	40052	1	1	80021	10	9	10	80000	10	80000	10	80015	14	36	0	0	80016	0	0	14	80002	16	0	14	1	0	0	5020	0	5	4	16	0	0	4	2	40044	0	80000	10	40059	40048	40049	40048	40060
80024	40052	300	1	1	1	1	0	19	1	0	1	40035	0	16	0	25	80010	10	80000	10	80000	50	1839788	1	49	36971	40059	40049	29995	3	30027	80010	20	80000	20	240000	40059	40060	1	1	80021	10	9	10	80000	10	80000	10	80016	15	36	0	1	80016	0	0	14	80000	16	0	14	1	0	0	5020	0	5	4	16	0	0	4	2	40049	0	80000	10	40053	40059	40053	40060	40051
80024	40047	300	1	1	1	0	0	19	0	0	1	40032	0	0	6	25	80010	10	80000	10	80000	50	1840220	1	49	36978	40052	40058	29994	3	30039	80010	20	80000	20	240000	40052	40047	1	1	80021	10	9	10	80000	10	80000	10	80014	14	36	0	0	80014	0	0	18	80002	16	36	14	0	0	0	5020	0	5	3	16	0	0	2	4	40055	0	80000	10	40048	40058	40053	40059	40048
80024	40047	300	1	0	0	0	0	17	1	0	1	40036	16	16	6	25	80010	10	80000	10	80000	50	1840246	1	49	36967	40059	40059	29993	3	30031	80010	20	80000	20	240000	40463	40058	1	1	80021	10	9	10	80000	10	80000	10	80015	15	36	0	1	80016	0	0	18	80002	14	36	14	0	0	1	5020	0	5	6	16	0	0	4	3	40044	0	80000	10	40051	40051	40060	40053	40060
80024	40050	300	1	1	0	1	0	19	0	0	1	40032	0	16	0	25	80010	10	80000	10	80000	50	1839693	1	49	36967	40058	40058	29994	3	30031	80010	20	80000	20	240000	40059	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	16	36	0	0	80016	0	1	18	80000	16	36	14	1	0	0	5020	0	5	4	16	0	0	2	4	40044	0	80000	10	40060	40051	40048	40048	40053
80024	40047	300	1	0	1	1	0	20	1	0	1	40043	16	0	5	25	80010	10	80000	10	80000	50	1840268	1	49	36979	40052	40047	29993	3	30039	80010	20	80000	20	240000	40057	40060	1	1	80021	10	9	10	80000	10	80000	10	80016	15	0	2	1	80016	0	1	18	80002	16	36	14	0	0	0	5020	0	5	2	16	2	1	5	2	40054	0	80000	10	40051	40060	40053	40048	40061

STRH (register)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations