Firestorm: LDRH measurements

Code:

  ldrh w0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	2	0	0	0	1	0	1	374	2	18	0	0	25	1000	1000	1000	14980	389	377	212	3	247	1000	1000	1000	377	71	1	1	1001	1000	1000	0	1000	39	1000	0	35	1035	6	1	0	39	73	1	16	1	1	386	0	0	2	1000	390	375	390	392	390
1004	389	3	0	0	0	0	0	1	374	2	0	18	0	25	1000	1000	1000	14060	389	389	212	3	249	1000	1000	1000	374	56	1	1	1001	1000	1000	0	1000	39	1035	0	0	1035	6	1	0	39	73	1	16	1	1	386	0	0	2	1000	375	390	375	390	395
1004	394	3	0	0	41	1	0	0	359	0	18	18	16	25	1000	1000	1000	14838	394	394	216	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	0	1039	0	0	1000	6	0	36	39	73	1	16	1	1	386	6	6	0	1000	390	395	375	395	390
1004	374	3	0	0	0	1	0	0	374	0	18	12	0	25	1000	1000	1000	14838	389	389	217	3	247	1000	1000	1000	394	71	1	1	1001	1000	1000	1	1000	0	1035	0	44	1035	6	0	35	39	73	1	16	1	1	371	6	6	2	1000	390	390	390	390	390
1004	389	3	0	0	41	1	0	1	374	2	18	0	0	25	1000	1000	1000	14989	389	389	217	3	232	1000	1000	1000	389	56	1	1	1001	1000	1000	1	1000	39	1000	0	36	1000	6	0	35	0	73	1	16	1	1	371	6	6	2	1000	390	375	390	375	392
1004	374	3	0	0	41	1	0	1	374	2	0	18	12	25	1000	1000	1000	14838	391	374	212	3	247	1000	1000	1000	374	71	1	1	1001	1000	1000	0	1000	39	1035	0	35	1000	6	0	35	39	73	1	16	1	1	386	6	0	4	1000	375	375	375	375	390
1004	389	3	1	0	41	0	0	1	374	0	12	18	12	25	1000	1000	1000	14060	389	389	212	3	247	1000	1000	1000	389	56	1	1	1001	1000	1000	0	1000	0	1035	0	35	1035	6	1	35	39	73	1	16	1	1	386	0	0	2	1000	375	375	375	375	390
1004	389	2	0	0	0	1	0	1	359	2	18	18	12	25	1000	1000	1000	14060	374	389	212	3	247	1000	1000	1000	389	56	1	1	1001	1000	1000	1	1000	39	1035	0	0	1035	0	1	39	39	73	1	16	1	1	387	6	6	2	1000	375	395	392	390	390
1004	389	2	0	0	41	1	0	0	359	2	12	0	12	25	1000	1000	1000	14303	394	389	197	3	232	1000	1000	1000	374	56	1	1	1001	1000	1000	0	1000	0	1035	0	35	1035	6	1	0	39	73	1	16	1	1	386	10	6	2	1000	392	390	390	390	375
1004	402	3	1	0	41	1	0	1	374	2	0	0	12	25	1000	1000	1000	14838	394	374	212	3	232	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	0	1000	0	0	1000	6	0	0	39	73	1	16	1	1	386	6	6	2	1000	390	378	390	375	390

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	1	1	1	1	0	0	0	256	0	1	0	0	0	70042	69788	59701	25	40108	30103	10002	30100	10000	616078	3342542	49	66980	70041	70060	64696	3	64960	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	0	0	1	10000	1	1	0	1	1	0	2610	2	71	1	1	69804	30003	10	10	10	10000	30100	70042	70058	70163	70175	70042
40204	70041	525	1	0	0	1	1	0	0	19	0	0	0	0	0	70045	69702	59719	25	40108	30106	10002	30100	10000	616095	3342686	49	66961	70041	70060	64650	3	64944	40100	30200	10000	60200	10000	70065	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	3	1	10003	0	0	2	1	10000	0	1	1	1	1	0	2610	1	71	1	1	69823	30006	13	13	0	10000	30100	70042	70058	70061	70061	70061
40204	70060	526	1	0	0	0	0	0	0	38	0	0	0	0	0	70045	69791	59716	25	40108	30106	10002	30100	10000	616078	3342686	49	66980	70060	70041	64637	3	64944	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	0	0	1	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69804	30006	0	10	0	10000	30100	70061	70061	70042	70061	70061
40204	70060	525	1	1	1	0	0	0	0	41	0	0	0	0	0	70045	69791	59719	25	40104	30106	10001	30100	10000	616095	3342542	49	66961	70060	70060	64748	17	64990	40100	30200	10000	60200	10000	70065	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10003	0	0	1	1	10000	1	1	0	1	1	0	2610	1	71	1	1	69804	30003	0	10	13	10000	30100	70058	70058	70042	70042	70102
40204	70058	525	1	0	0	0	0	0	0	56	0	0	0	0	0	70042	69788	59701	25	40104	30106	10002	30100	10000	616078	3342686	49	66980	70060	70060	64728	3	64960	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	0	10001	0	0	0	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69895	30006	0	13	13	10000	30100	70061	70042	70061	70042	70061
40204	70041	525	1	1	0	0	0	0	0	41	0	1	0	0	0	70045	69791	59719	25	40108	30106	10002	30100	10000	616078	3342686	49	66961	70060	70057	64714	3	64944	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	3	1	10001	0	0	0	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69823	30006	0	0	10	10000	30100	70061	70042	70167	70061	70042
40204	70060	525	1	0	1	0	0	0	0	26	0	0	0	0	2	70045	69788	59719	25	40108	30106	10002	30100	10000	616078	3342542	49	66977	70060	70041	64724	3	64944	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	3	1	10001	0	0	0	1	10000	1	1	1	1	2	0	2610	1	71	1	1	69820	30006	13	10	0	10000	30100	70042	70061	70061	70061	70042
40204	70060	525	1	0	0	0	0	0	0	2	0	1	0	0	0	70042	69704	59721	25	40108	30106	10002	30100	10000	616095	3342830	49	66978	70436	70057	64770	3	64960	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	0	10001	0	0	2	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69823	30006	13	13	10	10000	30100	70061	70061	70042	70061	70061
40204	70057	524	1	1	1	0	1	0	0	7	0	0	0	0	0	70026	69791	59719	25	40108	30106	10002	30100	10000	616095	3342686	49	66961	70060	70060	64720	3	64944	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	0	0	1	1	10000	0	1	0	1	1	0	2610	1	71	1	1	69823	30006	13	13	13	10000	30100	70061	70042	70058	70042	70042
40204	70060	525	1	1	1	0	1	0	0	68	0	1	0	0	0	70045	69791	59701	25	40108	30106	10001	30100	10000	616078	3342686	49	66980	70041	70057	64738	3	64944	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	1	0	10001	0	0	1	1	10000	1	1	0	1	0	0	2610	1	71	1	1	69804	30006	10	10	13	10000	30100	70042	70061	70058	70061	70061

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	0	0	0	0	0	394	0	0	0	70032	69744	59695	25	40014	30032	10002	30582	10000	626019	3342206	0	49	66970	70050	70035	64760	3	64981	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	2	1	10001	0	0	1	10000	1	1	0	1	0	1	2520	5	71	2	1	69813	30000	6	6	6	10000	30010	70036	70051	70051	70036	70051
40024	70050	524	0	0	0	0	0	4	1	0	0	70020	69743	59695	25	40026	30013	10000	30010	10000	617068	3341470	0	49	66967	70035	70047	64761	3	64960	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	1	71	1	1	69819	30006	6	0	6	10000	30010	70057	70062	70042	70042	70042
40024	70056	524	1	0	0	1	0	40	1	0	0	70020	69728	59709	25	40014	30010	10000	30010	10000	617068	3342206	0	49	66970	70035	70035	64719	3	64981	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	2	0	10003	0	2	1	10000	0	1	1	1	0	0	2520	1	71	1	1	69798	30000	6	6	0	10000	30010	70048	70036	70048	70048	70048
40024	70047	525	0	0	0	0	0	49	1	0	0	70032	69760	59695	25	40010	30013	10001	30010	10000	616952	3342062	0	49	66970	70035	70035	64741	3	64975	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	1	71	1	1	69816	30006	6	6	6	10000	30010	70057	70042	70057	70057	70042
40024	70041	524	1	1	1	1	0	24	1	0	0	70035	69743	59695	25	40010	30013	10001	30010	10000	617068	3342206	0	49	66970	70035	70055	64775	3	64975	40010	30020	10000	60020	10000	70050	35	1	1	40022	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	3	10000	1	0	1	0	0	0	2520	1	71	1	1	69810	30003	6	0	6	10000	30010	70048	70048	70048	70048	70048
40024	70050	524	0	0	0	0	0	56	1	0	1	70041	69780	59701	25	40018	30013	10002	30010	10000	617036	3342494	0	49	66976	70041	70056	64732	3	64975	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10015	0	0	0	10000	1	0	1	0	0	0	2520	2	71	1	1	69813	30003	0	9	9	10000	30010	70036	70036	70051	70036	70036
40024	70035	525	0	0	0	0	0	443	0	0	0	70041	69702	59701	25	40018	30016	10001	30010	10000	616995	3342494	0	49	66961	70041	70056	64691	3	64960	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	0	2520	1	71	1	1	69810	30003	6	0	6	10000	30010	70051	70036	70052	70051	70036
40024	70050	525	0	0	0	0	0	1	1	0	0	70026	69702	59701	25	40014	30016	10002	30010	10000	617036	3341769	0	49	66973	70041	70041	64742	3	64960	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	1	71	1	2	69813	30003	9	6	0	10000	30010	70036	70036	70036	70048	70051
40024	70047	525	0	0	0	0	0	55	1	0	0	70020	69760	59709	25	40014	30013	10001	30010	10000	617068	3342206	0	49	66955	70050	70035	64725	3	64975	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	2520	1	71	1	1	70032	30000	9	6	9	10000	30010	70048	70036	70051	70051	70056
40024	70050	524	0	0	0	0	0	80	0	0	1	70038	69777	59715	25	40018	30016	10002	30010	10000	617036	3342494	0	49	66976	70056	70056	64722	3	64975	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	2520	1	71	1	1	69810	30003	6	6	6	10000	30010	70048	70048	70036	70048	70048

Test 3: throughput

Count: 8

Code:

  ldrh w0, [x6]
  ldrh w0, [x6]
  ldrh w0, [x6]
  ldrh w0, [x6]
  ldrh w0, [x6]
  ldrh w0, [x6]
  ldrh w0, [x6]
  ldrh w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26727	200	1	0	0	108	0	0	1	26692	2	12	12	16	25	80100	100	80000	100	80000	500	1167231	0	49	23649	26738	26707	16654	3	16685	80100	200	80000	200	80000	26731	77	2	1	80201	100	99	100	80000	100	80000	1	100	80000	43	0	80038	0	0	0	80038	6	1	0	44	19	5110	1	16	1	1	26704	14	10	7	80000	100	26732	26708	26708	26732	26732
80204	26731	200	0	0	0	0	1	0	0	26692	2	1	1	19	25	80100	100	80000	100	80000	500	1168312	0	49	23651	26838	26736	16636	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	0	80039	0	0	39	80039	6	1	39	43	19	5110	1	16	1	1	26728	14	14	7	80000	100	26732	26732	26708	26732	26732
80204	26731	200	0	0	0	60	0	0	1	26716	0	1	1	16	25	80100	100	80000	100	80000	500	1165556	0	49	23651	26833	26716	16636	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	0	80038	0	0	38	80038	6	1	38	43	19	5110	1	16	1	1	26728	10	10	4	80000	100	26732	26732	26732	26708	26732
80204	26707	201	0	0	0	45	1	0	0	26716	2	1	1	0	25	80100	100	80000	100	80000	500	1168312	0	49	23627	26736	26736	16654	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	0	80000	0	0	39	80000	6	0	39	0	19	5110	1	16	1	1	26728	0	14	7	80000	100	26708	26732	26732	26732	26732
80204	26707	201	0	0	0	89	1	0	1	26712	2	1	0	0	25	80100	100	80000	100	80000	500	1165556	0	49	23627	26835	26733	16663	3	16665	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	0	80038	0	0	38	80038	6	1	0	44	0	5110	1	16	1	1	26728	0	10	4	80000	100	26728	26732	26732	26732	26708
80204	26731	201	0	0	0	92	0	0	0	26692	2	1	1	19	25	80100	100	80000	100	80000	500	1167127	0	49	23651	26743	26738	16652	3	16696	80100	200	80000	200	80000	26731	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	0	80038	0	0	38	80039	6	1	39	44	19	5110	1	16	1	1	26728	14	10	7	80000	100	26708	26708	26732	26732	26732
80204	26732	200	0	0	0	95	0	0	0	26712	2	1	12	19	25	80100	100	80000	100	80000	500	1167127	0	49	23627	26845	26710	16661	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	1	100	80000	43	0	80038	0	0	38	80038	6	1	39	43	19	5110	1	16	1	1	26704	14	0	7	80000	100	26732	26732	26732	26708	26732
80204	26731	200	0	0	0	24	0	0	1	26716	2	1	1	0	25	80100	100	80000	100	80000	500	1167127	0	49	23627	26751	26710	16724	3	16667	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	0	80038	0	1	0	80000	6	1	0	44	0	5110	1	16	1	1	26704	14	10	7	80000	100	26732	26732	26708	26732	26708
80204	26731	200	0	0	0	59	1	0	1	26716	0	1	1	19	25	80100	100	80000	100	80000	500	1166525	0	49	23651	26832	26713	16758	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80038	0	1	38	80038	6	0	39	44	0	5110	1	16	1	1	26704	14	0	7	80000	100	26732	26732	26732	26708	26732
80204	26707	200	0	0	0	92	0	0	1	26692	2	12	1	19	25	80100	100	80000	100	80000	500	1167127	0	49	23651	26839	26715	16637	3	16689	80100	200	80000	200	80000	26731	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80038	0	0	38	80000	0	1	0	0	0	5110	1	16	1	1	26704	14	14	4	80000	100	26732	26708	26732	26732	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26733	200	1	0	1	1	0	0	95	1	0	3	26717	2	18	0	16	25	80010	10	80000	10	80000	50	1167648	1	0	49	23652	26831	26715	16741	3	16712	80010	20	80000	20	80000	26714	81	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80035	0	0	0	35	80035	6	0	35	39	0	0	0	5020	0	0	2	16	0	2	2	26730	9	9	2	80000	10	26733	26733	26733	26733	26734
80024	26733	200	1	1	0	1	1	0	101	1	0	2	26717	3	18	18	16	25	80010	10	80000	10	80000	50	1167660	0	0	49	23635	26844	26737	16685	3	16712	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	21	42	80057	0	0	1	59	80038	6	0	19	42	19	1	0	5020	0	0	2	16	0	2	2	26729	9	9	2	80000	10	26733	26733	26733	26733	26716
80024	26733	200	1	0	1	1	0	0	116	1	0	3	26717	2	18	18	0	25	80010	10	80000	10	80000	50	1170204	0	0	49	23652	26838	26739	16667	3	16695	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	42	80057	1	0	2	59	80038	6	0	58	42	19	0	1	5020	5	0	2	16	0	2	2	26729	9	9	2	80000	10	26733	26733	26733	26733	26734
80024	26733	200	1	0	1	1	0	0	98	0	0	1	26717	2	18	18	16	25	80010	10	80000	10	80000	50	1168791	0	0	49	23652	26844	26738	16789	3	16713	80010	20	80000	20	80000	26714	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	19	42	80057	1	0	1	21	80000	6	1	19	42	19	0	0	5020	5	0	2	16	0	2	2	26741	9	0	2	80000	10	26716	26734	26734	26734	26716
80024	26732	200	1	0	0	1	0	0	71	0	0	0	26717	2	18	18	16	25	80010	10	80000	10	80000	50	1167660	0	0	49	23652	26811	26733	16736	3	16712	80010	20	80000	20	80000	26733	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	42	80019	1	0	0	59	80038	6	1	57	0	18	0	0	5020	0	0	2	16	0	2	2	26712	9	9	2	80000	10	26734	26733	26736	26733	26733
80024	26732	200	1	1	1	1	0	0	65	1	0	1	26717	0	18	18	16	25	80010	10	80000	10	80000	50	1166960	0	5	49	23634	26824	26741	16677	3	16712	80010	20	80000	20	80000	26733	64	1	1	80021	10	9	10	80000	10	80000	0	10	80019	21	42	80057	1	0	2	59	80038	6	1	19	42	19	2	0	5020	5	0	2	16	0	2	2	26730	9	9	2	80000	10	26733	26733	26733	26733	26716
80024	26733	200	1	1	0	1	0	0	65	1	0	2	26717	2	18	18	1	25	80010	10	80000	10	80000	50	1170204	0	0	49	23652	26835	26732	16810	3	16713	80010	20	80000	20	80000	26714	64	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	80019	0	1	1	59	80038	6	1	57	42	19	2	0	5020	0	0	2	16	0	2	2	26711	9	9	2	80000	10	26733	26733	26733	26734	26733
80024	26741	200	1	1	1	0	0	0	107	1	0	2	26717	0	18	18	16	25	80010	10	80000	10	80000	50	1167660	1	0	49	23652	26852	26738	16683	3	16714	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	42	80019	1	0	1	60	80038	6	1	57	42	19	0	0	5020	0	4	2	16	0	2	2	26729	9	0	2	80000	10	26733	26733	26733	26889	26715
80024	26732	200	1	1	0	0	0	0	87	1	0	3	26717	2	18	18	16	25	80010	10	80000	10	80000	50	1167660	0	5	49	23652	26828	26733	16691	3	16706	80010	20	80000	20	80000	26732	64	1	1	80021	10	9	10	80000	10	80000	0	10	80019	22	41	80057	1	0	0	59	80000	0	1	19	42	19	1	0	5020	5	0	2	16	0	2	2	26729	9	0	2	80000	10	26716	26716	26716	26734	26733
80024	26732	200	1	1	0	0	1	1	15	1	0	0	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167599	1	5	49	23652	26917	26750	16842	3	16695	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	80057	0	0	0	59	80038	6	1	57	42	19	2	0	5020	5	4	2	16	0	2	2	26711	9	0	2	80000	10	26733	26733	26733	26733	26734

LDRH

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations