Firestorm: PACIZA measurements

Code:

  paciza x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	3	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	12	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	1	3	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	71	0	103	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	3	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	12	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	109	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  paciza x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	677	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	0	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70054	678	0	0	0	0	0	0	0	0	103	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70054	68480	3	68674	10200	10200	10200	0	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	679	0	0	0	0	0	0	12	0	61	59815	25	10200	10200	10200	1808330	1	49	0	0	70029	70029	68480	3	68674	10200	10200	10200	0	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	1	69875	10100	10100	70030	70030	70030	70030	70030
10204	70029	678	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	0	70029	912	1	1	10201	100	99	10100	0	1	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	679	1	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	0	70029	912	1	1	10201	100	99	10100	0	1	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	679	0	0	0	0	0	0	0	0	319	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	0	70029	912	1	1	10201	100	99	10100	0	1	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	678	0	0	0	0	0	0	3	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	0	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	679	0	0	0	0	0	0	0	216	103	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	0	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	770	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	674	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	0	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	689	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	0	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	617	0	0	0	0	0	0	0	0	117	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	0	3	79	2	3	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	621	0	0	0	0	0	0	0	0	578	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	656	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	1	0	0	0	0	0	0	0	104	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	0	0	12	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	3	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10080	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	621	1	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030

Test 3: throughput

Count: 8

Code:

  paciza x0
  paciza x1
  paciza x2
  paciza x3
  paciza x4
  paciza x5
  paciza x6
  paciza x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80040	663	0	0	0	39	0	192	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	3	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	643	0	0	0	12	0	742	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	3	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	644	0	0	0	12	0	2280	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	770	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	703	0	0	0	0	0	467	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	698	0	0	0	75	0	230	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	12	0	337	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	1274	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80229	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	703	0	0	0	0	0	251	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	12	0	637	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	80041	699	0	0	0	0	0	0	0	0	163	25	80020	80020	80020	400100	1	0	49	76955	80035	80035	69988	3	70006	80020	80020	80080	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	5	1	1	25	0	1	1	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	5	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	5	1	1	25	0	1	1	80024	80010	0	80010	80080	80081	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	5	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	5	1	1	25	0	1	1	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	5	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	5	1	2	25	0	1	1	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	701	0	0	0	0	0	0	0	0	510	25	80020	80020	80020	400100	1	5	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	5	1	1	25	0	1	1	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	5	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	3	0	5020	5	0	1	25	0	1	1	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	697	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	5	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	1	0	0	0	5020	5	0	1	25	0	2	1	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	703	0	0	0	0	0	0	0	0	63	25	80020	80020	80020	400100	0	5	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	3	0	5020	5	0	1	25	0	1	1	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	705	0	0	0	0	0	12	0	0	77	43	80020	80020	80020	400100	1	5	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	0	0	1	25	0	1	1	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	701	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	5	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	5	1	2	25	0	1	1	80074	80010	0	80010	80036	80036	80036	80036	80036

PACIZA

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations