Firestorm: LDRSW (pre-index) measurements

Code:

  ldrsw x0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	20	22	23	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1054	7	0	0	0	1	0	85	30	1	0	2	4	1027	12	1	9	5	29	25	2000	1000	1000	1000	1000	52792	45828	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1036	0	0	86	1058	8	0	38	12	147	1056	28	7	39	55	0	73	1	16	1	1	1019	1000	25	18	0	1000	1000	1044	1041	1041	1041	1041
2004	1042	8	0	1	0	0	0	117	22	0	0	1	0	1025	0	1	5	17	25	25	2000	1000	1000	1000	1000	52816	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1026	0	2	96	1045	7	0	26	10	36	1062	58	8	24	55	0	73	1	16	1	1	1037	1000	36	39	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	1	0	0	0	67	20	0	0	1	0	1025	16	0	11	4	23	25	2000	1000	1000	1000	1000	52828	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1056	44	1	1	1001	1000	1000	0	1026	0	2	47	1043	6	2	22	10	27	1045	46	7	40	58	0	73	1	16	1	1	1021	1000	22	32	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	0	54	28	1	0	1	0	1025	0	1	3	8	24	25	2000	1000	1000	1000	1000	52828	45823	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1000	0	0	81	1031	8	1	22	0	27	1041	27	7	33	71	0	73	1	16	1	1	1038	1000	33	26	0	1000	1000	1043	1057	1043	1057	1041
2004	1056	8	0	0	0	0	0	90	40	1	0	2	0	1041	17	4	4	21	22	25	2000	1000	1000	1000	1000	52812	45823	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1056	44	1	1	1001	1000	1000	0	1032	24	0	60	1022	0	2	0	0	31	1019	24	6	26	79	0	73	1	16	1	1	1019	1000	27	28	0	1000	1000	1043	1041	1043	1057	1041
2004	1040	7	0	1	0	0	0	64	24	1	0	2	0	1025	0	1	10	4	21	25	2000	1000	1000	1000	1000	52820	45824	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1020	0	3	67	1085	7	1	24	6	40	1066	56	5	38	64	0	73	1	16	1	1	1021	1000	24	34	9	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	0	62	16	0	0	3	0	1025	10	2	6	9	15	25	2000	1000	1000	1000	1000	52840	45824	0	1056	1056	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1024	0	1	99	1048	5	0	40	14	40	1070	39	7	22	47	0	73	1	16	1	1	1019	1000	29	27	9	1000	1000	1041	1058	1043	1056	1043
2004	1040	8	0	0	0	0	0	54	26	1	0	2	0	1025	21	1	9	9	17	25	2000	1000	1000	1000	1000	51440	45824	0	1040	1056	699	3	789	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1000	0	0	76	1020	0	0	0	0	26	1026	33	7	20	47	0	73	1	16	1	1	1020	1000	26	27	0	1000	1000	1057	1041	1041	1041	1057
2004	1040	7	0	0	0	0	0	72	0	0	0	2	0	1025	14	2	3	3	16	25	2000	1000	1000	1000	1000	52824	45823	0	1059	1040	699	3	773	2000	1000	1000	1000	1000	1056	44	1	1	1001	1000	1000	0	1016	0	0	55	1036	2	1	16	14	28	1064	43	10	24	39	0	73	1	16	1	1	1021	1000	26	27	0	1000	1000	1041	1041	1041	1041	1060
2004	1059	8	0	0	0	0	0	62	0	0	0	2	16	1025	0	1	3	3	15	25	2000	1000	1000	1000	1000	52828	45824	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1018	0	3	65	1059	3	4	15	0	42	1020	39	7	22	47	0	73	1	16	1	1	1038	1000	18	18	0	1000	1000	1041	1041	1041	1055	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1866

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72253	540	0	0	0	0	0	0	406	830	1	736	0	128	71784	808	3	2	71816	25	50820	40588	10126	40100	10000	615369	2730456	0	49	68682	71931	71931	65478	3	65570	50100	40200	10000	70200	10000	71851	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10903	0	165	483	10647	283	14	911	70	14	10919	110	2	122	0	0	9	0	2610	2	63	1	1	71731	40500	1160	1031	1087	10000	40100	71695	72038	71873	72146	71861
50204	71999	538	1	0	0	0	1	0	447	809	1	704	1	104	71954	786	2	3	71644	25	50700	40596	10135	40100	10000	614802	2717006	0	49	68905	72071	72012	65276	3	65546	50100	40200	10000	70200	10000	71971	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10899	1	157	502	10629	277	8	898	44	21	10896	124	3	135	0	0	3	0	2610	1	57	1	1	71704	40480	1030	1046	1091	10000	40100	71688	71878	71940	71822	71986
50204	71857	537	1	0	0	0	0	0	400	796	1	696	1	124	71916	790	2	2	71724	25	50760	40600	10131	40100	10000	613685	2730649	0	49	68659	71814	71932	65216	3	65496	50100	40200	10000	70200	10000	71919	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10896	0	139	473	10641	264	7	887	44	14	10936	138	3	131	0	0	4	0	2610	1	57	1	1	71711	40444	1004	1010	1147	10000	40100	72028	71919	72007	71852	71853
50204	71810	538	0	0	0	0	0	0	416	810	1	744	0	104	71859	806	2	2	71588	25	50805	40600	10145	40100	10000	612516	2721972	0	49	68874	71749	71754	65439	3	65470	50100	40200	10000	70200	10000	71857	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10908	0	138	498	10644	269	9	935	48	14	10899	122	2	123	0	0	3	0	2610	1	57	1	1	71747	40540	1125	1072	1043	10000	40100	71797	71709	71892	72077	71841
50204	72004	539	0	0	0	0	0	0	470	788	1	736	1	128	71934	797	2	3	71579	25	50680	40664	10118	40100	10000	616463	2729672	0	49	68988	71995	72009	65343	3	65528	50100	40200	10000	70200	10000	71946	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10901	1	163	498	10661	260	8	896	28	22	10955	129	3	132	1	0	11	0	2610	1	58	1	1	71837	40480	1066	990	1129	10000	40100	71797	72089	71606	71921	71838
50204	71855	539	0	0	0	0	0	0	398	845	1	736	1	100	72001	809	2	2	71601	25	50790	40596	10136	40100	10000	614517	2726894	0	49	68994	71971	71850	65444	3	65623	50100	40200	10000	70200	10000	71812	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10865	1	161	490	10629	258	12	935	76	27	10862	125	4	122	1	0	9	0	2610	1	64	1	1	71746	40508	1081	1056	1112	10000	40100	71804	71865	72059	71842	71780
50204	71766	538	1	0	0	0	0	0	370	836	1	688	1	144	71813	767	2	2	71751	25	50735	40624	10134	40100	10000	615436	2721239	0	49	68867	71909	72095	65285	3	65534	50100	40200	10000	70200	10000	71901	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10925	1	161	502	10641	280	10	896	138	27	10939	136	3	106	1	3	3	0	2610	1	56	1	1	71749	40500	1144	1041	1087	10000	40100	72022	71829	71824	71743	71749
50204	71934	539	1	1	0	0	0	0	435	790	1	728	0	104	71943	804	3	2	71690	25	50710	40624	10134	40100	10000	612808	2717147	0	49	68796	71989	71860	65293	3	65609	50100	40200	10000	70200	10000	72068	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10914	0	153	495	10632	275	10	899	48	23	10919	121	2	136	0	3	9	0	2610	1	56	1	1	71810	40528	1012	979	1011	10000	40100	72060	71875	71976	71972	71967
50204	71831	539	0	0	0	0	0	0	457	802	1	720	0	104	72151	786	2	2	71662	25	50765	40604	10132	40100	10000	614991	2728544	0	49	68803	71833	71981	65327	3	65648	50313	40200	10000	70200	10000	71836	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10913	0	155	496	10652	269	10	891	72	17	10940	136	2	121	0	3	5	0	2610	1	57	1	1	71711	40476	1028	1129	1129	10000	40100	71890	71929	71674	71943	72069
50204	71881	539	0	0	0	0	0	0	480	797	1	728	1	140	71825	787	2	2	71520	25	50725	40616	10129	40100	10000	614227	2732476	0	49	68919	71900	71960	65236	3	65665	50100	40200	10000	70200	10052	72088	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10893	0	163	516	10623	278	11	928	48	23	10913	131	2	125	0	0	9	0	2610	1	58	1	1	71817	40520	1048	1039	1023	10000	40100	72021	71971	71991	71879	71982

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1757

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	24	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	71902	537	2	0	0	0	0	1	509	818	1	0	728	2	112	71794	788	1	1	71712	25	50670	40550	10136	40010	10000	630625	2714901	0	49	68593	0	71772	71734	65241	3	65523	50010	40020	10000	70020	10000	71785	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10928	2	136	490	10656	270	12	883	80	36	10892	135	1	123	1	0	3	1	0	2520	12	85	0	13	13	71635	40532	964	938	1000	10000	40010	71884	71675	71875	71796	71846
50024	72007	541	3	0	0	0	0	0	531	821	1	0	712	2	164	71710	809	1	1	71617	25	50650	40562	10126	40010	10000	611565	2723971	0	49	68733	0	71645	71890	65281	3	65767	50010	40020	10000	70020	10000	71738	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10881	10	166	493	10672	278	12	894	34	39	10944	141	3	114	2	0	7	0	0	2521	13	65	0	14	14	71662	40544	934	938	950	10000	40010	71931	71938	71922	71829	71863
50024	71619	537	2	0	0	0	0	1	503	865	1	0	728	4	156	71811	811	1	1	71574	25	50745	40562	10129	40010	10000	610258	2719565	0	49	68674	0	71778	71858	65302	3	65612	50010	40020	10000	70020	10000	71779	35	1	1	40022	10	9	10	10000	30010	10000	0	10	10913	9	125	489	10649	273	12	936	78	29	10925	128	2	122	1	0	3	0	0	2520	14	65	0	12	12	71636	40516	886	778	822	10000	40010	71772	71919	71838	71865	71818
50024	71681	537	3	0	3	0	0	0	460	817	1	0	680	1	64	71668	798	1	1	71678	25	50695	40522	10141	40010	10000	630354	2716393	0	49	68595	0	71709	71783	65312	3	65502	50010	40020	10000	70020	10051	71883	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10928	2	135	500	10680	290	8	932	32	45	10941	137	3	127	2	0	5	0	0	2520	12	65	0	11	14	71884	40524	926	896	990	10000	40010	71897	71709	71821	71710	71682
50024	71767	537	2	0	0	0	0	0	536	831	1	0	720	1	100	71963	803	1	1	71698	25	50665	40550	10139	40010	10000	631397	2714153	0	49	68641	0	71819	71626	65248	3	65955	50010	40020	10000	70020	10000	71648	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10928	4	144	485	10660	267	12	908	78	36	10956	139	3	126	2	0	3	1	0	2520	13	65	0	14	12	71593	40500	930	984	922	10000	40010	71911	71734	71887	71733	71951
50024	71849	537	2	0	0	0	0	0	530	865	1	0	744	2	108	71825	826	1	0	71406	25	50660	40550	10139	40010	10000	612835	2720877	0	49	68763	0	71742	71890	65210	3	65683	50010	40020	10000	70020	10000	71894	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10934	9	161	551	10652	280	10	938	82	30	10919	133	3	120	2	0	3	0	0	2520	13	85	0	6	13	71439	40540	906	936	924	10000	40010	71643	71563	71702	71590	71665
50024	71629	535	1	0	0	1	0	0	534	846	1	0	728	1	100	71643	797	1	1	71517	25	50690	40554	10135	40010	10000	630377	2712508	0	49	68726	0	71729	71748	65160	3	65607	50010	40020	10000	70020	10000	71603	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10909	2	146	493	10644	277	11	930	78	29	10941	134	2	116	1	0	3	0	0	2520	12	85	0	13	14	71518	40564	974	1000	946	10000	40010	71808	71903	71890	71690	71724
50024	71664	537	3	0	0	0	0	0	590	796	1	0	728	0	144	71654	808	1	1	71544	25	50710	40462	10128	40010	10000	630654	2710642	0	49	68554	0	71458	71659	65148	3	65592	50010	40020	10000	70020	10000	71719	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10931	3	140	468	10671	268	8	892	74	27	10971	128	3	120	2	3	9	0	0	2520	14	65	0	14	6	71681	40516	932	988	902	10000	40010	71827	71671	71754	71740	71759
50024	71949	537	2	0	0	0	0	0	532	839	1	0	736	0	120	71831	803	1	1	71338	25	50625	40442	10141	40010	10000	629599	2712390	0	49	68703	0	71733	71676	65198	3	65775	50010	40020	10000	70020	10051	71738	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10915	2	140	487	10695	228	14	946	80	44	10914	119	2	128	1	3	4	0	0	2520	12	65	0	5	14	71663	40540	1024	1012	996	10000	40010	71774	71680	71791	71750	71572
50024	71694	539	1	1	0	0	0	0	506	834	1	0	720	2	100	71669	796	1	1	71347	25	50695	40518	10120	40010	10000	612812	2723145	0	49	68529	0	71700	71648	65299	3	65668	50010	40020	10000	70020	10000	71399	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10913	1	139	474	10644	265	10	912	32	29	10871	122	2	137	1	0	3	0	0	2520	13	85	0	13	12	71685	40500	1046	796	914	10000	40010	71820	71866	71883	71789	71775

Test 3: throughput

Count: 8

Code:

  ldrsw x0, [x6, #8]!
  ldrsw x0, [x7, #8]!
  ldrsw x0, [x8, #8]!
  ldrsw x0, [x9, #8]!
  ldrsw x0, [x10, #8]!
  ldrsw x0, [x11, #8]!
  ldrsw x0, [x12, #8]!
  ldrsw x0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3657

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29665	219	1	0	0	0	0	1	0	6367	819	1	632	94	220	29063	764	319	1927	1847	1872	25	160168	80148	80000	80100	80000	400759	1290145	1	53	49	25996	29236	29122	9075	3	9268	160100	80200	80000	80200	80000	29216	35	1	1	80201	100	99	10	100	80000	100	80000	1	100	80910	18	417	5442	84631	677	13	890	40	5200	85787	685	119	4862	4375	18	0	0	0	5110	3	16	3	3	29148	25	80072	330	364	78	80000	80100	29264	29232	29441	29099	29143
160204	29301	219	1	0	0	0	0	1	0	6549	829	1	536	81	136	29233	793	370	1864	1910	1890	25	160163	80167	80000	80100	80000	400782	1296453	1	71	49	26244	29212	29377	9434	3	9277	160100	80200	80000	80200	80000	29186	35	1	1	80201	100	99	10	100	80000	100	80000	0	100	80902	20	402	5870	84851	740	16	918	42	4813	85976	747	130	4822	5098	18	0	10	0	5110	3	16	2	3	29335	29	80072	349	339	98	80000	80100	28964	29387	29090	28981	29306
160204	29033	218	1	0	1	0	0	0	0	7054	865	1	784	92	112	29201	793	330	2075	2286	1817	25	160160	80149	80000	80100	80000	400843	1292873	1	65	49	25990	29347	29354	8979	3	9428	160100	80200	80000	80200	80000	29157	35	1	1	80201	100	99	22	100	80000	100	80000	0	100	80914	16	476	5242	85468	715	15	935	30	4968	85824	724	120	4695	5806	16	1	5	0	5110	3	16	3	5	29282	30	80063	384	334	95	80000	80100	29307	29039	29118	29097	29068
160204	29071	221	1	1	0	0	0	0	0	6650	841	1	584	87	108	29324	823	377	2106	2089	1961	25	160155	80137	80000	80100	80000	400750	1291282	1	68	49	25884	29280	29311	9133	3	9224	160100	80200	80000	80200	80000	29135	35	1	1	80201	100	99	6	100	80000	100	80000	0	100	80907	15	412	5537	85064	726	12	914	58	4806	86068	785	118	5076	4974	18	0	24	0	5110	2	17	3	3	29247	38	80068	380	338	84	80000	80100	29545	29201	29249	29213	29148
160204	29415	218	1	0	0	0	0	0	0	6245	782	1	712	92	108	29298	775	350	2229	2357	1908	25	160156	80158	80000	80100	80000	400790	1296790	0	51	49	26211	29010	28988	9077	3	9079	160100	80200	80000	80200	80000	29450	35	1	1	80201	100	99	10	100	80000	100	80000	0	100	80903	18	377	5817	85776	694	17	941	78	5883	86194	693	133	4779	4613	16	1	6	1	5110	3	17	3	3	29113	33	80070	425	331	83	80000	80100	29310	29291	29296	29341	29538
160204	29353	220	1	0	0	0	0	0	0	6650	836	1	648	114	108	29140	784	379	1963	2047	1920	25	160150	80172	80000	80100	80000	400798	1287632	0	60	49	26012	29125	29318	9027	3	9105	160100	80200	80000	80200	80000	29105	35	1	1	80201	100	99	14	100	80000	100	80000	0	100	80897	17	409	5290	84783	716	17	854	46	5853	85577	816	118	4863	5077	16	0	5	0	5110	3	16	3	2	29281	25	80067	417	349	74	80000	80100	29131	29172	28931	29494	29191
160204	29152	218	2	0	0	0	0	0	0	6492	779	1	672	76	96	29006	778	411	2022	2208	1711	25	160163	80156	80000	80100	80000	400733	1284992	0	59	49	25978	29064	29295	9023	3	9387	160100	80200	80000	80200	80000	29087	35	1	1	80201	100	99	11	100	80000	100	80000	0	100	80891	34	338	6295	85156	762	13	866	64	4925	86046	773	119	5066	5501	17	0	2	0	5110	3	16	3	3	29189	20	80065	311	360	98	80000	80100	29379	29262	29121	29295	29158
160204	29316	220	1	1	0	0	0	0	0	6636	799	1	704	94	152	29503	798	385	2146	2069	1953	25	160158	80157	80000	80100	80000	400775	1285808	0	72	49	26061	29066	29311	9180	3	9126	160100	80200	80000	80200	80000	29207	35	1	1	80201	100	99	11	100	80000	100	80000	0	100	80903	36	408	5152	84938	647	13	878	48	5242	85660	762	137	5243	5131	35	0	5	0	5110	2	17	3	2	29046	25	80065	345	333	87	80000	80100	29038	29379	29243	29208	28926
160204	29565	218	1	0	0	0	1	0	0	6469	788	1	720	73	152	29311	784	438	1970	2000	2184	25	160149	80155	80000	80100	80000	400781	1291640	0	59	49	26147	29377	29610	9246	3	9321	160100	80200	80000	80200	80000	29251	35	1	1	80201	100	99	10	100	80000	100	80000	0	100	80911	36	388	5138	84584	688	18	912	40	5352	85999	800	132	4561	5161	14	0	3	0	5110	2	16	3	3	29307	25	80045	389	350	91	80000	80100	29144	29228	29433	29172	29186
160204	29221	221	1	0	0	0	0	0	1	6938	856	1	808	90	148	29095	796	449	2120	2047	1830	25	160154	80173	80000	80100	80000	400705	1287943	0	82	49	26100	29342	29259	9422	3	9277	160100	80200	80000	80200	80000	29287	35	1	1	80201	100	99	17	100	80000	100	80000	0	100	80904	14	408	5415	85160	744	12	901	46	5108	85758	809	119	5025	5057	36	3	0	0	5110	3	16	3	3	29151	23	80064	373	407	91	80000	80100	29206	29281	29211	29096	29011

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3677

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29733	220	0	0	0	6853	786	1	728	127	124	29383	807	379	1655	1530	2010	25	160080	80069	80000	80010	80000	400333	1297420	65	49	26314	29397	29398	9647	3	9307	160010	80020	80000	80020	80000	29280	35	1	1	80021	10	9	32	10	80000	10	80000	0	10	80938	415	5502	85428	639	8	935	68	5262	86034	682	139	4898	5519	0	7	5020	3	16	1	1	29496	46	80064	611	603	114	80000	80010	29563	29512	29436	29566	29534
160024	29352	220	0	0	0	6642	848	1	728	116	124	29550	827	345	1704	1652	2022	25	160064	80076	80000	80010	80000	400330	1299474	76	49	26461	29326	29556	9551	3	9419	160010	80020	80000	80020	80000	29394	35	1	1	80021	10	9	47	10	80000	10	80000	0	10	80938	388	5643	85551	665	6	928	70	4845	86181	754	119	4455	4977	3	4	5020	1	16	1	1	29418	29	80072	595	615	120	80000	80010	29466	29421	29483	29395	29314
160024	29396	220	0	0	0	6421	861	1	696	110	108	29497	809	368	1782	1910	2182	25	160084	80062	80000	80010	80000	400362	1291564	71	49	26363	29465	29525	9825	3	9463	160010	80020	80000	80020	80000	29483	35	1	1	80021	10	9	39	10	80000	10	80000	0	10	80906	367	5200	85321	674	11	903	72	5235	86060	689	134	4759	5392	3	7	5020	1	16	1	1	29206	34	80063	618	562	94	80000	80010	29464	29474	29334	29240	29606
160024	29359	220	0	1	0	6359	835	1	704	137	96	29529	800	398	1781	2141	2014	25	160068	80065	80000	80010	80000	400370	1300628	77	49	26532	29590	29338	9400	3	9562	160010	80020	80000	80020	80000	29532	35	1	1	80021	10	9	48	10	80000	10	80000	0	10	80952	399	5121	85238	681	8	935	28	4908	86213	765	138	4736	5220	3	4	5020	1	16	1	1	29544	46	80071	637	617	103	80000	80010	29297	29425	29453	29496	29552
160024	29493	221	0	0	0	6764	828	1	744	127	76	29580	789	399	1692	1826	2277	25	160075	80077	80000	80010	80000	400341	1310214	55	49	26555	29252	29350	9579	3	9516	160010	80020	80000	80020	80000	29360	35	1	1	80021	10	9	51	10	80000	10	80000	0	10	80912	373	5180	85246	628	8	922	68	5374	85887	753	118	5109	4949	0	7	5020	1	16	1	1	29129	23	80059	637	611	120	80000	80010	29393	29349	29267	29302	29454
160024	29364	228	0	0	0	6416	836	1	728	142	112	29419	811	391	1649	1806	2204	25	160069	80073	80000	80010	80000	400315	1293771	60	49	26431	29478	29395	9261	3	9405	160010	80020	80000	80020	80000	29377	35	1	1	80021	10	9	50	10	80000	10	80000	0	10	80922	416	5434	85076	712	13	909	42	5045	86391	808	133	4840	5347	0	3	5020	1	15	2	2	29552	33	80070	648	591	114	80000	80010	29576	29474	29570	29514	29466
160024	29296	221	0	0	0	6647	850	1	760	125	100	29585	811	358	1620	1844	2113	25	160072	80067	80000	80010	80000	400339	1282520	64	49	26298	29455	29442	9375	3	9266	160010	80020	80000	80020	80000	29556	35	1	1	80021	10	9	30	10	80000	10	80000	0	10	80922	391	5469	85403	654	12	932	46	5372	85911	816	139	5432	5145	0	3	5020	2	16	2	1	29381	37	80074	620	616	118	80000	80010	29342	29507	29465	29536	29613
160024	29456	220	1	1	1	6725	824	1	712	131	124	29467	799	368	1752	1728	2231	25	160069	80071	80000	80010	80000	400379	1287497	61	49	26376	29292	29409	9396	3	9435	160010	80020	80000	80020	80000	29436	35	1	1	80021	10	9	47	10	80000	10	80000	0	10	80914	387	5343	85220	673	9	950	74	5234	85878	736	131	4849	5521	0	9	5020	1	16	1	1	29463	43	80065	606	598	102	80000	80010	29480	29333	29485	29490	29462
160024	29528	219	0	0	0	6725	818	1	720	124	292	29598	811	416	1924	1817	2117	25	160074	80080	80000	80010	80000	400339	1312761	58	49	26122	29535	29543	9465	3	9372	160010	80020	80000	80020	80000	29504	35	1	1	80021	10	9	66	10	80000	10	80000	0	10	80928	435	5587	85798	660	11	904	44	5267	86508	831	135	5221	4706	0	3	5020	1	16	1	1	29343	38	80078	716	591	100	80000	80010	29475	29357	29500	29470	29291
160024	29518	220	0	0	0	6697	821	1	704	113	140	29399	799	364	1834	2075	2426	25	160077	80079	80000	80010	80000	400336	1299745	66	49	26345	29654	29685	9539	3	9353	160010	80020	80000	80020	80000	29551	35	1	1	80021	10	9	54	10	80000	10	80000	0	10	80902	385	5618	85680	603	11	930	68	4953	86117	820	140	5485	5461	0	3	5020	1	16	2	2	29593	38	80068	647	630	100	80000	80010	29524	29292	29534	29352	29605

LDRSW (pre-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations