Firestorm: CMN (sxtx, 64-bit) measurements

Code:

  cmn x0, x1, sxtx

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	f5	f6	f7	f8	fd
1004	369	3	1	1	0	2	43	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	77	4	18	4	4	366	1000	370	370	370	370	370
1004	369	2	1	1	0	2	43	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	77	4	18	4	4	366	1000	370	370	370	370	370
1004	369	3	1	1	0	2	43	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	77	4	18	4	4	366	1000	370	370	370	370	370
1004	369	3	1	1	0	2	43	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	77	4	18	4	4	366	1000	370	370	370	370	370
1004	369	2	1	1	0	2	43	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	77	4	18	4	4	366	1000	370	370	370	370	370
1004	369	2	1	1	0	2	43	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	77	4	18	4	4	366	1000	370	370	370	370	370
1004	369	2	1	1	0	2	43	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	77	4	18	4	4	366	1000	370	370	370	370	370
1004	369	2	1	1	0	2	43	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	77	4	18	4	4	366	1000	370	370	370	370	370
1004	369	3	1	1	0	2	43	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	77	4	18	4	4	366	1000	370	370	370	370	370
1004	369	3	1	1	0	2	138	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	77	4	18	4	4	366	1000	370	370	370	370	370

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn x0, x1, sxtx
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	4	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	3	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	1	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	4	38	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	1	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	1	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	15	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	1	0	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	54	6	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	3	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	21	0	82	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	105	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	82	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	1	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	82	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	102	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	536	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn x0, x1, sxtx
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	168	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	0	2	28	3	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	698	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	1	3	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	1	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17506	20201	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	396	19918	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20476	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	12	614	19917	25	20100	20100	20207	1297782	1	49	16955	20035	20035	17424	3	17481	20100	20200	30200	20080	104	1	1	20201	100	99	100	20100	10100	0	7	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	21	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	149	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	631	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	108	0	1270	12	27	0	12	13	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	390	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	12	27	0	13	7	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	84	0	1270	13	27	0	12	12	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	99	0	1270	12	27	0	12	5	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	99	0	1270	14	27	0	13	11	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	1	799	0	1270	13	27	0	12	10	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	1	0	0	1270	13	27	0	13	6	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1	1270	13	27	0	13	14	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	441	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	13	27	0	13	12	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	102	0	1270	14	27	0	13	6	19995	20000	10010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  cmn x0, x1, sxtx
  cmn x0, x1, sxtx
  cmn x0, x1, sxtx
  cmn x0, x1, sxtx
  cmn x0, x1, sxtx
  cmn x0, x1, sxtx
  cmn x0, x1, sxtx
  cmn x0, x1, sxtx

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26772	201	0	77	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	4	19	2	2	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	201	0	100	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	19	2	2	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	144	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	19	2	2	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	121	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	19	2	2	26731	80135	100	26736	26736	26736	26736	26736
80204	26735	200	0	1175	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80295	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	19	2	2	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	58	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	19	2	2	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	123	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	19	2	2	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	144	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	19	2	2	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	123	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	19	2	2	26731	80213	100	26736	26736	26736	26736	26736
80204	26735	200	0	1196	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	19	2	2	26731	80000	100	26736	26736	26736	26736	26736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26710	200	0	0	206	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	2	18	3	3	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	2	0	0	5020	0	3	18	3	3	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	2	18	2	3	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	2	18	2	3	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	3	18	3	3	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	2	1	80021	10	9	10	80010	10	0	0	0	5020	0	3	18	3	2	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	41	0	3	5020	0	3	18	3	3	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	3	18	3	3	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	3	18	3	2	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	199	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	3	18	3	2	26701	80000	10	26706	26706	26706	26706	26706

CMN (sxtx, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations