Firestorm: STLXP (32-bit) measurements

Code:

  stlxp w0, w1, w2, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 50.674

Integer unit issues: 0.000

Load/store unit issues: 50.674

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	22	23	3f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	64	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	atomic or exclusive fail (b4)	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	37993	284	0	0	1998	0	0	37978	7267	50674	50674	87814	1003249	1	1000	49	34913	0	37993	37993	13140	5949	24406	87814	91440	274320	38004	37993	1001	1	1001	1000	1000	44965	44965	44965	0	1998	44965	1000	1000	0	16590	8	2055	2	2	37909	0	1000	37994	37994	37994	37994	37994
1004	37993	284	0	0	1998	0	0	37978	7267	50674	50674	87814	1003249	1	1000	49	34913	0	37993	37993	13140	5937	24394	87814	91440	274320	38009	37995	1001	1	1001	1000	1000	44965	44965	44965	0	1998	44965	1000	1000	0	16590	2	2063	2	2	37909	0	1000	37994	37994	37994	37994	37994
1004	37993	284	0	0	1998	0	0	37978	7267	50674	50674	87814	1003249	1	1000	49	34913	0	37993	37993	13140	5937	24394	87814	91440	274320	37994	37993	1001	1	1001	1000	1000	44965	44965	44965	0	1998	44965	1000	1000	0	16590	2	2063	2	2	37909	0	1000	37994	37994	37994	37994	37994
1004	37993	284	0	0	1998	0	0	37978	7267	50674	50674	87814	1003249	1	1000	49	34913	0	37993	37993	13140	5937	24394	87814	91440	274320	37994	38000	1001	1	1001	1000	1000	44965	44965	44965	0	1998	44965	1000	1000	0	16590	2	2057	2	2	37909	0	1000	37994	37994	37994	37994	37994
1004	37993	284	0	0	2001	1	0	37978	7267	50674	50674	87814	1003249	1	1000	49	34913	0	37993	37993	13140	5943	24397	87814	91440	274320	38001	37993	1001	1	1001	1000	1000	44965	44965	44965	0	1998	44965	1000	1000	0	16590	2	2063	2	2	37909	0	1000	37994	37994	37994	37994	37994
1004	37993	285	0	0	1998	0	0	37978	7267	50674	50674	87814	1003249	1	1000	49	34913	0	37993	37993	13140	5949	24402	87814	91440	274320	38001	37993	1001	1	1001	1000	1000	44965	44965	44965	0	2008	44965	1000	1000	2	16590	2	2063	2	2	37909	0	1000	37994	37994	37994	37994	37994
1004	37993	285	0	0	1998	0	0	37978	7267	50674	50674	87814	1003249	1	1000	49	34913	0	37993	37993	13140	5937	24394	87814	91440	274320	38007	37994	1001	1	1001	1000	1000	44965	44965	44965	0	1998	44965	1000	1000	0	16590	2	2053	2	2	37909	0	1000	37994	37994	37994	37994	37994
1004	37993	284	0	0	1998	0	0	37978	7267	50674	50674	87814	1003249	1	1000	49	34913	0	37993	37993	13140	5940	24394	87814	91440	274320	37997	37993	1001	1	1001	1000	1000	44965	44965	44965	0	1998	44965	1000	1000	0	16590	2	2063	2	2	37909	0	1000	37994	37994	37994	37994	37994
1004	37993	284	0	0	1998	0	0	37978	7267	50674	50674	87814	1003249	0	1000	49	34913	0	37993	37993	13140	5937	24394	87814	91440	274320	38006	37998	1001	1	1001	1000	1000	44965	44965	44965	0	1998	44965	1000	1000	0	16590	2	2063	2	2	37909	0	1000	37994	37994	37994	37994	37994
1004	37993	285	0	0	1998	1	0	37978	7267	50674	50674	87814	1003249	1	1000	49	34913	0	37993	37993	13140	5941	24397	87814	91440	274320	38015	37996	1001	1	1001	1000	1000	44965	44965	44965	0	1998	44965	1000	1000	0	16590	2	2063	2	2	37912	0	1000	37994	37994	37994	37994	37994

Test 2: throughput

Code:

  stlxp w0, w1, w2, [x6]
  add x6, x6, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 38.9249

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	1f	20	22	23	24	29	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	atomic or exclusive fail (b4)	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20209	389225	2916	2	6	0	0	2	2	0	20228	1	815	2	0	0	632	113	156	389238	571	0	69401	558500	298925	259591	788773	697488	12744663	11718062	0	10000	0	49	386049	0	389252	389127	83468	59202	181170	1486285	794496	778606	794504	2336016	389133	389254	10001	1	20201	100	99	100	10000	10100	10000	100	230674	8	35739	309	0	730	229883	10	0	932	46	20025	230520	10000	1344	0	0	0	0	209460	1	60	11040	57	64	389068	291425	10000	10100	389128	389254	389128	389129	389128
20204	389250	2915	1	2	0	0	2	1	0	20241	0	806	1	0	0	728	181	304	389236	614	7	69402	558518	298939	259576	788773	697487	12744671	11717662	0	10000	0	49	386175	3	389253	389254	83527	59083	181302	1486262	794474	778665	794473	2335995	389128	389127	10001	1	20201	100	99	100	10000	10100	10000	100	230542	8	36273	238	0	656	229849	5	1	860	52	20019	230510	10000	1552	0	0	0	0	209461	1	41	11007	57	108	389114	291423	10000	10100	389129	389128	389256	389128	389128
20204	389250	2916	1	2	1	0	2	1	0	20171	0	835	2	0	0	520	177	228	389111	569	0	69278	558502	298925	259577	788773	697487	12744693	11717011	1	10000	0	49	386050	0	389251	389130	83531	59206	181296	1486462	794501	778604	794473	2335812	389128	389252	10001	1	20201	100	99	100	10000	10100	10000	100	230604	4	26162	310	0	682	229847	2	4	859	78	20016	230572	10000	1400	0	2	0	0	209460	1	60	10978	56	64	389068	291423	10000	10100	389129	389250	389129	389255	389253
20204	389252	2915	1	2	1	0	2	0	0	20147	0	820	1	0	0	592	176	276	389113	635	0	69422	558527	298987	259578	788772	697490	12744742	11716968	1	10000	0	49	386172	0	389127	389127	83528	59083	181168	1486260	794473	778675	794473	2335992	389129	389128	10001	1	20201	100	99	100	10000	10100	10000	100	230574	0	34086	338	0	720	229877	27	0	924	46	20019	230524	10000	1512	0	0	0	0	209457	1	59	11582	57	64	389189	291575	10000	10100	389128	389130	389131	389254	389132
20204	389254	2915	1	2	1	0	2	0	0	20272	0	801	1	0	0	584	159	220	389112	700	0	69404	558500	298925	259577	788777	697488	12744648	11717874	0	10000	0	49	386056	0	389251	389127	83467	59097	181293	1486289	794496	778613	794498	2335989	389255	389251	10002	1	20201	100	99	100	10000	10100	10000	100	230653	0	33513	329	0	672	229847	6	0	844	42	20022	230512	10000	1480	0	0	0	0	209460	1	60	10978	57	64	389194	291424	10000	10100	389252	389127	389130	389128	389253
20204	389253	2915	1	2	0	0	1	0	0	20188	176	879	1	0	0	736	160	224	389236	573	32	69404	558506	299090	259576	788801	697678	12744662	11717803	0	10000	0	49	386170	0	389252	389252	83529	59206	181324	1486283	794496	778619	794477	2335815	389127	389127	10002	1	20201	100	99	100	10000	10100	10000	100	230548	1	32965	325	0	719	229853	11	0	875	58	20016	230524	10000	1440	0	1	0	0	209460	1	60	10970	57	64	389069	291425	10000	10100	389251	389131	389286	389129	389253
20204	389252	2916	1	1	0	0	2	1	0	20256	0	788	1	0	0	744	174	112	389112	663	0	69279	558502	298925	259577	788773	697487	12744648	11717686	0	10000	0	49	386047	0	389252	389128	83527	59078	181191	1486263	794473	778679	794532	2336007	389252	389253	10001	1	20201	100	99	100	10000	10100	10000	100	230570	2	31297	241	0	682	229862	9	1	906	50	20016	230626	10000	1352	0	0	0	0	209461	1	62	10978	60	66	389381	291423	10000	10100	389254	389251	389129	389253	389198
20204	389251	2915	1	2	1	0	2	0	0	20146	0	851	2	0	0	568	187	108	389111	575	0	69404	558502	298926	259576	788797	697486	12745173	11717689	0	10000	0	49	386172	0	389127	389205	83464	59203	181299	1486284	794505	778633	794478	2335995	389252	389127	10001	1	20202	100	99	100	10000	10100	10000	100	230555	0	34974	228	0	663	229843	4	1	880	90	20016	230579	10000	1432	0	1	0	0	209459	1	60	10975	57	64	389193	291423	10000	10100	389130	389253	389184	389254	389130
20204	389127	2915	1	2	1	0	2	1	0	20325	0	810	1	0	0	608	151	120	389235	589	5	69280	558504	298924	259579	788796	697531	12744644	11717665	0	10000	14	49	386171	0	389127	389128	83471	59207	181302	1486259	794497	778681	794502	2335830	389130	389253	10001	1	20201	100	99	100	10000	10100	10000	100	230598	1	32977	301	0	754	229878	7	1	873	62	20010	230562	10000	1664	0	1	0	0	209479	1	59	10976	57	63	389230	291426	10000	10100	389130	389130	389128	389131	389129
20204	389129	2915	1	2	0	0	2	1	0	20217	0	800	1	0	0	400	143	112	389236	676	0	69402	558500	298926	259576	788808	697486	12744601	11717718	0	10000	0	49	386169	0	389205	389250	83568	59083	181178	1486283	794500	778616	794499	2335830	389126	389252	10001	1	20201	100	99	100	10000	10100	10000	100	230546	1	32956	264	0	668	229847	4	0	898	58	20004	230538	10000	1456	0	0	0	0	209477	1	60	10978	57	64	389191	291424	10000	10100	389253	389129	389251	389128	389253

1000 unrolls and 10 iterations

Result (median cycles for code): 38.9946

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20029	389973	2921	2	0	0	1	2	20230	7	885	1	544	99	124	389940	694	4	70100	550222	290553	259666	760249	697575	12689806	11765184	0	10000	0	49	386877	0	389944	389944	70825	59888	188868	1457838	760821	759176	760820	2277525	389957	44	10001	1	20021	10	9	10	10000	10010	10000	10	230636	15	32973	362	0	669	229945	6	0	916	36	20020	230670	10000	7	1480	1	6	0	200996	0	43	10978	38	40	389940	289803	10000	10010	389993	389966	389946	389946	389958
20024	389955	2921	3	1	3	1	0	20278	7	815	1	688	110	420	389942	586	3	70089	550216	290552	259664	760252	697576	12689852	11765158	0	10000	0	49	386876	0	389956	389955	70828	59899	188863	1457822	760820	759190	760820	2277522	389956	44	10001	1	20021	10	9	10	10000	10010	10000	10	230639	7	31862	267	0	725	229941	9	0	868	74	20032	230643	10000	7	1360	1	1	0	201084	0	43	10977	40	40	389886	289801	10000	10010	389945	389957	389956	389945	389957
20024	389989	2921	3	1	0	0	0	20222	7	783	1	744	120	284	389929	662	2	70099	550220	290554	259665	760250	697576	12689799	11765195	1	10000	0	49	386875	0	389956	389944	70815	59888	188867	1457826	760826	759178	760823	2277507	389944	44	10001	1	20021	10	9	10	10000	10010	10000	10	230628	7	32619	321	0	679	229953	11	2	900	86	20021	230687	10000	7	1656	1	0	0	201000	0	39	10978	39	40	389885	289801	10000	10010	389946	389946	389947	389956	389958
20024	389957	2921	2	1	0	1	0	20209	7	809	1	656	99	148	389929	573	2	70111	550216	290557	259667	760252	697574	12689859	11765217	1	10000	0	49	386857	0	389938	389937	70813	59899	188859	1457818	760810	759170	760810	2277513	389936	389947	10001	1	20021	10	9	10	10000	10010	10000	10	230682	0	36111	283	0	692	229943	6	4	845	42	20016	230756	10000	0	1368	0	2	0	200996	0	40	10972	38	38	389882	289793	10000	10010	389951	389948	389937	389948	389937
20024	389948	2921	2	0	2	0	0	20179	7	820	1	656	91	240	389931	585	4	70088	550218	290553	259671	760262	697574	12689793	11765229	1	10000	14	49	386876	0	389948	389955	70817	59898	188863	1457826	760824	759168	760823	2277531	389956	44	10001	1	20021	10	9	10	10000	10010	10000	10	230680	7	37780	282	0	725	229967	5	4	933	48	20020	230623	10000	7	1480	1	3	0	200995	0	39	10970	36	38	389896	289802	10000	10010	389957	389995	389960	389957	389946
20024	389945	2921	3	0	0	1	0	20114	7	839	1	416	91	224	389941	540	4	70088	550220	290553	259669	760258	697576	12689846	11765137	1	10000	0	49	386864	0	389957	389944	70826	59901	188857	1457842	760818	759182	760820	2277519	389981	44	10001	1	20021	10	9	10	10000	10010	10000	10	230690	15	36674	309	0	676	229956	8	0	925	82	20208	230631	10000	7	1624	1	2	0	200996	0	41	10978	38	39	389896	289802	10000	10010	389958	389945	389947	389948	389956
20024	389944	2921	3	1	0	0	0	20215	7	801	2	544	102	224	389941	701	3	70100	550218	290552	259670	760252	697574	12689814	11765196	1	10000	0	49	386875	0	389944	389946	70823	59906	188853	1457824	760821	759172	760822	2277501	389958	44	10001	1	20021	10	9	10	10000	10010	10000	10	230642	7	34275	240	0	748	229952	11	0	992	40	20011	230692	10000	7	1088	1	0	0	200997	0	42	10931	40	41	389897	289801	10000	10010	389956	389956	389957	389945	389945
20024	389957	2953	4	0	4	0	4	20271	7	800	4	392	94	120	389940	596	4	70088	550220	290553	259665	760246	697574	12689770	11765172	1	10000	0	49	386864	0	389945	389956	70822	59888	188867	1457822	760828	759177	760828	2277531	389957	44	10001	1	20021	10	9	10	10000	10010	10000	10	230670	9	26556	306	0	642	229942	6	2	908	90	20018	230610	10000	7	1264	1	6	0	200997	0	40	10978	37	41	389898	289802	10000	10010	389949	389958	389957	389947	389958
20024	389945	2921	2	1	0	0	0	20180	7	806	2	424	108	92	389941	554	4	70100	550216	290566	259667	760258	697576	12689823	11765145	0	10000	0	49	386864	3	389955	389959	70820	59892	188867	1457822	760823	759169	760832	2277534	389956	44	10001	1	20021	10	9	10	10000	10010	10000	10	230724	15	30606	314	0	683	229952	5	0	878	98	20014	230684	10000	7	1368	1	8	0	200996	0	43	10974	41	42	389898	289804	10000	10010	389946	389960	389957	389947	389949
20024	389945	2920	3	0	4	0	0	20280	7	827	1	720	109	320	389940	704	3	70099	550216	290553	259664	760326	697574	12690182	11765108	1	10000	0	49	386864	0	389946	389961	70815	59888	188864	1457829	760817	759175	760824	2277516	389957	44	10001	1	20021	10	9	10	10000	10010	10000	10	230633	7	34990	262	0	691	229943	5	0	920	46	20017	230682	10000	7	1472	1	0	0	200997	0	43	10978	36	41	389896	289803	10000	10010	389949	389946	389957	389947	389960

Test 3: throughput

Code:

  stlxp w0, w1, w2, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 38.0115

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10205	380102	2847	0	0	1	0	0	19998	0	0	0	0	380092	0	70271	529284	10697	518575	10697	915736	54383	10462783	0	10000	49	377027	0	380107	380107	130437	59947	248979	926433	19100	938443	19100	2815329	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458865	0	458866	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172639	1	131	11070	131	131	380048	1197	10000	100	380148	380111	380111	380111	380111
10204	380110	2847	0	0	0	0	0	19998	0	0	0	183	380110	0	70276	529272	10697	518575	10697	915715	54384	10461754	0	10000	49	377030	0	380124	380124	130429	59957	248974	926412	19100	938418	19100	2815278	380110	380110	10001	1	10201	100	99	100	10000	100	10000	100	458911	0	458866	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172637	1	131	11081	130	130	380053	1197	10000	100	380142	380122	380111	380111	380113
10204	380111	2847	0	0	0	0	0	19998	0	0	0	180	380092	0	70272	529272	10697	518575	10696	915736	54384	10461863	0	10000	49	377027	0	380107	380107	130437	59947	248979	926522	19100	938443	19100	2815329	380122	380107	10001	1	10201	100	99	100	10000	100	10000	100	458953	0	458866	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172640	1	131	11064	130	129	380048	1197	10000	100	380134	380113	380108	380108	380108
10204	380108	2848	0	0	0	0	0	19998	0	1	0	181	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	0	10000	49	377027	0	380108	380107	130437	59947	248979	926433	19100	938443	19100	2815329	380131	380101	10001	1	10201	100	99	100	10000	100	10000	100	458906	0	458866	0	458866	0	0	20004	458866	10000	0	10000	0	0	10	172638	1	116	11061	129	129	380048	1197	10000	100	380116	380143	380108	380108	380109
10204	380107	2847	0	0	0	0	0	19998	0	0	0	180	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	1	10000	49	377027	0	380107	380107	130437	59955	248992	926433	19100	938443	19100	2815329	380108	380107	10001	1	10201	100	99	100	10000	100	10000	100	458933	0	458866	0	458866	0	0	20001	458866	10000	0	10000	0	0	3	172636	1	130	11072	130	130	380048	1197	10000	100	380158	380118	380108	380108	380108
10204	380107	2847	0	0	0	0	0	19998	0	0	0	181	380092	0	70272	529272	10697	518601	10697	915736	54384	10461863	1	10000	49	377027	0	380107	380107	130437	59951	248979	926452	19100	938443	19100	2815329	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458868	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172561	1	129	11072	130	135	380048	1197	10000	100	380116	380135	380118	380108	380109
10204	380107	2847	0	0	0	0	0	20007	0	1	0	181	380103	0	70271	529272	10697	518575	10697	915736	54384	10461863	0	10000	49	377027	3	380111	380107	130437	59947	248979	926433	19100	938443	19100	2815329	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458915	0	458866	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172636	1	130	11059	130	130	380048	1197	10000	100	380141	380118	380108	380108	380108
10204	380107	2847	0	0	0	0	0	19998	0	0	0	181	380092	0	70271	529272	10697	518575	10698	915736	54384	10461863	0	10000	49	377027	0	380107	380107	130437	59949	248979	926532	19100	938443	19100	2815329	380107	380109	10001	1	10201	100	99	100	10000	100	10000	100	458919	0	458866	0	458868	0	0	20004	458866	10000	0	10000	0	0	10	172638	1	130	11072	131	131	380048	1197	10000	100	380131	380108	380108	380108	380108
10204	380107	2848	0	0	0	0	0	19998	0	0	0	181	380092	0	70273	529272	10697	518575	10697	915736	54384	10461863	0	10000	49	377027	0	380107	380124	130437	59963	248995	926433	19100	938443	19100	2815329	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458865	0	458882	0	458866	0	0	19998	459538	10000	0	10000	0	0	10	172638	1	130	11072	130	130	380048	1197	10000	100	380141	380116	380117	380125	380108
10204	380387	2847	0	0	0	0	0	20010	0	0	0	180	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	0	10000	49	377027	0	380107	380107	130437	59947	248979	926433	19100	938443	19100	2815329	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458970	0	458866	0	458868	0	0	20001	458866	10000	0	10000	0	0	10	172636	1	130	11072	130	129	380048	1197	10000	100	380116	380146	380116	380108	380110

1000 unrolls and 10 iterations

Result (median cycles for code): 38.0011

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	23	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	atomic or exclusive fail (b4)	l1d cache miss st nonspec (c0)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10025	380019	2847	0	0	0	0	19998	0	0	379997	0	70268	519732	1067	518665	1067	915805	5424	10470394	0	10000	0	49	376933	0	380013	380011	138348	59952	249327	916872	1910	953932	1910	2861676	380019	380012	10001	1	10021	10	9	10	10000	10	10000	10	458956	458960	0	458956	0	19998	458956	10000	10000	0	0	169646	43	11081	42	41	380179	117	10000	10	380012	380012	380012	380012	380012
10024	380011	2846	0	0	0	0	20007	0	0	379996	0	70267	519732	1067	518665	1067	915805	5424	10470394	0	10000	0	49	376931	0	380011	380011	138348	59943	249335	916872	1910	953985	1910	2861676	380037	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	458956	0	458956	2	19998	458956	10000	10000	0	0	169725	44	11080	49	49	379944	117	10000	10	380012	380012	380012	380012	380013
10024	380011	2846	0	0	0	0	20028	0	0	379996	0	70267	519732	1067	518665	1067	915805	5424	10470394	0	10000	0	49	376931	0	380011	380011	138348	59949	249364	916872	1910	953892	1910	2861676	380017	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	458956	0	458956	1	19998	458956	10000	10000	0	0	169646	49	11080	42	49	379946	117	10000	10	381334	381138	381161	380487	380013
10024	380011	2846	0	0	0	0	19998	0	0	379996	0	70267	519732	1067	518665	1067	915805	5424	10470399	0	10000	0	49	376931	0	380011	380035	138348	59940	249327	916872	1910	953892	1910	2861676	380026	380019	10001	1	10021	10	9	10	10000	10	10000	10	458956	458956	0	458956	0	19998	458956	10000	10000	0	0	169646	41	11080	43	49	379944	117	10000	10	380012	380012	380012	380012	380012
10024	380011	2847	0	0	0	0	19998	0	0	379996	0	70269	519732	1067	518664	1067	915807	5424	10470394	0	10000	360	49	376931	0	380011	380012	138348	59943	249330	917009	1910	953892	1910	2861676	380034	380019	10001	1	10021	10	9	10	10000	10	10000	10	458956	458956	0	459002	87	19998	458956	10000	10000	0	0	169646	41	11082	42	42	379944	117	10000	10	380012	380012	380012	380014	380012
10024	380011	2846	0	0	0	0	19998	0	0	380019	0	70267	519732	1067	518665	1067	915805	5424	10470394	0	10000	0	49	376933	0	380011	380013	138348	59939	249327	916872	1910	953892	1910	2861685	380019	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	458956	0	458956	0	19998	458955	10000	10000	0	0	169646	49	11069	42	49	379949	117	10000	10	380012	380012	380015	380012	380012
10024	380011	2846	0	0	0	0	19998	0	0	379996	0	70267	519731	1067	518665	1067	915829	5424	10470394	1	10000	0	49	376931	0	380011	380011	138348	59939	249327	916871	1910	953892	1910	2861676	380019	380019	10001	1	10021	10	9	10	10000	10	10000	10	458956	458956	0	458956	0	19998	458956	10000	10000	0	0	169646	49	11081	49	49	379944	117	10000	10	380012	380012	380012	380013	380012
10024	380011	2847	0	1	34	43	27762	5332	0	384608	912	72774	520290	1072	518901	1067	915804	5441	10488688	0	10000	0	49	376931	0	380034	380018	138348	59940	249343	916872	1910	953892	1910	2861685	380019	380019	10001	1	10021	10	9	10	10000	10	10000	10	458956	459018	0	458956	0	19998	458956	10000	10000	0	0	169646	49	11072	49	49	379952	117	10000	10	380014	380012	380012	380012	380033
10024	380012	2846	0	0	0	0	19998	0	0	379996	0	70267	519732	1067	518665	1067	915805	5423	10470900	0	10000	0	49	376931	0	380012	380011	138348	59939	249333	916872	1910	953892	1910	2861676	380045	380012	10001	1	10021	10	9	10	10000	10	10000	10	458956	458956	0	458956	0	20001	458956	10000	10000	0	0	169646	49	11070	43	43	379944	117	10000	10	380018	380012	380012	380012	380012
10024	380011	2847	0	0	0	0	20113	0	0	379997	0	70267	519732	1067	518665	1067	915805	5424	10470399	0	10000	0	49	376931	0	380011	380011	138348	59939	249340	916871	1910	953892	1910	2861676	380042	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	458955	0	458956	0	19998	458956	10000	10000	0	0	169646	41	11079	42	42	379944	117	10000	10	380012	380012	380012	380012	380012

STLXP (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations