Firestorm: LDR (register, sxtw, 64-bit) measurements

Code:

  ldr x0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	1	1	54	88	1	0	1	374	2	12	18	16	25	1000	1000	1000	14774	0	389	389	212	3	249	1000	1000	2000	389	71	1	1	1001	1000	1000	1000	39	1035	0	0	39	1039	6	1	35	43	73	1	16	1	1	391	10	6	4	1000	394	397	396	390	395
1004	394	2	0	0	45	0	1	0	2	379	2	12	18	16	25	1000	1000	1000	14838	1	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1039	0	0	39	1039	6	1	35	43	73	1	16	1	1	391	10	6	4	1000	395	395	395	395	395
1004	394	3	0	0	45	0	0	0	2	379	2	12	12	16	25	1000	1130	1000	14989	0	394	394	216	3	247	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1039	0	0	35	1039	6	1	35	43	73	1	16	1	1	391	10	10	2	1000	395	390	395	395	395
1004	394	3	0	0	45	0	1	0	2	379	2	12	18	16	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	2000	389	71	1	1	1001	1000	1000	1000	39	1039	0	0	39	1039	6	1	35	43	73	1	16	1	1	391	10	10	4	1000	395	390	395	395	396
1004	394	3	0	0	41	0	1	0	1	379	2	12	18	16	25	1000	1000	1000	14838	0	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1039	0	0	39	1039	6	1	35	43	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	389	2	1	0	45	0	0	0	2	379	2	12	18	16	25	1000	1000	1000	14989	0	394	394	217	3	247	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	43	1039	0	0	40	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	45	0	0	0	2	379	2	12	18	22	25	1000	1000	1000	14989	0	394	389	212	3	247	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1039	0	0	39	1039	6	1	35	43	73	1	16	1	1	392	10	6	4	1000	395	390	395	395	395
1004	394	3	0	0	45	0	0	0	2	379	2	12	18	16	25	1000	1000	1000	14989	1	394	394	217	3	247	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1039	0	0	35	1039	6	1	35	43	73	1	16	1	1	391	10	6	4	1000	395	395	395	395	395
1004	394	3	0	0	45	0	0	0	2	379	2	12	18	16	25	1000	1000	1000	14989	0	394	395	217	3	247	1000	1000	2000	394	72	1	1	1001	1000	1000	1000	39	1039	0	0	39	1039	6	1	36	43	73	1	16	1	1	386	10	10	4	1000	395	395	395	395	395
1004	394	2	0	0	45	0	1	0	2	379	2	12	18	11	25	1000	1000	1000	14989	0	394	394	224	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1033	0	0	39	1039	6	1	39	43	73	1	16	1	1	386	10	10	4	1000	395	390	395	395	392

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70053	525	0	0	0	0	0	0	1	0	1	0	70020	69735	59695	25	40104	30103	10001	30100	10000	616175	3342206	0	49	66967	70050	70050	64631	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	2610	2	71	1	1	69813	30003	0	6	6	10000	30100	70036	70051	70036	70051	70048
40204	70050	525	0	0	0	0	0	0	1	0	0	0	70032	69764	59706	42	40104	30103	10001	30100	10000	616132	3342062	0	49	66970	70050	70050	64646	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	0	0	2610	1	71	1	1	69852	30003	0	0	9	10000	30100	70036	70051	70051	70036	70051
40204	70035	524	0	0	0	0	0	0	1	0	0	0	70032	69764	59709	25	40104	30103	10001	30100	10000	616005	3342206	1	49	66967	70050	70047	64646	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69811	30000	9	6	6	10000	30100	70048	70051	70048	70036	70051
40204	70035	525	0	0	0	0	0	0	1	0	1	0	70035	69781	59706	25	40104	30103	10001	30100	10000	616005	3342206	1	49	66955	70035	70050	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	2610	1	71	1	1	69816	30000	9	9	9	10000	30100	70048	70048	70036	70048	70051
40205	70103	524	0	0	0	0	0	0	0	0	0	0	70032	69764	59695	25	40100	30100	10001	30100	10000	616175	3342206	1	49	66967	70035	70050	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	70101	30003	6	6	0	10000	30100	70048	70051	70051	70051	70048
40204	70035	524	0	0	0	0	0	0	1	0	0	0	70020	69784	59695	25	40104	30100	10001	30100	10000	616005	3342206	1	49	66970	70050	70050	64631	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69817	30003	6	6	0	10000	30100	70036	70051	70051	70048	70083
40204	70035	525	0	0	0	0	0	0	0	0	0	1	70035	69781	59709	25	40104	30100	10001	30100	10000	616175	3342062	0	49	66970	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	0	10000	1	0	1	0	2610	1	71	1	1	69811	30000	9	0	9	10000	30100	70036	70036	70051	70052	70036
40204	70050	524	0	0	0	0	0	0	1	0	0	0	70035	69764	59709	25	40112	30103	10001	30100	10000	616015	3344734	1	49	66955	70047	70035	64631	3	64938	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	2	0	0	10000	1	0	1	0	2610	1	71	1	1	69811	30000	9	9	0	10000	30100	70036	70036	70036	70051	70036
40204	70047	525	0	0	0	0	0	0	1	0	0	0	70032	69764	59695	25	40104	30103	10001	30100	10000	616175	3342206	0	49	66970	70050	70047	64646	3	64956	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	2610	1	71	1	1	69845	30000	0	9	9	10000	30100	70051	70036	70051	70051	70036
40204	70050	524	0	0	0	0	0	0	1	0	0	1	70020	69781	59695	25	40104	30103	10001	30100	10000	616005	3342206	1	49	66989	70061	70047	64646	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	2610	1	71	1	1	69836	30000	10	0	9	10000	30100	70036	70036	70051	70051	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	525	1	0	1	0	1	1	1	0	2	0	1	1	70038	69702	59712	25	40018	30016	10002	30010	10000	617009	3342350	0	1	49	66973	70041	70041	64671	0	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10001	0	0	0	1	10000	1	1	1	1	0	0	2520	3	71	5	5	69816	30006	0	6	6	10000	30010	70054	70054	70054	70042	70054
40024	70053	525	1	0	1	1	0	1	1	0	7	0	1	1	70038	69777	59712	25	40018	30013	10002	30010	10000	617009	3342350	0	0	49	66973	70053	70041	64671	0	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	0	10003	0	0	2	1	10000	1	1	1	1	0	0	2520	5	71	4	5	69816	30003	0	0	0	10000	30010	70054	70054	70054	70054	70054
40024	70053	525	1	0	1	1	1	1	1	0	2	0	1	1	70038	69777	59712	25	40018	30016	10002	30010	10000	617009	3342350	0	0	49	66973	70053	70053	64671	0	3	64966	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10002	0	0	0	1	10000	1	1	1	1	1	0	2520	3	71	3	4	69816	30006	6	6	0	10000	30010	70054	70054	70054	70054	70054
40024	70053	524	1	0	0	1	1	1	1	0	2	0	0	1	70026	69777	59712	25	40018	30016	10001	30010	10000	617009	3342350	0	0	49	66973	70053	70053	64671	0	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	0	0	1	10000	1	1	1	1	1	0	2520	4	71	4	5	69816	30006	6	6	6	10000	30010	70054	70042	70054	70054	70054
40024	70053	525	1	0	0	0	1	1	0	0	2	0	1	1	70038	69777	59712	25	40018	30016	10002	30010	10000	617009	3342350	0	0	49	66973	70055	70041	64671	0	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10003	0	0	2	1	10000	1	1	1	1	2	0	2520	4	71	5	3	69816	30006	6	6	6	10000	30010	70054	70054	70054	70054	70054
40024	70053	524	1	0	1	0	1	1	0	0	2	0	0	1	70038	69777	59712	25	40018	30016	10002	30010	10000	616995	3342350	0	0	49	67028	70053	70057	64671	0	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10003	0	0	0	1	10000	1	1	1	1	1	0	2520	4	71	5	4	69816	30006	6	6	0	10000	30010	70042	70054	70054	70054	70054
40024	70053	525	1	0	1	0	0	1	0	0	1	0	1	1	70038	69777	59712	25	40018	30016	10001	30010	10000	616995	3342350	0	0	49	66973	70053	70053	64671	0	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	1	10001	0	0	0	1	10000	1	1	1	1	2	0	2520	4	71	5	3	69816	30003	6	6	6	10000	30010	70054	70054	70042	70054	70054
40024	70053	525	1	0	1	1	0	1	1	0	1	0	1	1	70038	69702	59712	25	40031	30016	10002	30010	10000	617009	3341769	0	0	49	66973	70053	70053	64671	0	3	64978	40010	30020	10000	60020	20134	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10001	0	0	2	4	10000	1	1	1	1	1	0	2520	4	71	4	4	69816	30006	0	6	6	10000	30010	70054	70054	70054	70054	70054
40024	70053	525	1	0	0	1	1	1	0	0	2	0	1	0	70038	69777	59712	25	40018	30016	10002	30010	10000	617009	3342350	0	0	49	66973	70053	70053	64671	0	3	64978	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	2	1	10001	0	0	2	1	10000	1	1	1	1	1	0	2520	4	71	4	4	69816	30006	6	23	6	10000	30010	70056	70056	70047	70055	70054
40024	70041	525	1	0	0	1	1	1	0	0	2	0	1	1	70038	69777	59712	25	40014	30016	10002	30010	10000	617009	3341769	0	0	49	66975	70053	70053	64659	0	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	3	1	10003	0	0	0	1	10000	1	1	1	1	0	0	2520	4	71	4	5	69816	30006	6	6	6	10000	30010	70054	70054	70054	70054	70129

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	1	1	1	0	0	397	0	0	70036	69785	59695	25	40104	30103	10001	30100	10000	616175	3342398	1	49	66955	70054	70035	64748	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	54	10000	1	1	1	2611	2	71	2	3	69814	30003	10	10	0	10000	30100	70036	70055	70036	70036	70052
40204	70054	525	0	0	0	1	0	34	0	0	70039	69785	59695	25	40104	30103	10001	30100	10000	616041	3341470	1	49	66971	70054	70051	64647	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	2611	3	71	2	3	69817	30003	10	13	13	10000	30100	70052	70055	70055	70036	70055
40204	70054	524	0	0	0	0	1	42	0	0	70020	69785	59710	25	40104	30103	10001	30100	10000	616041	3342398	1	49	66971	70054	70054	64647	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	2611	3	71	3	2	69817	30003	13	10	13	10000	30100	70052	70055	70055	70052	70052
40204	70035	525	0	0	0	0	0	58	0	0	70039	69785	59695	25	40100	30103	10001	30100	10000	616175	3341470	1	49	66955	70054	70054	64647	3	64954	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	2611	3	71	2	3	69817	30000	0	13	13	10000	30100	70055	70055	70055	70055	70055
40204	70035	524	0	0	0	0	0	40	1	0	70039	69785	59713	25	40100	30103	10000	30100	10000	616175	3342398	1	49	66955	70054	70054	64647	3	64954	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	1	1	0	2611	2	71	2	3	69798	30003	10	13	13	10000	30100	70055	70036	70056	70036	70055
40204	70035	525	0	0	0	0	0	37	0	0	70036	69764	59713	25	40104	30100	10001	30100	10000	616041	3342254	1	49	66955	70054	70035	64647	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	2611	3	71	3	3	69817	30003	0	0	10	10000	30100	70052	70052	70055	70036	70055
40204	70097	525	0	0	0	0	0	40	1	0	70020	69785	59710	25	40104	30103	10001	30100	10000	616041	3342254	1	49	66974	70054	70054	64761	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	2611	2	71	3	3	69798	30000	10	0	13	10000	30100	70055	70036	70055	70036	70055
40204	70054	524	0	0	0	0	0	247	1	0	70039	69785	59713	25	40100	30103	10000	30100	10000	616041	3341470	1	49	66971	70054	70054	64647	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	1	0	10000	1	0	0	2611	3	71	2	3	69814	30003	0	10	10	10000	30100	70052	70036	70036	70057	70052
40204	70035	524	0	0	0	0	0	58	1	0	70096	69785	59695	25	40104	30100	10000	30100	10000	616041	3342398	1	49	66973	70035	70054	64765	3	64938	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	10000	1	0	0	2611	3	71	3	2	69798	30000	13	13	13	10000	30100	70055	70036	70036	70055	70055
40204	70054	524	0	0	0	1	1	52	1	0	70036	69785	59713	25	40104	30103	10001	30100	10000	616041	3342398	1	49	66955	70054	70035	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	1	0	2611	2	71	3	3	69798	30003	13	0	13	10000	30100	70052	70055	70055	70055	70055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	0	1	0	0	0	0	0	0	70020	69760	59709	25	40014	30010	10002	30010	10000	616982	3341470	5	1	49	66970	70050	70050	64668	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	1	0	10000	1	0	0	0	2520	0	15	71	15	6	69810	30003	9	6	9	10000	30010	70051	70051	70051	70093	70048
40024	70050	525	0	0	0	0	1	0	0	1	70035	69760	59709	25	40014	30013	10001	30010	10000	616982	3342206	4	0	49	66970	70047	70161	64668	3	64975	40010	30020	10000	60020	20000	70096	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	0	1	0	0	2520	0	13	71	13	15	69810	30003	9	0	9	10000	30010	70051	70036	70051	70036	70051
40024	70050	524	0	0	0	0	1	0	0	0	70035	69743	59709	25	40010	30013	10001	30010	10000	616982	3342062	3	0	49	66955	70035	70047	64668	3	64973	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	1	1	0	0	2520	0	14	71	15	13	69798	30000	6	9	6	10000	30010	70051	70051	70036	70048	70036
40024	70050	524	0	0	0	0	1	1	0	1	70035	69728	59695	25	40014	30013	10000	30010	10000	616952	3342062	2	0	49	66971	70050	70035	64668	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	1	3	10000	1	1	0	0	2520	0	16	71	17	16	69810	30003	6	0	9	10000	30010	70105	70053	70055	70051	70051
40024	70050	525	0	0	0	0	0	0	1	0	70040	69743	59706	25	40014	30013	10001	30010	10000	616982	3342062	3	0	49	66955	70050	70050	64668	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	0	1	0	0	2520	0	16	71	15	15	69810	30003	0	6	0	10000	30010	70051	70048	70051	70036	70051
40024	70065	525	0	0	0	0	1	1	1	0	70035	69728	59709	25	40014	30013	10000	30010	10000	616982	3342206	4	0	49	66970	70050	70050	64668	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	3	10000	0	0	0	0	2520	0	16	71	13	16	69813	30003	0	9	0	10000	30010	70036	70051	70048	70048	70036
40024	70047	524	0	0	0	0	0	0	1	1	70020	69760	59709	25	40014	30010	10001	30010	10000	617068	3342206	3	0	49	66970	70050	70035	64668	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	0	0	0	0	2520	2	7	71	16	7	69798	30000	9	6	9	10000	30010	70051	70036	70036	70036	70051
40024	70050	525	0	0	0	0	0	0	0	0	70032	69743	59695	25	40010	30013	10001	30010	10000	616982	3341470	3	0	49	66955	70047	70050	64668	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	1	1	0	0	2520	2	16	71	13	15	69798	30000	6	0	9	10000	30010	70036	70051	70051	70088	70051
40024	70035	525	0	0	0	0	0	0	0	0	70035	69743	59695	25	40014	30010	10001	30010	10000	617068	3342062	3	0	49	66955	70050	70035	64668	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	0	1	0	0	2520	0	16	71	16	8	69813	30003	9	0	0	10000	30010	70036	70051	70051	70051	70051
40024	70055	525	0	0	0	0	1	0	1	1	70035	69760	59714	25	40014	30013	10000	30010	10000	616982	3341470	3	1	49	66970	70050	70050	64653	3	64975	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	1	1	0	0	2520	0	15	71	16	17	69813	30000	6	6	0	10000	30010	70036	70051	70051	70051	70036

Test 4: throughput

Count: 8

Code:

  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26736	200	1	2	0	1	2	1	0	1	67	0	0	5	26722	3	7	7	20	25	80100	100	80000	103	80016	500	1168603	1	49	23656	26737	26736	16642	6	16666	80115	200	80024	200	160048	26714	64	1	1	80201	100	99	0	100	80000	100	80000	1	100	80021	19	43	0	80058	1	0	1	21	80039	6	0	59	43	19	2	1	1	1	5122	11	16	10	10	26733	13	13	5	80000	100	26737	26715	26737	26737	26737
80204	26736	200	1	2	0	1	2	1	0	0	21	1	0	3	26721	3	7	7	20	25	80100	100	80000	100	80016	500	1167300	1	49	23634	26736	26737	16664	6	16692	80115	200	80024	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	43	0	80059	0	0	0	21	80040	0	0	59	43	19	0	1	1	1	5122	10	16	10	10	26711	13	13	5	80000	100	26738	26715	26737	26737	26737
80204	26736	200	1	2	0	1	2	1	0	0	66	0	0	4	26721	3	7	7	20	25	80100	100	80000	100	80015	500	1167300	1	49	23656	26737	26736	16642	6	16666	80113	200	80024	200	160048	26714	64	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	43	0	80058	0	0	0	61	80040	6	0	19	43	19	0	1	1	1	5122	10	16	10	5	26733	13	0	0	80000	100	26737	26715	26737	26715	26737
80204	26714	200	1	2	0	1	2	0	1	1	66	0	0	5	26722	3	7	7	20	25	80100	100	80000	100	80015	500	1167377	1	49	23656	26737	26736	16664	6	16688	80115	200	80024	200	160048	26714	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	20	0	0	80059	0	0	0	61	80039	6	0	58	43	19	2	1	1	1	5122	10	16	10	9	26733	0	13	0	80000	100	26715	26737	26737	26737	26737
80204	26714	200	1	2	0	0	2	0	0	0	21	0	0	2	26721	3	7	7	20	25	80100	100	80000	100	80016	500	1167300	1	49	23656	26736	26736	16663	6	16688	80115	200	80024	200	160048	26736	86	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	0	0	80019	1	0	1	60	80040	6	0	59	0	19	2	1	1	1	5122	4	16	4	10	26711	13	0	5	80000	100	26738	26738	26738	26716	26715
80204	26736	200	1	2	0	1	2	1	0	1	67	0	0	5	26699	2	7	7	2	25	80100	100	80000	100	80015	500	1166590	1	49	23668	26736	26714	16664	6	16688	80115	200	80024	200	160048	26714	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	0	0	80060	0	0	0	63	80040	0	1	19	43	19	0	1	1	1	5122	9	16	10	10	26711	13	13	0	80000	100	26737	26737	26737	26737	26715
80204	26736	200	1	2	0	1	2	1	0	0	67	0	0	3	26721	3	7	7	1	25	80100	100	80000	100	80015	500	1167628	1	49	23656	26714	26736	16663	6	16688	80115	200	80024	200	160048	26714	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	43	0	80059	1	0	0	61	80000	6	0	19	43	19	1	1	1	1	5122	5	16	10	10	26733	13	13	5	80000	100	26737	26716	26737	26738	26737
80204	26714	201	1	2	0	0	2	1	1	1	66	0	0	4	26721	3	7	0	20	25	80100	100	80000	100	80016	500	1167377	1	49	23656	26736	26736	16663	6	16687	80115	200	80024	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	21	43	0	80059	0	0	0	60	80040	6	1	59	43	19	2	1	1	1	5122	4	16	10	9	26733	0	13	5	80000	100	26737	26738	26738	26738	26715
80204	26737	200	1	2	0	1	2	1	1	0	66	1	0	4	26699	0	0	7	18	25	80100	100	80000	100	80014	546	1176200	1	49	23656	26736	26737	16666	6	16687	80115	200	80024	200	160048	26744	63	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	20	0	0	80058	0	1	1	21	80000	0	1	58	43	19	2	1	1	1	5122	4	16	10	9	26733	13	0	5	80000	100	26715	26737	26737	26737	26715
80204	26737	200	1	2	0	1	2	0	0	0	21	0	0	4	26721	3	7	7	19	25	80100	100	80000	100	80198	500	1167215	1	49	23634	26736	26736	16642	6	16688	80115	200	80024	200	160048	26736	64	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	20	43	0	80059	0	0	0	61	80000	6	0	58	0	19	1	1	1	1	5122	9	16	10	10	26733	13	13	0	80000	100	26715	26737	26715	26715	26738

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26737	201	0	0	0	0	0	45	0	1	3	26700	2	0	7	19	25	80010	10	80000	10	80000	50	1173975	3	1	49	23656	26736	26737	16681	3	16717	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80000	0	39	80000	6	0	58	0	19	1	5020	0	5	16	4	4	26734	13	0	5	80000	10	26737	26737	26737	26737	26716
80024	26737	200	1	0	1	0	0	21	0	0	0	26713	0	12	12	16	25	80010	10	80000	10	80000	50	1166886	6	1	49	23656	26721	26708	16672	3	16707	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80039	0	39	80039	0	1	39	0	0	0	5020	0	4	16	4	3	26724	10	10	4	80000	10	26709	26709	26728	26728	26731
80024	26727	200	0	0	0	1	0	45	0	1	1	26712	2	12	0	0	25	80010	10	80000	10	80000	50	1168843	7	1	49	23651	26708	26727	16672	3	16711	80010	20	80000	20	160000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80000	0	39	80000	6	1	39	43	0	0	5020	0	3	16	3	4	26705	14	14	4	80000	10	26728	26728	26728	26729	26729
80024	26728	199	0	0	0	0	0	0	0	1	1	26693	0	12	1	16	25	80010	10	80000	10	80000	50	1167501	6	1	49	23647	26728	26708	16676	3	16708	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80000	0	39	80039	6	1	39	43	0	0	5020	0	4	16	4	4	26725	10	10	4	80000	10	26728	26728	26728	26728	26729
80024	26728	200	0	0	0	0	0	45	0	1	1	26716	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	6	1	49	23628	26727	26727	16672	3	16688	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	0	38	80039	6	1	0	44	0	0	5020	0	4	16	4	3	26724	10	0	4	80000	10	26709	26709	26728	26732	26709
80024	26708	200	0	0	0	0	0	44	0	1	1	26712	0	12	12	16	25	80010	10	80000	10	80000	50	1168843	6	1	49	23651	26728	26728	16652	3	16707	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	1	39	80039	0	1	39	43	0	0	5020	0	4	16	4	3	26705	10	0	0	80000	10	26729	26709	26732	26729	26728
80024	26727	199	0	0	0	1	1	45	0	0	1	26712	2	0	12	16	25	80010	10	80000	10	80000	50	1168843	6	1	49	23647	26728	26731	16672	3	16688	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80039	0	0	80039	0	0	0	0	0	0	5020	0	3	16	3	4	26724	0	10	4	80000	10	26729	26729	26729	26729	26728
80024	26708	200	0	0	0	0	0	45	0	1	1	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	7	1	49	23628	26727	26727	16672	3	16707	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80000	0	42	80000	0	1	0	43	0	0	5020	0	4	16	4	3	26727	0	10	4	80000	10	26728	26729	26731	26729	26729
80024	26727	200	0	0	0	0	0	45	0	0	1	26713	2	12	12	16	25	80010	10	80000	10	80000	50	1166750	8	1	49	23648	26727	26708	16672	3	16708	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	0	39	80039	0	1	39	43	0	0	5020	0	4	16	4	3	26724	10	10	0	80000	10	26729	26729	26729	26709	26728
80024	26728	200	0	0	0	0	0	45	0	1	1	26712	2	12	12	0	25	80010	10	80000	10	80000	50	1168843	6	1	49	23628	26728	26728	16672	3	16707	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	1	42	80039	6	0	39	43	0	0	5020	0	4	16	4	4	26725	10	0	7	80000	10	26709	26729	26729	26709	26728

LDR (register, sxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations