Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

BICS (register, 32-bit)

Test 1: uops

Code:

  bics w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004103580061917251000100010006225010351035805388210001000200010354011100110000073127119931000100010361036103610361036
10041035800101917251000100010006225010351035805388210001000200010354011100110000073127119931000100010361036103610361036
1004103570061917251000100010006225010351035805388210001000200010354011100110000073127119931000100010361036103610361036
1004103571061917251000100010006225010351035805388210001000200010354011100110000073127119931000100010361036103610361036
1004103580061917251000100010006225010351035805388210001000200010354011100110000073127119931000100010361036103610361036
1004103580061917251000100010006225010351035805388210001000200010354011100110000073127119931000100010361036103610361036
1004103580061917251000100010006225010351035805388210001000200010354011100110000073127119931000100010361036103610361036
1004103570061917251000100010006225010351035805388210001000200010354011100110000073127119931000100010361036103610361036
1004103580061917251000100010006225010351035805388210001000200010354011100110000073127119931000100010361036103610361036
1004103580061917251000100010006225010351035805388210001000200010354011100110000073127119931000100010361036103610361036

Test 2: Latency 1->2

Code:

  bics w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)0318191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357500061992725101001010010110647212496955100351003586737873510110102242024810035401110201100991001010010003111719016001001310000101001003610036100361003610036
1020410035750006199272510100101001011064721249695510035100358673887351011010224202481003540111020110099100101001001300071012711999510000101001003610036100361003610036
10204100357500082992025101001010010100647152496955100351003586563873210100102002020010035401110201100991001010010019000710127111002810000101001003610036100361003610036
10204100357500016899202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001000000071012711999510000101001003610036100361003610036
1020410035750006199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001001600071012711999510000101001003610036100361003610036
1020410035760006199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001000000071012711999510000101001003610036100361003610036
10204100357500019599202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001000000071012711999510000101001003610036100361003610036
1020410035780006199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001000000071012711999510000101001003610036100361003610036
1020410035750006199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001000000071012711999510000101001003610036100361003610036
10204100357500044199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001000000071012711999510000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)1e3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002410035751631466991825100101001010010647246496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
10024100357500061991825100101001010010647246496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
100241007175000156991825100101001010010647246496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
10024100357600061991825100101001010010647246496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
10024100357500061991825100101001010010647246496955100351003586783875410010100202002010035403110021109101001010064022722999710000100101003610036100361003610036
100241003575075061991825100101001010010647246496955100351003586783875410010100202002010035401110021109101001010364022722999710000100101003610036100361003610036
10024100357500061991825100101001010010647246496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
1002410035750315061991825100101001010010647246496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
10024100357500061991825100101001010010647246496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
10024100357500061991825100101001010010647246496955100351022686893875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036

Test 3: Latency 1->3

Code:

  bics w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020410035751261992025101001010010100647152496955100351003586563873210100102002020010035401110201100991001010010000071012711999510000101001003610036100361003610036
102041003575061992025101001010010100647152496955100351003586563873210100102002020010035401110201100991001010010000071012711999510000101001003610036100361003610036
1020410035751261992025101001010010100647152496955100351003586563873210100102002020010035401110201100991001010010000071012711999510000101001003610036100361003610036
1020410035750189992025101001010010100647152496955100351003586563873210100102002020010035401110201100991001010010040071012711999510000101001003610036100361003610036
10204100357512103992025101001010010100647152496955100351003586563873210100102962020010035401110201100991001010010000071012711999510000101001003610036100361003610036
102041003575061992025101001010010100647152496955100351003586563873210100102002020010035401110201100991001010010000071012711999510000101001003610036100361003610036
102041003575061992025101001010010100647152496955100351003586563873210100102002020010035401110201100991001010010000071012711999510000101001003610036100361003610036
102041003575061992025101001010010100647152496955100351003586563873210100102002020010035401110201100991001010010000071012711999510000101001003610036100361003610036
102041003576061992025101001010010100647152496955100351003586563873210100102002020010035401110201100991001010010000071012711999510000101001003610036100361003610036
1020410035760147992025101001010010100647152496955100351003586568873210100102002020010035401110201100991001010010000071012711999510000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002410035750619918251001010010100106472460496955100351003587113875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
1002410035750619918251001010010100106472461496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
1002410035750619918251001010010100106472460496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
1002410035750619918251001010010100106472461496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
1002410035750619918251001010010100106472460496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
1002410035750619918251001010010100106472460496955100351003586783875410010100202002010035401110021109101001010065722722999710000100101003610036100361003610036
1002410035750619918251001010010100106472461496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
1002410035750619918251001010010100106472460496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
1002410035750619918251001010010100106472460496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036
1002410035760619918251001010010100106472460496955100351003586783875410010100202002010035401110021109101001010064022722999710000100101003610036100361003610036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  bics w0, w1, w2
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204202641522001152816352010831993912720144201902052312997661491722620219200351746036176122061220312309412029664512020110099100201001010000212395521111408364112018020113201002026620262202702026320266
20204202631522100005552528113971992815120214202142052812997301491718120261202621750029176122052320688310872026264612020110099100201001010020202400801111406056012018020113201002031020266202642003620219
20204202191520010056540440013111992614720214202132052313003590491718120309202181747421175882044120717309592026564612020110099100201001010004002401561111424172022021420153201002012720308203102031120311
20204203081520100166924440017801992714920261202642065413011450491722820308203071745531176642061220615310842030964712020110099100201001010042202403301111407232012017920111201002026320262200362026520036
202042026115101101506608811320199251302019120146202771298471149169552003520035174258174852011220224302362003564112020110099100201001010000000001111320016002001220000201002003620036200362003620036
202042003515000000000006119930252010020100201121297233149169552003520035174257174862011220224302362003564112020110099100201001010000100001111319016002001220000201002003620036200362003620036
202042003515000000000006119930252010020100201121297233149169552003520035174258174862011220224302362003564112020110099100201001010000000001111320016002001220000201002003620036200362003620036
202042003515000000000006119930252010020100201121297233149169552003520035174258174852011220224302362003564112020110099100201001010000000001111320016002001220000201002003620036200362003620036
2020420035150000000000053619930252010020100201121297233149169552003520035174258174862011220224302362003564112020110099100201001010000000001111319016002001220000201002003620036200362003620036
202042003515000000000006119930252010020100201121297233149169552003520035174258174852011220224302362003564112020110099100201001010000000001111319016002001220000201002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024200351500061199182520010200102001012972471491695520035200351742831750420010200203002020035641120021109102001010010000001270627441999520000200102003620036200362003620036
20024200351500061199182520010200102001012972470491695520035200351742831750420010200203002020035641120021109102001010010000001270327331999520000200102003620036200362003620036
20024200351500015619918252001020010200101297247049169552003520035174283175042001020020300202003564112002110910200101001000126001270327441999520000200102003620036200362003620036
20024200801500061199182520010200102001012972471491695520035200351742831750420010200203002020035641120021109102001010010000001270327331999520000200102003620036200362003620036
20024200351500061199182520010200102001012972471491695520035200351742831750420010200203002020035641120021109102001010010000001270327331999520000200102003620036200362003620036
20024200351490061199182520010200102001012972471491695520035200351742831750420010200203002020035641120021109102001010010000001270327531999520000200102003620036200362003620036
20024200351500061199182520010200102001012972470491695520035200351742831750420010200203002020035641120021109102001010010000001270427431999520000200102003620036200362003620036
20024200351500061199182520010200102001012972471491695520035200351742831750420010200203002020035641120021109102001010010000001270327331999520000200102003620036200362003620036
20024200351500061199182520010200102001012972471491695520035200351742831750420010200203002020035641120021109102001010010000001270427331999520000200102003620036200362003620036
20024200351500061199182520010200102001012972470491695520035200351742831750420010200203002020035641120021109102001010010000001270427331999520000200102003620036200362003620036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  bics w0, w1, w2
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202042003515006119930252010020100201121297233149169552003520035174257174862011220224302362003564112020110099100201001010056111131916002001220000201002003620036200362003620036
202042003515006119930252010020100201121297233149169552003520035174258174852011220224302362003564112020110099100201001010000111131916102001220000201002003620036200362003620036
202042003515006119930252010020100201121297233149169552003520035174257174862011220224302362003564112020110099100201001010000111132016002001220000201002003620036200362003620036
2020420035150061199302520100201002011212972331491695520035200351742581748620112202243023620035641120201100991002010010100018111132016002001220000201002003620036200362003620036
202042003515006119930252010020100201121297233149169552003520035174257174862011220224302362003564112020110099100201001010017102111131916002001220000201002003620036200362003620036
202042003515006119930252010020100201121297233149169552003520035174258174862011220224302362003564112020110099100201001010025177111131916002001220000201002003620036200362003620036
202042003515006119930252010020100201121297233149169552003520035174257174862011220224302362003564112020110099100201001010000111131916002001220000201002003620036200362003620036
202042003515006119930252010020100201121297233149169552003520035174257174862011220224302362003564112020110099100201001010099111131916002001220000201002003620036200362003620036
202042003515006119930252010020100201121297233149171372003520035174258174852011220224302362003564112020110099100201001010000111131916002001220000201002003620036200362003620036
202042003515006119930252010020100201121297233149169552003520035174258174852011220224302362003564112020110099100201001010003111132016002001220000201002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? int retires (ef)f5f6f7f8fd
20024200351500010006119918252001020010200101297247114916955200352003517428317504200102002030020200356411200211091020010100105000127001272219995200000200102003620036200362003620036
200242003515000000061199182520010200102001012972470149169552003520035174283175042001020020300202003564112002110910200101001056870127002272119995200000200102003620036200362003620036
200242003515000000025119918252001020010200101297247114916955200352003517428317504200102002030020200356411200211091020010100105200127002271120028200000200102003620036200362003620036
2002420035150000000611991825200102001020010129724710491695520035200351742831750420010200203002020035641120021109102001010010411800127002272119995200000200102003620036200362003620036
200242003515000000061199182520010200102001012978740149169552003520035174283175042001020020300202003564112002110910200101001042720127002271219995200000200102003620036200362003620036
2002420035150000000611991825200102001020010129724700491695520035200351742831750420010200203002020035641120021109102001010010391230127002272119995200000200102003620036200362003620036
20024200351500000006119918252001020010200101297247004916955200792003517428317504200102002030020200356411200211091020010100104900127002272119995200000200102003620036200362003620036
200242003515000000025219918252001020010200101297247114916955200352003517428317504200102002030020200356411200211091020010100104800127002271219995200000200102003620036200362003620036
20024200351500000006119918252001020010200101297247004916955200352003517428317504200102002030020200356411200211091020010100105100127002271119995200000200102003620036200362003620036
20024200351500000006119918252001020010200101297247004916955200352003517428317504200102002030020200356411200211091020010100104800127002272219995200000200102003620036200362003620036

Test 6: throughput

Count: 8

Code:

  bics w0, w8, w9
  bics w1, w8, w9
  bics w2, w8, w9
  bics w3, w8, w9
  bics w4, w8, w9
  bics w5, w8, w9
  bics w6, w8, w9
  bics w7, w8, w9
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802042674020011000002392580100801008010040050014923655267352673516672316690801008020016020026735391180201100991008010010005104805112719882673180000801002673626736267362673626736
802042673520011000570239258010080100801004005001492365526735267351667231669080100802001602002673539118020110099100801001000810605112819882673180000801002673626736267362673626736
8020426735200110000013925801008010080100400500149236552673526735166723166908010080200160200267353911802011009910080100100000005112719772673180000801002673626736267362673626736
8020426735201110000013925801008010080100400500149236552673526735166723166908010080200160200267353911802011009910080100100000005112719772673180000801002673626736267362673626736
8020426735200110000013925801008010080100400500149236552673526735166723166908010080200160200267353911802011009910080100100000005112919652673180000801002673626736267362688226736
8020426735201110000023925801008010080100400500149236552673526735166723166908010080200160200267353911802011009910080100100000005112719782673180000801002673626736267362673626736
8020426735200110000013925801008010080100400500149236552673526735166723166908010080200160200267353911802011009910080100100000005112719782673180000801002673626736267362673626736
8020426735200110000013925801008010080100400500149236552673526735166723166908010080200160200267353911802011009910080100100000005112719852673180000801002673626736267362673626736
8020426735200110000013925801008010080100400500149236552673526735166723166908018780200160200267353911802011009910080100100000005112719772673180000801002673626736267362673626736
8020426735200110000013925801008010080100400500149236552673526735166723166908010080200160200267353911802011009910080100100000005112819882673180000801002673626736267362673626736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800242671120003525800108001080010400050149236252670526705166653166838001080020160020267053911800211091080010101050200518352670280000800102670626706267062670626706
800242670520003525800108001080010400050049236252670526705166653166838001080020160020267053911800211091080010102050200518632670280000800102670626706267062670626706
800242670520003567800108001080010400050049236252670526705166653166838001080020160020267053911800211091080010101050200318652670280000800102670626706267062670626706
8002426705200035258001080010800104000501492362526705267051666531668380010800201600202670539118002110910800101020350200518542670280000800102670626706267062670626706
800242670520003525800108001080010400050049236252670526705166653166838001080020160020267053911800211091080010101050200318542670280000800102670626706267062670626706
800242670520003525800108001080010400050149236252670526705166653166838001080020160020267053911800211091080010101050200318352670280000800102670626706267062670626706
8002426705200035258001080010800104000500492362526705267051666531668380010800201600202670539118002110910800101030950200518532670280000800102670626706267062670626706
8002426705200035258027080010800104000500492362526705267051666531668380010800201600202670539118002110910800101022350200318532670280000800102670626706267062670626706
800242670520003525800108001080010400050049236252670526705166653166838001080020160020267053911800211091080010101050200518552670280000800102670626706267062670626706
800242670520003525800108001080010400050149236252670526705166653166838001080020160020267053911800211091080010100050200318552670280000800102670626706267062670626706