Firestorm: BICS (register, 32-bit) measurements

Code:

  bics w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	101	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	1	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  bics w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	61	9927	25	10100	10100	10110	647212	49	6955	10035	10035	8673	7	8735	10110	10224	20248	10035	40	1	1	10201	100	99	100	10100	100	0	3	1	1	1	719	0	16	0	0	10013	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10100	10100	10110	647212	49	6955	10035	10035	8673	8	8735	10110	10224	20248	10035	40	1	1	10201	100	99	100	10100	100	1	3	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	82	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	1	9	0	0	0	710	1	27	1	1	10028	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	168	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	1	6	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	195	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	78	0	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	441	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	1	63	1	466	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10071	75	0	0	0	156	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	3	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	3	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	315	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10226	8689	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  bics w0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	12	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	12	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	189	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	4	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	12	103	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10296	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	147	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	8	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8711	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	657	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  bics w0, w1, w2
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20264	152	2	0	0	1	1	5	2	816	352	0	1083	19939	127	20144	20190	20523	1299766	1	49	17226	20219	20035	17460	36	17612	20612	20312	30941	20296	64	5	1	20201	100	99	100	20100	10100	0	0	2	1	2	3955	2	1	1	1	1408	3	64	1	1	20180	20113	20100	20266	20262	20270	20263	20266
20204	20263	152	2	1	0	0	0	0	5	552	528	1	1397	19928	151	20214	20214	20528	1299730	1	49	17181	20261	20262	17500	29	17612	20523	20688	31087	20262	64	6	1	20201	100	99	100	20100	10100	2	0	2	0	2	4008	0	1	1	1	1406	0	56	0	1	20180	20113	20100	20310	20266	20264	20036	20219
20204	20219	152	0	0	1	0	0	5	6	540	440	0	1311	19926	147	20214	20213	20523	1300359	0	49	17181	20309	20218	17474	21	17588	20441	20717	30959	20265	64	6	1	20201	100	99	100	20100	10100	0	4	0	0	2	4015	6	1	1	1	1424	1	72	0	2	20214	20153	20100	20127	20308	20310	20311	20311
20204	20308	152	0	1	0	0	1	6	6	924	440	0	1780	19927	149	20261	20264	20654	1301145	0	49	17228	20308	20307	17455	31	17664	20612	20615	31084	20309	64	7	1	20201	100	99	100	20100	10100	4	2	2	0	2	4033	0	1	1	1	1407	2	32	0	1	20179	20111	20100	20263	20262	20036	20265	20036
20204	20261	151	0	1	1	0	1	5	0	660	88	1	1320	19925	130	20191	20146	20277	1298471	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1320	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	0	0	0	0	1	1	1	1319	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1320	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1320	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	0	0	0	536	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	6	27	4	4	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	156	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	126	0	0	1270	3	27	4	4	19995	20000	20010	20036	20036	20036	20036	20036
20024	20080	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	149	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	3	27	5	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	4	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  bics w0, w1, w2
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	5	6	1	1	1	1319	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	1	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	18	1	1	1	1320	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	17	102	1	1	1	1319	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	25	177	1	1	1	1319	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	9	9	1	1	1	1319	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	17137	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	3	1	1	1	1320	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	1	0	0	0	61	19918	25	20010	20010	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	50	0	0	1270	0	1	27	2	2	19995	20000	0	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	56	87	0	1270	0	2	27	2	1	19995	20000	0	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	251	19918	25	20010	20010	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	52	0	0	1270	0	2	27	1	1	20028	20000	0	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	41	180	0	1270	0	2	27	2	1	19995	20000	0	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297874	0	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	42	72	0	1270	0	2	27	1	2	19995	20000	0	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	39	123	0	1270	0	2	27	2	1	19995	20000	0	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	0	49	16955	20079	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	49	0	0	1270	0	2	27	2	1	19995	20000	0	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	252	19918	25	20010	20010	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	48	0	0	1270	0	2	27	1	2	19995	20000	0	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	51	0	0	1270	0	2	27	1	1	19995	20000	0	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	48	0	0	1270	0	2	27	2	2	19995	20000	0	20010	20036	20036	20036	20036	20036

Test 6: throughput

Count: 8

Code:

  bics w0, w8, w9
  bics w1, w8, w9
  bics w2, w8, w9
  bics w3, w8, w9
  bics w4, w8, w9
  bics w5, w8, w9
  bics w6, w8, w9
  bics w7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26740	200	1	1	0	0	0	0	0	2	39	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	51	0	48	0	5112	7	19	8	8	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	1	1	0	0	0	57	0	2	39	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	81	0	6	0	5112	8	19	8	8	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	1	1	0	0	0	0	0	1	39	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5112	7	19	7	7	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	201	1	1	0	0	0	0	0	1	39	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5112	7	19	7	7	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	1	1	0	0	0	0	0	1	39	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5112	9	19	6	5	26731	80000	80100	26736	26736	26736	26882	26736
80204	26735	201	1	1	0	0	0	0	0	2	39	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5112	7	19	7	8	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	1	1	0	0	0	0	0	1	39	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5112	7	19	7	8	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	1	1	0	0	0	0	0	1	39	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5112	7	19	8	5	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	1	1	0	0	0	0	0	1	39	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80187	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5112	7	19	7	7	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	1	1	0	0	0	0	0	1	39	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5112	8	19	8	8	26731	80000	80100	26736	26736	26736	26736	26736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26711	200	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	1	0	5020	0	5	18	3	5	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	2	0	5020	0	5	18	6	3	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	67	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	1	0	5020	0	3	18	6	5	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	20	3	5020	0	5	18	5	4	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	1	0	5020	0	3	18	5	4	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	1	0	5020	0	3	18	3	5	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	30	9	5020	0	5	18	5	3	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80270	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	22	3	5020	0	3	18	5	3	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	1	0	5020	0	5	18	5	5	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	3	18	5	5	26702	80000	80010	26706	26706	26706	26706	26706

BICS (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations