Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STADDL (64-bit)

Test 1: uops

Code:

  staddl x0, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 70 nops): 3.000

Issues: 3.006

Integer unit issues: 1.005

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)09l2 tlb miss instruction (0a)0e18191e22243a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafbbl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)cfd0d1d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
73005331312487110000104510579333013112098130051006200010002000110491695724930096327853297531530001000200020004000332772591117100110001000020000221005100004200552216121116591827537842882327837784454257272324711008174501502215358200010003300433022329673286432912
73004330062475002000100500585532918112087330071007200010002000110451695744929932328453293731030001000200020004000329892599117100110001000020000221005100008200542215693118842834240193652294038654444146462324501007174001556115715200010003312733065329263311032941
730043298924810000000100700582832919112101930081007200010002000110191696424929988329003308331030001000200020004000329302599117100110001000020000221004100015200642216074116561818438204662305437564445166567326071005171931529215699200010003314132944328463297233021
730043302124870000001009005803328531120948300610072000100020001105716970104929916327153318031030001000200020004000328862615117100110001000020000221005100005200332216052118031832538202682306338384458237272324861007168131553816178200010003292033152329863295133022
73004330592475000000100600590133062112109730041004200010002000110921688694929921329013314131030001000200020004000329592617117100110001000020000221003100003200332215884117492831439310652302538884456296663326531006167861532915307200010003304532983330233312633097
73004330042476000000100910594832886112084930041004200010012000109811690044930092328733290431030001000200020004000331262629117100110001000020000221003100003200332215964117890826139233662315338554458246459324601004172651529215240200010003285832938328483293833062
73004332452467000000100400595633105112085530061007200010002000110771696824930014327783299931030001000200020004000331542572117100110001000020000221005100013200332216121119222833737912722305638594444246768325521005174791520815938200010003302933057331143302833126
73004330932476000000103010583932864112087030041007200010002000109981689124929951327843299631530001000200020004000331822582117100110001000120000221003100003200452215972114143827038182652301938514454246768326081005172271519816204200010003295732938329143287833034
73004331682475000000100400576132997112082730091004200010002000110451698284930086327823315131330001000200020004000330952561117100110001000020000221003100003200632216063117802819639191682315738534458177172324381004169351545715454200010003307532813329083298933080
73004329752464000000100900597932906112119530041004200010002000109731689354930039329623308231330001000200020004000329662543117100110001000020000221003100006200652215729115181837437951642302637944457206862324901009170901540615991200010003293433126328953308232918

Test 2: throughput

Code:

  staddl x0, [x6]
  add x6, x6, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0125

retire uop (01)cycle (02)03l1d tlb fill (05)0e0f191e1f2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
40209701345261000724308141720771687010377861201265720325408632073320000201002000020481193323359020849670397007770119645553650814010020200200003020040000701176711202011009910010000101001000001002087611688431993310978102492600890549852111722091430108000013101161169911206276620000201007011470123701247012670127
402047012352500007292083717767115670105819613613456853254090120787200002010020000204814533230300157496704470083701206456036508040100202002000030200400007012267112020110099100100001010010000010020952123579519935108991023628238813411372119722381440107200013101161169913206516620000201007012770128701347012970123
402047012752500007184083517368614870111821411813357032254085420716200002010020000204759333237380106496704570086701196456336507940100202002000030200400007012168112020110099100100001010010000010020876108679519933108681023925439013610162116722241384105600013101161169914206306620000201007012570115701237012270121
402047012552500007323083317128215670104861312712557705254067020707200002010020000204859133235591102496704470077701276455936507940100202002000030200400007013368112020110099100100001010010000010020883115381919933108691026228338933211532114522030411119201013101161169945205726620000201007012070125701237012170122
402047011652500007342082117207915670113811613513657378254093720780200002010020000204782833232000170496704470078701216456036508340100202002000030200400007011768112020110099100100001010010000010020892118282019925108861025027039135411252113022381448104800013101161169911205786620000201007011970122701297012770124
402047012652500007314082517128016070106805713613457101254089120786200002010020000204800233235190116496704470086701246456236508040100202002000030200400007012168112020110099100100001010010000010020914120576019932108791024029239093811722115522121391122400013101161169906206606620000201007012470126701317013070126
402047012452500047340080017047512470110768512313957183254071720900200002010020000204851433235850158496704370085701186456236507940100202002000030200400007012067112020110099100100001010010000010020882113782319926108681024729639033411082112722221427106400013101161169915206166620000201007012470125701287012870119
40204701245250000739908321696881527011077031331275779125406842092020000201002000020479833322969173496704270081701256456336508240100202002000030200400007012168112020110099100100001010010000010020896117778919932109071020428938995011122113422140411116000013101161169913207376620000201007012570126701257012770123
4020470124525000072160784176889152701088034132143572962540889207152000020100200002048067332307411144967043700847012664564365085401002020020155302004000070134133112020110099100100001010010000010020930116382319930108791026228338613410822112022471393105600013101161169905208326620000201007012170120701197012570122
4020470120525010073040821165682136701048303116140576982540908206692000020100200002048612332396608349670387008970126645593650804010020200200003020040000701276811202011009910010000101001000001002092811977721993010915102472763921341030211402211039897600013101161169907207286620000201007012570124701287012370127

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0126

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
400297014752510101007256081717361121367011381221132140613825644416421992200002001020000204704333226250242497925781937780497401021673174448792246522809332224513678598671912002110910100001001010000110215970120572020333108381025826218811701136210605196041711121201270216116991620844101020000200107013170128701267012870128
4002470124525101000071481801167210210870112805261331445614325405872077820000200102000020480813322060028049670487008370126645903651104001020020200003002040000701296911200211091010000100101000001020895211297861993510856102492951914401028211275214138910481201270116117000120701101020000200107013270129701307012972126
400247012452610000007238182817521111407010976920146149565852540797207342000020010200002047410332223707549670467008770128645893651064001020020200003002040000701286911200211091010000100101000001020944412147811993710903102402855897381101211025238240810242001270116126991420624101020000200107012970124701267012870132
40024701285252200000719427971720891087011982422147144571762540749206172000020010200002047820332307301884967047700847012864586365106400102002020000300204000070124691120021109101000010010100000102089911064765199341087010256258187352999211185192234910082201270116116991220586101020000200107012570128701317012870128
400247013252520000007392280516969214070111790241381465556225405932061020000200102000020471683322204027249670477008870132645863651114001020020200003002040000701246811200211091010000100101000001020904612028101992910886102452731889901054211275193239810962001270116116991320946101020000200107012970132701277012670123
400247012852522200007420280717048915670109790291411455606625407392076720000200102000020473933322639020349670467008570129645873651084001020020200003002040000701316811200211091010000100101000001020904211378191993410873102522671965361034211605197241411282201270116116991520587101020000200107013570129701297013270130
4002470126525202000071722831173610516070112834311421605673625406072086720000200102000020482393323973026949670477008470127645853651074001020020200003002040000701256911200211091010000100101000001020914211607731992910861102602711869361069211035171135911601001270116116991420683101020000200107013270130701257013170126
4002470125525111000172561800178410211670111785301291425619825407132064920000200102000020478203322637015549670467009270129645913651084001020020200003002040000701236811200211091010000100101000001020907312648031993310868102552821917341046211185201140010321101270116116991920581101020000200107012870129701287012970133
400247013552510100007239182717361011007011477918142132570942540581210102000020010200002047536332227701204967046700857012864583365107400102002020000300204000070132701120021109101000010010100000102093041015776199281086710266273189534105821126519513969281101270116116991520674101020000200107012770125701307012870124
400247012252510000007338180517368816870113784171321535602325406772077320000200102000020472663323543025349670457008470127645853651004001020020200003002040000701266811200211091010000100101000001020868211527641993010839102382841887321020211095188139110481001270116116991220937101020000200107012970128701297012970130

Test 3: throughput

Code:

  staddl x0, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 22.0127

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f22243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
3020622013716490100000274531100220090164202719255049627783231521010020000850393910524120149349217045022013322014121544562163063010017202001102002000020200400002201078881110201100991001000010010000010020000302227276100001166273665616957119300111722103492242021936919927812101002000010100220144220140220082220146220114
302052201251648000000027385010022014618720162925506132789022968101002000085788081052437215154921705132201612201292154256216335301001849231310203200052020640009220103866111020110099100100001001000001002000001626471100000171543736517029018310111716109400160021944513627351131002000010100220126220109220150220117222371
3020422009116491010000268370100220130043202440255001427170232281010020000845386710526321154049217045022009522013721541962163293010016312021102032000520206400092201178882110201100991001000010010000010020142312527246100011167803691116770119310111716104370160021945916926878101002000010100222277220126220145220123220111
302042201231648000100028981110022009618820259825507752762923137101002000084031391052503814884921404402201192201192154086216359301002021178510203200052020640009220101904111020110099100100001001000001002000032192716810000017221368661705612030011171697050160021940414627410101002000010100220096220126220119220124220126
302042201131649000000027341010022016618102023372550839274582338610100200008533466105259031491492170430220111220117215445621630730100183114501020320005202064000922013586211102011009910010000100100000100200003017269661000021724036725170381030011171610006016002194411702783601002000010100220162220106220139220102220108
302042201351649000000026718110022011001010202073255067927395233661010020000852543410525478148349217045022013522011321549362163353010018752011102032000520206400092201218821110201100991001000010010000010020000302026931100010174493699817558100011171610441016002193811532752010002000010100220197220129220146220142220124
302042201371649000000027640010022009608020214125510002765123275101002000084618871052476315714921707102201292201432154396216365301001980207510203200052020640009220137873111020110099100100001001000001002000032262706310000016782371081678011230011171710268016002194371992767801002000010100220152220119220110220114220126
30204220151164900010002693310012201320902019862550791276522319610100200008415367105253640459492170630220161220122215467621636730239167016721020320005202064000922011197011102011009910010000100100000100200003019273101000001731837149173431180011171696360160021944919127678101002000010100222355220160220150220120220098
3020422013916530000000271731100220098068202105255065727944230431010020000864467010526230049449217079022012522013121549662163313010019772031102032000520206400092201238821110201100991001000010010000010020000312027009100010160803655617217019310111716101260160021938125627619101002000010100220110220158220134220108220124
302042201331648000000027440010022012827620205825506542788423124101002000083354431052295815054921704502201352201052155116216321301002164244710203200052020640009220139882111020110099100100001001000001002000031232719410000016802368061646211830011171610242016002194251512796801002000010100220128220128220152220120220120

1000 unrolls and 10 iterations

Result (median cycles for code): 22.0257

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)9192inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
300262200651649000000003163110012202184151420117925528523281720058100102000010651264105247750129049217155022025722023921533632164973001014212910020200002002040000220299658111002110906301810100001010000110200000310315601000100215884156521477131310006401523321622219376432867992000010010220212220307220265220208220267
3002422023716500000010031548100122023201313201459255284832775200731001020000106159641052417401401492172090220289220243215312321652630010130119100202000020020400002202496581110021109054137101000010100000102000003128314171000100214264145821474029000064015102216222193447327541002000010010220262220252220264220198220226
3002422029116500000000031528010122022221502010732552915328582006910010200001068166610525522113114921717302202772202432154103216529300101521681002020115200204000022025365811100211090609351010000101000001020000002831556100011021484414782152410310006401527521622219317232811992000010010220241220234220251220255220214
3002422020616491011000031805140002202480181820097125529393292720073100102000010717955105241471131549217119022020122021921531432164443001011611710020200002002040000220205658111002110907747210100001010000010200242527273164210044100216684157421595127000064015297216222193582327621002000010010222894220994220242220290220278
300242202971650000010003149310002202660011201447255274732710200771001020000106219601052484301419492171910220249220245215362321644730010141169100202000020020400002202507221110021109055972101000010100000102002627041315381001401215794148821522152733252064015269216222193963328031062000010010220240220232220264220240220250
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