Firestorm: LDRSH (pre-index, 64-bit) measurements

Code:

  ldrsh x0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1056	8	0	0	63	21	1	0	4	12	1041	0	1	29	4	17	25	2000	1000	1000	1000	1000	52820	45824	1	1059	1040	699	3	792	2000	1000	1000	1000	1000	1059	44	1	1	1001	1000	1000	1020	0	3	82	1030	6	1	16	24	0	33	1058	64	8	24	64	0	73	1	16	1	1	1038	1000	40	36	12	1000	1000	1060	1060	1060	1060	1060
2004	1059	8	1	0	84	34	1	0	0	0	1039	19	1	12	5	14	25	2000	1000	1000	1000	1000	52836	45823	0	1059	1059	699	3	792	2000	1000	1000	1000	1000	1059	44	1	1	1001	1000	1000	1038	0	0	60	1046	4	4	12	0	0	13	1052	49	8	21	64	0	73	1	16	1	1	1038	1000	45	53	12	1000	1000	1060	1060	1060	1060	1060
2004	1059	8	0	0	64	18	0	0	0	12	1044	0	0	7	3	20	25	2000	1000	1000	1000	1000	52832	45824	1	1059	1059	699	3	792	2000	1000	1000	1000	1000	1059	44	1	1	1001	1000	1000	1000	0	0	64	1032	12	0	0	0	0	19	1044	55	9	7	56	0	73	1	16	1	1	1035	1000	38	45	12	1000	1000	1060	1060	1041	1060	1060
2004	1059	8	0	0	73	20	1	0	0	0	1044	11	2	12	3	27	25	2000	1000	1000	1000	1000	52812	45816	1	1059	1059	699	3	792	2000	1000	1000	1000	1000	1059	44	1	1	1001	1000	1000	1024	0	0	61	1018	6	0	28	0	6	12	1045	43	6	19	72	0	73	1	16	1	1	1038	1000	34	45	12	1000	1000	1060	1060	1060	1057	1060
2004	1059	7	0	0	83	28	0	0	0	0	1044	17	0	17	6	14	25	2000	1000	1000	1000	1000	52828	46921	1	1059	1059	699	3	792	2000	1000	1000	1000	1000	1056	44	1	1	1001	1000	1000	1038	0	1	76	1034	1	0	22	0	12	17	1042	61	5	15	32	0	73	1	16	1	1	1038	1000	40	38	12	1000	1000	1060	1060	1057	1060	1060
2004	1059	8	0	0	40	12	0	0	0	0	1044	11	0	10	0	13	25	2000	1000	1000	1000	1000	52836	45824	1	1059	1059	699	3	792	2000	1000	1000	1000	1000	1059	44	1	1	1001	1000	1000	1026	0	0	85	1040	6	0	20	0	12	13	1044	43	9	15	56	0	73	1	16	1	1	1038	1000	37	33	12	1000	1000	1060	1057	1059	1060	1060
2004	1059	8	0	0	59	16	1	0	0	0	1025	19	2	27	3	17	25	2000	1000	1000	1000	1000	52848	45828	1	1059	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1012	6	1	39	1039	3	0	16	0	12	14	1046	54	4	23	63	0	73	1	16	1	1	1038	1000	40	42	12	1000	1000	1057	1060	1060	1060	1060
2004	1059	8	0	0	64	22	1	0	0	12	1044	0	0	25	6	21	25	2000	1000	1000	1000	1000	52816	45824	1	1059	1059	699	3	792	2000	1000	1000	1000	1000	1059	44	1	1	1001	1000	1000	1016	0	0	72	1029	9	0	15	32	0	19	1016	50	10	9	47	0	73	1	16	1	1	1038	1000	54	42	12	1000	1000	1060	1060	1060	1060	1060
2004	1059	8	0	0	44	20	1	0	1	0	1039	13	0	28	9	21	25	2000	1000	1000	1000	1000	52828	45824	1	1059	1059	699	3	792	2000	1000	1000	1000	1000	1059	44	1	1	1001	1000	1000	1034	0	0	51	1035	1	0	20	0	12	26	1031	43	7	24	96	0	73	1	16	1	1	1035	1000	43	41	12	1000	1000	1060	1060	1060	1060	1060
2004	1059	8	0	1	56	20	1	0	0	0	1044	11	0	6	3	25	25	2000	1000	1000	1000	1000	52812	45824	0	1059	1059	699	3	792	2000	1000	1000	1000	1000	1059	44	1	1	1001	1000	1000	1020	0	0	88	1011	0	0	26	0	0	15	1055	51	9	32	72	0	73	1	16	1	1	1038	1000	34	36	12	1000	1000	1060	1060	1060	1060	1060

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1844

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	71992	538	0	0	0	0	0	517	0	870	1	728	0	100	72040	841	1	1	71423	25	50788	40668	10135	40100	10000	677489	2713132	0	49	68832	71601	71851	65310	3	65653	50100	40200	10000	70200	10000	71771	35	1	1	40201	100	99	100	10000	30100	10000	1	100	11015	149	518	10663	267	7	951	50	29	10942	138	2	123	0	7	0	2610	2	51	1	1	71800	40564	920	1090	1119	10000	40100	71783	71853	71672	71822	71907
50204	71963	539	0	0	0	0	0	539	0	833	1	760	0	136	71785	802	1	1	71509	25	50780	40636	10144	40100	10000	678095	2723411	0	49	68633	71837	71919	65279	3	65544	50100	40200	10000	70200	10000	71944	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10925	156	511	10646	295	8	948	70	22	10926	140	2	135	3	9	0	2610	1	57	1	1	71564	40524	896	988	1019	10000	40100	71823	72058	71943	71746	71793
50204	71811	538	0	0	0	0	0	526	0	861	1	768	0	140	71818	814	1	1	71493	25	50755	40681	10144	40100	10000	680777	2721265	0	49	68943	71846	71907	65161	3	65323	50100	40200	10000	70200	10000	71852	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10929	161	491	10657	269	14	904	38	31	10912	144	2	133	0	3	0	2610	1	51	1	1	71730	40524	938	830	907	10000	40100	71737	71834	71754	71729	71850
50204	71825	536	0	0	0	0	0	507	0	825	1	744	2	132	71666	812	1	1	71650	25	50818	40624	10121	40100	10000	677790	2712991	0	49	68722	71740	71668	65280	3	65493	50100	40200	10000	70200	10000	71934	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10900	145	520	10656	283	11	926	44	37	10919	134	1	129	3	7	0	2610	1	50	1	1	71680	40571	994	1010	957	10000	40100	71824	71734	71685	71783	71786
50204	71791	549	0	0	0	0	0	553	0	816	1	704	0	100	71694	832	2	1	71449	25	50755	40630	10144	40100	10000	695355	2715065	0	49	68614	71969	71838	65116	3	65444	50100	40200	10000	70200	10000	71855	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10954	138	509	10664	272	10	931	80	32	10975	128	1	125	3	7	0	2610	1	51	1	1	71633	40528	932	1076	1103	10000	40100	71799	71873	71886	71907	71896
50204	71867	564	0	0	0	1	0	495	0	848	1	712	0	116	71963	814	1	1	71625	25	50785	40616	10142	40100	10000	678566	2724631	0	49	68788	71920	71843	65251	3	65438	50100	40200	10000	70544	10000	72044	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10900	147	490	10677	279	6	920	50	22	10973	135	1	144	0	9	0	2610	1	51	1	1	71707	40544	892	912	909	10000	40100	71945	71783	71851	71773	71835
50204	71860	538	0	0	0	0	0	518	0	854	1	720	0	100	71823	824	2	1	71515	25	50790	40648	10125	40100	10000	676550	2716751	0	49	68756	71823	71901	65228	3	65532	50100	40200	10000	70200	10000	71955	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10904	143	466	10682	286	13	918	34	28	10992	133	1	131	0	7	0	2610	1	51	1	1	71797	40520	992	984	905	10000	40100	71907	71995	71729	71709	71745
50204	71787	538	0	0	0	0	0	530	0	836	1	720	1	144	71838	810	1	1	71608	25	50790	40660	10132	40100	10000	677665	2718663	1	49	68631	71737	71741	65207	3	65235	50100	40200	10000	70200	10000	71872	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10895	153	505	10654	279	9	912	50	32	10947	145	1	127	0	7	0	2610	1	51	1	1	71758	40548	828	914	889	10000	40100	71799	71675	71778	71762	71714
50204	71799	538	0	0	0	0	0	536	0	814	1	744	0	104	71841	817	1	1	71742	25	50735	40600	10147	40100	10000	678641	2723282	0	49	68712	71785	71695	65144	3	65624	50100	40200	10000	70200	10000	71857	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10900	168	490	10649	275	9	916	46	28	10949	129	1	141	3	8	0	2610	1	51	1	1	71541	40504	1000	930	983	10000	40100	71937	71755	71707	71865	71896
50204	71899	539	0	0	0	0	0	554	0	832	1	712	0	108	71841	809	2	1	71554	25	50735	40673	10122	41130	10205	624881	2733596	0	49	68709	71916	71746	65410	3	65450	50100	40200	10000	70200	10042	71757	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10965	139	497	10651	269	9	927	54	29	10943	139	1	132	0	7	0	2610	1	51	1	1	71652	40512	940	864	987	10000	40100	71846	71937	71924	71873	71825

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1933

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	19	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72200	540	3	1	0	1	0	1	0	0	435	815	1	688	5	128	72084	810	6	0	71795	25	50730	40566	10143	40010	10000	614230	2729994	1	49	68842	0	71854	72012	65625	0	3	65689	50010	40020	10000	70020	10000	71841	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10917	4	159	498	10651	268	11	919	72	27	10940	123	4	118	3	1	9	2523	17	71	17	19	71774	40544	1128	1131	1187	10000	40010	71924	71743	72049	72072	71915
50024	71752	539	3	1	0	1	0	0	0	0	466	845	1	736	6	112	71957	813	2	3	71794	25	50650	40566	10146	40010	10000	612981	2732628	1	49	68898	0	71933	71893	65402	0	3	65449	50010	40020	10000	70020	10000	71958	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10888	3	154	497	10641	234	8	921	46	25	10931	135	9	126	3	1	9	2523	12	85	15	12	71769	40524	1113	1130	1039	10000	40010	71893	72020	71895	71967	71852
50024	71934	538	3	1	0	1	0	0	0	0	410	808	1	728	4	140	71882	861	5	3	71915	25	50745	40578	10149	40010	10000	614115	2727547	0	49	68709	0	71879	71925	65479	0	3	65694	50010	40020	10000	70020	10000	72025	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10884	3	150	511	10658	276	10	923	96	28	10963	125	8	130	3	3	4	2525	15	71	14	16	71868	40580	940	1089	1080	10000	40010	71988	71848	72054	72078	72011
50024	71989	539	3	1	0	1	0	0	0	0	459	791	1	712	7	124	71814	796	4	3	71694	25	50735	40554	10151	40010	10000	612777	2723249	0	49	68842	0	71883	71917	65408	0	3	65513	50010	40020	10000	70020	10000	71859	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10905	3	141	503	10642	271	11	899	38	31	10903	126	8	119	3	1	4	2523	14	71	13	16	71612	40464	1040	1057	1105	10000	40010	71874	71774	71975	71972	71843
50024	71880	538	3	1	0	1	1	0	0	0	435	828	1	720	4	132	72081	806	6	0	71573	25	50680	40506	10135	40010	10000	614160	2728715	0	49	68760	0	71831	71867	65440	0	3	65665	50010	40020	10000	70020	10000	71925	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10924	5	151	518	10638	264	11	897	52	25	10935	119	9	136	4	3	6	2523	14	71	14	15	71621	40560	1065	1076	1064	10000	40010	71836	71896	71808	71902	71817
50024	71753	539	4	1	0	1	0	0	0	0	472	852	1	720	6	120	71935	774	2	0	71771	25	50710	40514	10146	40010	10000	615135	2732508	0	49	68790	0	71884	71737	65500	0	3	65469	50010	40020	10000	70020	10000	71869	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10937	4	158	530	10643	268	11	898	54	23	10939	127	6	123	4	3	4	2523	15	71	16	16	71884	40572	1248	985	1052	10000	40010	71794	72065	72027	72011	71962
50024	72024	538	4	1	0	1	0	0	0	0	432	805	1	696	5	144	71927	816	2	3	71799	25	50685	40510	10144	40010	10000	614770	2732056	0	49	68854	0	71966	71805	65339	0	3	65708	50010	40020	10000	70020	10000	72001	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10912	4	154	497	10658	278	10	903	78	25	10910	124	11	125	4	3	6	2523	12	71	10	16	71620	40508	1004	1238	1115	10000	40010	72078	71942	71869	72020	71940
50024	71914	538	4	1	0	1	2	0	0	0	431	823	1	792	5	108	71869	785	5	3	71789	25	50695	40534	10142	40010	10000	613618	2724621	1	49	68979	0	71959	71971	65350	0	3	65438	50010	40020	10000	70020	10000	71951	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10904	5	159	513	10645	274	57	900	74	30	10935	135	5	125	4	0	5	2523	17	71	11	14	71686	40592	1091	1067	1064	10000	40010	71950	71935	71999	71810	71877
50024	72017	538	4	1	0	1	0	0	0	0	492	878	1	704	6	108	72030	797	1	3	71633	25	50715	40562	10129	40010	10000	614591	2720962	1	49	68701	0	72031	71722	65507	0	3	65621	50010	40020	10000	70020	10000	71971	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10899	4	157	512	10651	279	14	915	50	39	10944	140	5	124	3	0	9	2523	15	71	13	16	71651	40544	1044	1095	1093	10000	40010	71976	71983	72004	71864	71949
50024	71844	539	3	1	0	1	0	0	0	0	402	809	1	688	4	112	71788	800	5	3	71708	25	50710	40502	10147	40010	10000	613128	2730462	0	49	68877	0	71840	72027	65539	0	3	65588	50010	40020	10000	70020	10000	72097	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10964	3	161	485	10645	267	18	899	46	35	10922	120	9	126	3	3	6	2523	16	85	14	13	71712	40528	933	1144	1019	10000	40010	71997	72162	71772	71995	71981

Test 3: throughput

Count: 8

Code:

  ldrsh x0, [x6, #8]!
  ldrsh x0, [x7, #8]!
  ldrsh x0, [x8, #8]!
  ldrsh x0, [x9, #8]!
  ldrsh x0, [x10, #8]!
  ldrsh x0, [x11, #8]!
  ldrsh x0, [x12, #8]!
  ldrsh x0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3671

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29909	221	1	0	1	0	0	6199	809	1	704	104	136	29301	789	327	1715	1639	2197	25	160157	80165	80000	80100	80000	400736	1308508	0	61	49	26365	29611	29248	9233	3	9489	160100	80200	80000	80200	80000	29305	35	1	1	80201	100	99	39	100	80000	100	80000	100	80867	19	384	5487	0	85372	591	13	875	48	4706	85965	832	122	4810	5421	36	0	0	5110	1	17	1	1	29281	31	80055	577	615	91	80000	80100	29395	29501	29539	29633	29242
160204	29323	221	2	2	0	0	0	6928	819	1	696	112	112	29458	802	414	1894	1741	2235	25	160170	80163	80000	80100	80000	400794	1300131	0	62	49	26095	29398	29280	9239	3	9229	160100	80200	80000	80200	80000	29394	35	1	1	80201	100	99	37	100	80000	100	80000	100	80915	37	393	5453	0	85471	620	12	908	76	5043	86037	792	133	5080	5160	37	15	8	5110	1	17	1	1	29190	35	80059	577	583	101	80000	80100	29582	29533	29385	29423	29226
160204	29520	220	2	2	0	0	0	7307	789	1	688	115	132	29359	787	434	1703	1796	2116	25	160162	80156	80000	80100	80000	400734	1306235	0	67	49	26291	29156	29420	9364	3	9440	160100	80200	80000	80200	80000	29343	35	1	1	80201	100	99	40	100	80000	100	80000	100	80912	36	381	5437	0	85170	648	6	886	72	5151	86081	784	132	4380	5302	37	5	6	5110	1	17	1	1	29196	41	80052	555	571	104	80000	80100	29411	29538	29520	29382	29365
160204	29372	220	2	1	0	0	0	6634	803	1	712	110	108	29498	805	388	1759	1887	2146	25	160156	80153	80000	80100	80000	400807	1322923	1	53	49	26327	29465	29506	9165	3	9078	160100	80200	80000	80200	80000	29292	35	1	1	80201	100	99	61	100	80000	100	80000	100	80939	40	394	5316	0	84985	617	9	896	48	5279	85569	738	133	5206	5205	37	7	3	5110	1	16	1	1	29409	36	80058	594	594	100	80000	80100	29352	29503	29253	29374	29409
160204	29382	220	2	0	2	0	0	7288	799	1	672	128	128	29208	778	339	1637	1710	2031	25	160144	80155	80000	80100	80000	400795	1296576	0	57	49	26210	29379	29309	9297	3	9541	160100	80200	80000	80200	80000	29423	35	1	1	80201	100	99	55	100	80000	100	80000	100	80954	38	375	5795	0	85555	666	10	884	72	5203	86080	764	129	4970	5288	37	0	3	5110	1	16	1	1	29397	35	80053	538	535	108	80000	80100	29332	29504	29494	29511	29244
160204	29426	219	2	2	0	0	0	6932	807	1	680	140	132	29389	778	334	1636	1877	2046	25	160154	80154	80000	80100	80000	400765	1316709	0	48	49	26385	29450	29268	9270	3	9428	160100	80200	80000	80200	80000	29420	35	1	1	80201	100	99	33	100	80000	100	80000	100	80941	38	357	5438	0	85350	677	11	902	66	5159	85733	766	131	5050	5270	36	0	3	5110	1	16	1	1	29255	31	80066	632	570	107	80000	80100	29425	29234	29371	29290	29485
160204	29324	220	2	0	2	0	0	6361	782	1	696	121	136	29680	763	306	1594	1814	2170	25	160157	80164	80000	80100	80000	400772	1304822	1	49	49	26365	29384	29401	9452	3	9312	160100	80200	80000	80200	80000	29491	35	1	1	80201	100	99	52	100	80000	100	80000	100	80953	37	392	5422	0	85207	639	10	911	78	5493	85531	759	132	4927	4931	33	3	3	5110	1	16	1	1	29487	28	80060	578	587	101	80000	80100	29376	29598	29535	29300	29526
160204	29311	220	2	0	0	0	0	6386	775	1	680	119	112	29381	810	424	1760	1625	2256	25	160159	80168	80000	80100	80000	400782	1301916	0	75	49	26388	29199	29289	9238	3	9118	160100	80200	80000	80200	80000	29486	35	1	1	80201	100	99	57	100	80000	100	80000	100	80889	37	445	5439	0	85111	681	10	910	82	4906	86316	734	139	5109	5962	34	0	3	5110	1	16	1	1	29323	31	80069	588	514	84	80000	80100	29646	29588	29409	29543	29357
160204	29261	220	2	0	2	0	0	7230	778	1	696	137	124	29330	770	348	1680	1749	1994	25	160176	80158	80000	80100	80000	400744	1302209	0	57	49	26385	29309	29377	9412	3	9338	160100	80200	80000	80200	80000	29273	35	1	1	80201	100	99	57	100	80000	100	80000	100	80939	37	375	5609	0	85694	594	9	877	48	4364	85710	752	140	4993	4351	37	3	3	5110	1	16	1	1	29480	43	80055	564	614	103	80000	80100	29350	29410	29543	29496	29158
160204	29531	220	2	0	0	0	0	6796	790	1	672	109	172	29338	781	373	2174	1700	2076	25	160160	80155	80000	80100	80000	400720	1286264	0	60	49	26378	29393	29338	9374	3	9650	160100	80200	80000	80200	80000	29595	35	1	1	80201	100	99	56	100	80000	100	80000	100	80950	36	419	5434	0	84848	576	10	924	48	4765	85684	805	141	4543	5077	37	0	3	5110	1	16	1	1	29469	37	80056	592	563	104	80000	80100	29037	29448	29227	29385	29508

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3666

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29901	219	1	0	0	7180	804	1	632	102	104	29330	766	346	1933	1871	2080	25	160091	80060	80000	80010	80000	400321	1296618	1	1	66	49	26358	29372	29406	9001	0	3	9383	160010	80020	80000	80020	80000	29490	35	1	1	80021	10	9	30	10	80000	10	80000	0	10	80928	27	376	5572	85174	679	13	908	32	4941	85811	850	119	4928	4972	13	1	4	0	5020	0	0	7	16	0	0	4	2	29427	23	80068	550	600	124	80000	80010	29284	29487	29298	29344	29392
160024	29092	219	1	0	1	6985	827	1	744	104	140	29268	802	317	2003	1777	1882	25	160085	80074	80000	80010	80000	400291	1288936	0	0	52	49	26338	29325	29366	9273	0	3	9235	160010	80020	80000	80020	80000	29166	35	1	1	80021	10	9	28	10	80000	10	80000	0	10	80877	8	459	5928	85443	598	11	830	62	5245	85976	800	127	4933	5025	38	0	3	0	5020	0	0	3	16	0	0	2	4	29443	18	80058	576	515	123	80000	80010	29176	29068	29558	29469	29364
160024	29281	220	2	0	0	6527	824	1	664	108	104	29442	802	340	2213	2018	2101	25	160079	80076	80000	80010	80000	400307	1303360	0	0	54	49	26268	29387	29669	9207	0	3	9193	160010	80020	80000	80020	80000	29291	35	1	1	80021	10	9	27	10	80000	10	80000	0	10	80912	35	327	5512	85264	707	11	935	38	5131	85729	740	127	5455	5766	18	0	0	0	5020	0	0	4	16	0	0	4	2	29262	25	80063	535	525	113	80000	80010	29216	29421	29327	29323	29338
160024	29349	221	1	0	2	6844	823	1	672	92	152	29392	790	329	2008	1969	2012	25	160070	80079	80000	80010	80000	400320	1302269	0	0	69	49	26412	29066	29509	9355	0	3	9485	160010	80020	80000	80020	80000	29293	35	1	1	80021	10	9	20	10	80000	10	80000	0	10	80899	20	370	5080	85194	626	7	857	30	5083	85948	660	112	4437	5470	18	6	3	0	5020	0	0	2	16	0	0	2	4	29455	18	80051	550	495	94	80000	80010	29351	29427	29330	29166	29253
160024	29221	220	1	0	1	6840	767	1	728	109	148	29235	760	341	1740	1885	2141	25	160075	80080	80000	80010	80000	400357	1294541	0	1	57	49	26114	29298	29458	9531	0	3	9402	160010	80020	80000	80020	80000	29552	35	1	1	80021	10	9	30	10	80000	10	80000	0	10	80880	0	386	6252	85286	651	13	874	46	5115	85570	751	129	4968	5317	0	0	2	0	5020	0	0	2	16	0	0	4	2	29399	42	80078	597	521	95	80000	80010	29280	29146	29289	29210	29392
160024	29262	218	1	0	0	6936	843	1	680	101	96	29296	808	310	1540	1667	1943	25	160065	80065	80000	80010	80000	400343	1289494	0	0	70	49	26033	29241	29242	9314	0	3	9302	160010	80020	80000	80020	80000	29269	35	1	1	80021	10	9	24	10	80000	10	80000	0	10	80929	40	415	5786	85203	647	12	906	42	4781	86112	817	134	5052	4982	19	0	3	0	5020	0	0	2	16	0	0	6	6	29387	19	80075	498	561	89	80000	80010	29317	29539	29485	29373	29348
160024	29496	220	1	0	0	6816	801	1	760	96	128	29391	758	352	1739	1952	1877	25	160077	80078	80000	80010	80000	400342	1295965	0	0	61	49	26253	29339	29290	9308	0	3	9417	160010	80020	80000	80020	80000	29285	35	1	1	80021	10	9	23	10	80000	10	80000	0	10	80905	17	406	5142	85210	661	14	896	32	5692	85908	706	138	5046	5265	37	1	8	0	5020	0	1	6	16	0	0	3	6	29234	23	80064	532	514	108	80000	80010	29238	29397	29252	29362	29321
160024	29345	219	2	0	1	6364	784	1	688	100	156	29028	791	316	1572	1853	1912	25	160078	80070	80000	80010	80000	400347	1292156	0	1	64	49	26465	29450	29500	9246	0	3	9525	160010	80020	80000	80020	80000	29421	35	1	1	80021	10	9	21	10	80000	10	80000	0	10	80913	37	333	5984	85280	646	13	919	68	5390	86099	738	137	5272	5059	16	0	0	0	5020	0	0	4	16	0	0	4	4	29322	16	80250	511	583	106	80000	80010	29399	29381	29309	29235	29216
160024	29186	219	1	1	0	7008	819	1	728	92	140	29215	806	352	1643	1824	2033	25	160073	80078	80000	80010	80000	400341	1288860	0	0	60	49	26075	29304	29269	9041	0	3	9287	160010	80020	80000	80020	80000	29359	35	1	1	80021	10	9	19	10	80000	10	80000	0	10	80904	17	421	5938	85116	660	14	891	114	5379	85940	741	127	5096	4881	36	4	5	0	5020	0	0	6	16	0	0	2	4	29290	20	80060	534	475	86	80000	80010	29463	29400	29353	29203	29390
160024	29387	221	4	0	0	6613	839	1	704	111	232	29377	797	334	1920	2175	1989	25	160079	80053	80000	80010	80000	400344	1290087	0	0	75	49	26307	29173	29229	9229	0	3	9304	160010	80020	80000	80020	80000	29271	35	1	1	80021	10	9	18	10	80000	10	80000	1	10	80894	18	368	5367	85977	656	14	900	48	4879	86030	702	143	4929	5131	18	0	3	0	5020	0	0	3	16	0	0	6	5	29485	15	80068	559	525	118	80000	80010	29367	29355	29392	29388	29334

LDRSH (pre-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations