Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STADD (32-bit)

Test 1: uops

Code:

  stadd w0, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 70 nops): 3.000

Issues: 3.003

Integer unit issues: 1.003

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)0e0f181e22243a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)9dl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafbbl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)cfd0d1d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
73005332762522832100100010586432919002094030031003200010002000109071681114929775331233308331430001000200020004000329992598117100110001000120000010021000002002320159021153708123384314862321138134444116864326591002171571488315982200010003300233110331043325733093
73004330412492628100100000582633142012107630031003200010002000109851687024929906329183308831330001000200020004000328982586117100110001000020002010021000022003220155371186708166379013602342138724435136562326451003176981542916228200010003299033305330013302333328
73004329592483133010100000588132850002100530041003200010002000109661688444930250327333328431430001000200020004000332782594117100110001000020002210011000022002120162751183908256404313622308937534432145767326341002169741485216474200010003321333157328683330333438
73004329382472724110100410597332877002095530031002200010002000109491687374929877327043324631430001000200020004000330622589117100110001000020000210021000122002222159391190908230382413572312036284433196462325781003171601471715615200010003302532840331353326432932
73004330842483026110100010570432939002093830031000200010002000109471686384929980329613303131430001000200020004000330732580117100110001000020002210021000002002222158901153808294388017652305738444434166463325201003172531470515727200010003296132969328893328232976
73004328992462827000100000588933185012090830031002200010002000109011686984930218330673325531430001000200020004000329482586117100110001000020002210021000022002120159201183208281381716622309038364442146366324211004170341494415603200010003304233038329583334233156
73004330402472827000100310597133158002092930021003200010002000109041686804929942327913296931430001000200020004000330412598117100110001000020002210031000062000022158721165318358383011572288938914442115959325581004171421491315562200010003323332906329923296233158
73004332322473228100100410589233001102096130001000200010002000109671686964929855327563289831430001000200020004000329262589117100110001000020002210001000022002222159351174508283367713662303038454440116565326091003170161480116201200010003325633278331313290933103
73004331582502524000100500593233065002122030031002200010002000109621687244929878327133288831030001000200020004000329902580117100110001000020002210021000002002222154331178208241384515702319137014441166967325561003172391491715907200010003314833003330483304033060
7300433261249262600010080057103299700209923003100320001000200010938168676493014333010332963103000100020002000400033186257311710011000100002000001002100002200220215799116330821339079612320538134434176367326541000167151564215471200010003329833082329533308833003

Test 2: throughput

Code:

  stadd w0, [x6]
  add x6, x6, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0071

retire uop (01)cycle (02)030e0f1e1f2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
4020730075225103754119511766311630060193446980129392540643206562000020100200009139971412749129749269913006830069248203250334010020200200003020040000300796411202011009910010000101001000001002018165527010329100551901918224820318314721874071310117113006820561101020000201003007630072300763007230076
40204300752251137231233186210430054198477170129492540656207302000020100200009139251412786129049269913007630085248223250334010020200200003020040000300756411202011009910010000101001000001002019848927910259100552401915620920293813322295031310116113006820594101020000201003007230076300763008030072
40204300752261037061189184717630056176366961129422540553206942000020100200009139661412751128749269953007630075248203250324010020200200003020040000300756411202011009910010000101001000001002018764030310344100332431685426220363614912284871310116113007220562101020000201003007230076300723007630076
4020430075225003771221611046620030056205595881129992540678206552000020100200009134971412783129849269913006830069248143250294010020200200003020040000300716811202011009910010000101001000001002019746228210349100762201988224020370415612025601310116113006820581101020000201003007230072300723007230072
4020430071225003726221010647230056161536176129782540573206592000020100200009135341412728126649269913007130071248163250334010020200200003020040000300756411202011009910010000101001000001002019150929710331100702411864821520317813921814381310116113006820516101020000201003007230076300763007630072
4020430071225003731221210635630060220546355129812540668207062000020100200009141091412736126149269913006830071248173250334010020200200003020040000300696911202011009910010000101001000001002022844926310343100562701912219720369812422575631310117113006820611101020000201003007630076300723007230072
402043007122500367522141885312030056178418663130362540614207182000020100200009135971412799125549269913007230075248223250294010020200200003020040000300756811202011009910010000101001000001002017961426910313100531901797022420305513822324541310116113006820541101020000201003007230070300763007630072
4020430075225003767118110483630060163445975129642540662206562000020100200009133001412876128149269913007130069248123250294010020200200003020040000300716811202011009910010000101001000001002022455532510308100362201554222720399712822194701310117113007220629101020000201003006730072300703007230072
40204300712250037461185185010030056189447262129422540673207192000020100200009137491412689027349269963007530075248153250294010020200200003020040000300716811202011009910010000101001000001002015756734710299100412202104222820292717011975181310116113007220535101020000201003007230072300723007030076
40204300752250037861235196577630064188397481129922540688207312000020100200009138331413018028649269913006830071248133250284010020200200003020040000300716811202011009910010000101001000001002029358629810297100712702126826120338915212325521310116113006820585101020000201003007630076300763007630076

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0080

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f202223293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)7bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
4002730075226220200037838223108632203007019476870129982540538205582000020010200009131641413282126549270113008530085248540325057400100200202000030020400003008565112002110901010000100101000001020214164572700103361005913319732156203106124101933991741270316333007720454131320000200103008130081300763008630081
40024300802252222000369511220100474030065205262551298025405742052120000200102000091339514131521269492700030082300852485003250614001002002020000300204000030080651120021109691010000100101000011020243164662610102951008116124352190203263138101844511621270316343007720492131320000200103008130086300863008130086
400243008022522220003622111941006017630070205167461130122540490205212000020010200009132501413109026149270053008230085248520325060400100200202000030020400003007565112002110901010000100101000001020269166042490102641004814318852189203226138112265941601270317343007720572131320000200103008630086300813008130076
400243007522620220003721111931006052300652187988112987254062820515200002001020000913316141344702674927000300823008024841032506540010020020200003002040000300807011200211090101000010010100000102018917657216010309100331331682215120239495121594831721270316333008220467131320000200103008130081300813008130081
4002430080225200000036291118510052164300601789796013021254050720542200002001020000913204141320802774927000300803008024846032506040010020020200003002040000300856511200211090101000010010100000102020717560332010255100531131878615120292313292437361621270316333007720506131320000200103008130086300763008130076
400243008022611120003761721910064156300701921068711292825404662049620000200102000091308014131980239492700030077300802484603250604001002002020000300204000030075651120021109010100001001010000010202601465528701030910062171202241852034368982675441311270316333007720462131320000200103007630086300813008130086
40024300752251110000370682151007612030070229958621294825406082052320000200102000091324714131610269492700030077300802485103250664001012002020000300204000030085641120021109010100001001010000010202061455827901028210044142181341622024967982305921411270316333007720536131320000200103008130081300813007630081
4002430080226110200036347182100691723006520013794712956254067120489200002001020000913209141324702784927005300803008524840032506040010020020200003002040000300807011200211090101000010010100000102023515588267010303100523212908818620409512971615281401270316333007720498131320000200103008130086300863008130086
400243008022511100003625823810055216300651948646812971254055720510200002001020000913202141318702524927005300723007524855032506040010020020200003002040000300806511200211090101000010010100000102027214638289010259100451622882814820339610681595321401270316333007720455131320000200103008130081300763008630081
4002430080225111000036651021810144600300651566425113003254045620476200002001020000912597141316502814927000300773008024847032506140010020020200003002040000300757011200211090101000010010100000102020315452268010250100411611712224020381610572026281301270316333007220553131320000200103008630081300813008130081

Test 3: throughput

Code:

  stadd w0, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.2887

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f181e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)67696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
30205111092833000110199991100104081189893022542542216222048010100200004510238492420017349999101021671041639977679946330100154110251020320005202064000910395636251102011009910010000100100000100200000322419525100010093212919091461263400111716190160093338181780701002000010100100535100458100086100994103886
3020410335777400000022873000110395329084327254051819096206821010020000459755949914922004910253210378510425210119969912230100134710991020020000202004079810500553511102011009910010000100100000100200000330186681000000970130719101461303400111722022522102176519810141402000010100101463100443101070100901101637
302041040347730000101810411029992138084700254078220938203141030720000445523448605822254910227610341710246898735810024230100768778102032000520206400091044363951110201100991001000010010000010020000034271800810000001008029914975500340011171627016001022321122909141002000010100101154103331103932103191101993
3020410144776500000020030010010242028683599253946819179208551010020000406873646806371354997675104779103397988916930843010016681370102032000520206400099870052911102011009910010000100100000100200000332418197100000011171294559567027330011171700160096212191962514100200001010010444610337210334510226899063
3020497955722000100194481101105401010884812254063121065203621010020000478641749893246549100915100063100830974806982073010014789781020320005202064000910419856511102011009910010000100100000100200000033205351000000104622921010390031340011171731016001013221018904141402000010100103686103449103431103025104128
302041035127720000001878000011056830678296625396831993921135101002000040264634748756140499667310151310034397691698302301001019894102032000520206400091023685101110201100991001000010010000010020000032018248100010070862774196770200001117170016009835812019401002000010100103541103126103046103164102478
30204104254778000010195581000103784280852172541175224792007410100200004639854481603937049993321039111032509978461007643010011461041102032000520206400091005044321110201100991001000010010000010020000035322000910000009423287879652003100111716001600100575111964301002000010100105361105963106440105244104953
302041038967750000001933711001037430110879952546598245962053610100200004280149475550573491002321032471035269970216970393010012631131102032000520206400091042003981110201100991001000010010000010020000034019057100010010319303201071612834001117160016001050741719999141412000010100102309102308101756102258104757
30204100559775000000192641001995740568349925409231961821241101002000046145244951936103491005231012211017339754279773830100844763102032000520206400091051935991110201100991001000010010000010020000000194851000000110643074883661260001117162511600102855111854401002000010100101626103008102972102119101907
3020498772741000000173890100991953888505725410881974520155101002000044359114927607220499979810404110223198489798087301009897881020320005202064000910553853511102011009910010000100100000100200000343119829100010010875321309489027310011172226225221021081620236141002000010100102857102833102906102754106632

1000 unrolls and 10 iterations

Result (median cycles for code): 11.1666

retire uop (01)cycle (02)03l1d tlb fill (05)0e0f1e1f223a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch mispred nonspec (cb)cfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
3002511162883810020135100111669314149164725420462090020000100102000055090355318301110494910868911179111179710725831080483001021191002020107202304042611186052231100211092715810100001010000010200920272924122100010015340349351387612500006400216221114510240711062000010010111494111665111608111818111559
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