Firestorm: BFI (32-bit) measurements

Code:

  bfi w0, w1, #3, #7

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1036	8	0	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	0	3	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	6	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	3	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	6	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	4	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	7	0	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037

Test 2: Latency 1->1

Code:

  bfi w0, w1, #3, #7

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0036

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10036	75	1	1	81	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	7	8740	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	1	1	1	717	1	16	1	1	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	1	1	3	0	35	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	7	8739	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	1	1	1	717	1	16	1	1	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	1	1	0	0	35	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8739	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	1	1	1	717	1	16	1	1	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	1	1	12	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8740	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	1	1	1	717	1	16	1	1	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	1	1	12	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8739	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	1	1	1	717	1	16	1	1	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	1	1	0	0	35	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8739	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	1	1	1	718	1	16	1	1	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	1	1	0	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	7	8740	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	1	1	1	717	1	16	1	1	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	1	1	15	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	7	8740	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	1	1	1	717	1	16	1	1	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	1	1	9	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	7	8740	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	1	1	1	717	1	16	1	1	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	1	1	9	0	35	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8740	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	1	1	1	717	1	16	1	1	10033	10000	10100	10037	10037	10037	10037	10037

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0036

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	a9	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10037	75	3	47	25	10010	10010	10010	60049	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	9	47	25	10010	10010	10010	60049	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	47	25	10010	10010	10010	60049	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	133	25	10010	10010	10010	60049	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	47	25	10010	10010	10010	60049	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	68	25	10010	10010	10010	60049	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	47	25	10010	10010	10010	60049	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	47	25	10010	10010	10010	60049	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	3	47	25	10010	10010	10010	60049	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	142	25	10010	10010	10010	60049	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  bfi w0, w1, #3, #7

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	20035	150	0	61	9951	25	20100	20100	20106	1288657	1	49	16955	0	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	1	1	1	1919	2	16	1	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20035	150	0	61	9951	25	20100	20100	20106	1288657	1	49	16955	0	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20035	150	48	61	9951	25	20100	20100	20106	1288657	1	49	16955	0	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20035	150	0	61	9951	25	20100	20100	20106	1288657	1	49	16955	0	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20035	150	0	61	9951	25	20100	20100	20106	1288657	1	49	16955	0	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20080	150	0	61	9951	25	20100	20100	20106	1288657	1	49	16955	0	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20035	150	9	61	9951	25	20100	20100	20106	1288657	1	49	16955	0	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20035	150	0	61	9951	25	20100	20100	20106	1288657	0	49	16955	0	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20035	150	126	61	9951	25	20100	20100	20106	1288657	1	49	16955	0	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20035	150	0	61	9951	25	20100	20100	20106	1288657	1	49	16955	0	20035	20035	16160	7	16236	20182	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20036	20036	20036	20081	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	1	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	5	0	0	1890	0	7	16	6	4	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	1	0	0	1890	0	3	16	3	5	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	1	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	4	0	0	1890	0	5	16	5	4	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	441	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1890	0	5	16	5	3	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	1	0	0	1890	0	5	16	5	6	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	2	0	0	1890	0	5	16	5	3	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	1	0	0	1890	0	6	16	7	5	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1890	0	5	16	5	5	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	536	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	54	1890	0	3	16	3	5	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1890	0	6	16	3	5	20003	20000	30010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  bfi w0, w8, #3, #7
  bfi w1, w8, #3, #7
  bfi w2, w8, #3, #7
  bfi w3, w8, #3, #7
  bfi w4, w8, #3, #7
  bfi w5, w8, #3, #7
  bfi w6, w8, #3, #7
  bfi w7, w8, #3, #7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80082	600	0	46	25	80100	80100	80100	400682	49	76955	0	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	63	162	25	80100	80100	80100	400500	49	76955	0	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	521	25	80100	80100	80100	400500	49	76955	0	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	46	25	80100	80100	80100	400500	49	76955	0	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80074	80036	80036
80204	80035	599	0	46	25	80100	80100	80100	400500	49	76955	0	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	46	25	80100	80100	80100	400500	49	76955	0	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	12	46	25	80100	80100	80100	400500	49	76955	0	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	15	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	951	25	80100	80100	80100	400500	49	76955	0	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	46	25	80100	80100	80100	400500	49	76955	0	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	46	25	80100	80100	80100	400500	49	76955	0	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80035	599	0	0	0	0	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	2	16	4	2	80032	80000	80010	80036	80036	80036	80036	80128
80024	80035	600	0	0	0	0	0	0	0	88	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	4	16	9	3	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	0	0	24	0	711	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	4	16	4	2	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	0	0	0	0	711	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70148	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	2	16	2	4	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	0	46	25	80010	80010	80100	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	52	0	0	5020	4	50	2	4	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	0	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	4	0	0	5020	3	16	4	4	80032	80000	80010	80036	80036	80218	80036	80036
80024	80035	599	0	0	0	0	0	0	0	46	25	80010	80095	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	2	16	4	3	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	0	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	2	16	2	4	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	4	4	0	5020	4	16	4	2	80032	80000	80010	80036	80036	80036	80036	80071
80024	80035	599	0	0	0	0	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	30	0	0	5033	3	16	4	2	80032	80000	80010	80036	80036	80036	80036	80036

BFI (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations