Firestorm: LDRH (register) measurements

Code:

  ldrh w0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	399	3	1	0	1	0	1	65	1	0	3	367	0	0	0	15	25	1000	1000	1000	14540	399	398	222	3	257	1000	1000	2000	426	81	1	1	1001	1000	1000	0	1019	20	0	1057	1	0	0	21	1000	6	1	57	0	19	1	73	2	16	2	2	379	9	9	0	1000	400	382	400	399	400
1004	399	3	1	1	1	0	0	65	1	0	3	384	2	18	18	16	25	1000	1000	1000	15291	398	399	221	3	257	1000	1000	2000	399	82	1	1	1001	1000	1000	0	1019	19	42	1057	0	0	1	59	1038	6	1	58	42	19	1	73	2	16	2	2	395	9	9	2	1000	400	400	399	400	400
1004	398	3	1	1	1	0	0	65	1	0	3	384	1	18	18	15	25	1000	1000	1000	15334	398	399	221	3	257	1000	1000	2000	398	81	1	1	1001	1000	1000	0	1020	19	42	1057	1	0	2	59	1038	6	1	57	40	19	1	73	2	16	2	2	396	9	9	2	1000	400	400	403	400	400
1004	399	3	1	1	1	0	0	65	1	0	3	384	2	18	18	16	25	1000	1000	1000	15375	399	398	222	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	0	1019	21	42	1056	1	0	1	59	1038	6	1	57	42	19	2	73	2	16	2	2	396	9	9	2	1000	400	400	400	399	400
1004	399	3	1	1	1	0	0	65	1	0	3	384	2	18	18	15	25	1000	1000	1000	15334	399	399	221	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	0	1019	21	42	1057	1	0	1	59	1037	6	1	57	42	19	1	73	2	16	2	2	395	9	9	2	1000	399	400	400	400	400
1004	399	3	1	1	1	0	0	64	1	0	3	383	2	18	18	16	25	1000	1000	1000	15362	399	399	222	3	256	1000	1000	2000	400	81	1	1	1001	1000	1000	0	1020	20	42	1056	1	0	1	59	1038	6	1	57	42	19	1	73	2	16	2	2	396	9	9	2	1000	400	400	400	399	400
1004	399	3	1	1	1	0	0	65	1	0	3	384	2	18	18	15	25	1000	1000	1000	15282	399	399	221	3	257	1000	1000	2000	398	81	1	1	1001	1000	1000	0	1020	19	42	1058	1	0	2	59	1038	6	1	57	42	19	2	73	2	16	2	2	396	9	9	2	1000	402	400	400	399	400
1004	399	3	1	1	1	0	0	65	1	0	3	383	2	18	18	15	25	1000	1000	1000	15375	399	399	221	3	256	1000	1000	2000	399	81	1	1	1001	1000	1000	0	1020	20	42	1057	1	0	2	59	1038	6	1	57	42	19	2	73	1	16	2	2	396	9	9	2	1000	400	400	400	399	399
1004	398	3	1	1	1	0	0	65	1	0	3	383	2	18	18	17	25	1000	1000	1000	15300	399	398	222	3	257	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	0	39	1035	0	0	0	35	1035	6	1	35	39	0	0	73	2	16	2	2	388	6	6	2	1000	390	390	390	390	390
1004	391	3	0	0	0	0	0	41	1	0	1	374	2	18	18	12	25	1000	1000	1000	14838	389	389	212	3	247	1000	1000	2000	389	76	1	1	1001	1000	1000	0	1000	0	39	1035	0	0	0	35	1035	6	1	35	39	0	0	73	2	16	2	2	386	6	6	2	1000	390	390	390	390	390

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70128	525	0	0	0	0	1	0	1	0	70039	69782	59713	25	40104	30103	10001	30252	10000	616230	3342494	0	49	66974	70051	70035	64647	3	64955	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	234	10000	1	1	2610	2	71	1	1	69814	30000	10	10	0	10000	30100	70055	70036	70036	70052	70055
40204	70038	525	0	0	0	0	1	0	1	0	70020	69764	59713	25	40100	30103	10001	30100	10000	616050	3342590	1	49	66955	70054	70054	64647	3	64954	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	243	10000	1	1	2610	1	71	1	1	69905	30003	13	10	13	10000	30100	70055	70052	70036	70055	70055
40204	70035	525	0	0	0	0	1	0	0	0	70190	69764	59713	25	40104	30103	10002	30100	10000	616023	3342638	1	49	66971	70051	70035	64647	3	64954	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	3	132	10000	1	1	2610	1	71	1	1	69817	30000	0	10	13	10000	30100	70036	70052	70055	70036	70055
40204	70088	525	0	0	1	0	1	0	1	0	70036	69782	59710	25	40104	30103	10001	30100	10000	625063	3342638	0	49	66974	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	99	10000	1	1	2610	1	71	1	1	69798	30003	13	0	13	10000	30100	70036	70055	70055	70055	70055
40204	70118	525	0	0	0	0	6	0	1	0	70039	69785	59695	25	40104	30103	10001	30100	10000	616023	3342494	1	49	66971	70035	70051	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	258	10000	1	1	2610	1	71	1	1	69817	30000	13	13	10	10000	30100	70036	70055	70036	70052	70036
40204	70079	525	0	0	1	0	1	0	0	0	70039	69764	59695	25	40104	30103	10001	30100	10000	616023	3342398	0	49	66955	70054	70035	64631	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	249	10000	1	1	2610	1	71	1	1	69798	30009	0	13	0	10000	30100	70055	70036	70055	70055	70036
40204	70139	525	0	0	0	0	1	0	0	0	70020	69785	59695	25	40104	30103	10001	30100	10000	616050	3341710	1	49	66955	70054	70035	64631	3	64954	40100	30200	10000	60596	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	225	10000	1	1	2610	1	71	1	1	69817	30003	13	10	0	10000	30100	70052	70052	70055	70052	70052
40204	70166	525	0	0	0	0	2	0	0	0	70020	69785	59714	25	40104	30103	10001	30100	10000	616239	3343342	0	49	66955	70054	70051	64631	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	1	2610	1	71	1	1	69798	30000	13	0	13	10000	30100	70036	70036	70055	70036	70055
40204	70142	525	0	0	0	0	2	0	0	0	70020	69764	59710	25	40104	30103	10000	30100	10000	625372	3342446	1	49	66979	70054	70054	64631	3	64954	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	186	10000	0	1	2610	1	71	1	1	69817	30003	0	0	13	10000	30100	70055	70036	70036	70055	70055
40204	70136	525	0	0	0	0	10	108	0	0	70039	69785	59713	25	40104	30100	10000	30100	10000	616193	3342542	1	49	66971	70054	70054	64650	3	64954	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	1	231	10000	1	1	2610	1	71	1	1	69817	30003	0	13	10	10000	30100	70036	70036	70052	70055	70056

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	19	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	524	0	0	0	14	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342542	0	49	66974	70051	70102	64730	3	64966	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	0	0	0	0	2520	1	71	1	1	69814	30003	10	10	10	10000	30010	70153	70156	70052	70052	70036
40024	70051	525	0	0	0	2	1	0	70036	69775	59710	25	40010	30013	10001	30010	10000	617018	3342254	0	49	66971	70162	70065	64673	3	64976	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	2520	1	71	1	1	69814	30003	13	10	13	10000	30010	70036	70052	70036	70052	70052
40024	70054	525	0	0	0	1	1	0	70020	69775	59710	25	40010	30013	10001	30010	10000	616991	3342254	1	49	66980	70163	70079	64677	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	0	1	0	0	2520	1	71	1	1	69814	30003	13	10	13	10000	30010	70036	70036	70036	70055	70052
40025	70051	525	0	0	0	1	0	0	70039	69743	59713	25	40010	30013	10001	30010	10000	616991	3342254	0	49	66971	70151	70129	64673	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	2520	1	71	1	1	69814	30003	10	10	10	10000	30010	70052	70055	70052	70052	70052
40024	70051	525	0	0	0	1	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	617018	3342398	0	49	66974	70142	70089	64678	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	2520	1	71	1	1	69798	30003	10	10	0	10000	30010	70052	70052	70052	70052	70052
40024	70035	524	0	0	0	0	0	0	70039	69775	59695	25	40014	30013	10001	30010	10000	616991	3341470	0	98	66961	70119	70058	64659	3	64982	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10000	0	1	10000	1	1	1	0	0	2520	1	71	1	1	69821	30003	10	10	10	10000	30010	70052	70036	70052	70054	70148
40024	70051	524	0	0	0	1	1	0	70036	69743	59710	25	40010	30013	10000	30010	10000	616991	3342254	0	49	66974	70142	70085	64679	3	64976	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	1	10000	1	0	1	1	0	2520	1	71	2	1	69822	30006	10	13	0	10000	30010	70055	70052	70055	70052	70052
40024	70035	525	0	0	0	1	1	0	70036	69775	59695	25	40014	30013	10001	30010	10057	617090	3342686	1	49	66955	70167	70108	64678	3	64976	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	2520	1	71	1	1	69819	30003	10	10	0	10000	30010	70052	70052	70052	70052	70052
40024	70051	525	0	1	0	1	1	0	70036	69778	59695	25	40010	30013	10001	30010	10000	616991	3342254	0	49	66971	70103	70062	64674	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	2520	1	71	1	1	69817	30003	13	0	0	10000	30010	70055	70055	70055	70055	70052
40024	70051	524	0	0	0	1	0	0	70036	69775	59710	25	40014	30013	10001	30010	10000	617018	3342398	1	49	66974	70133	70093	64677	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	2520	1	71	1	2	69798	30003	10	10	10	10000	30010	70055	70055	70052	70036	70052

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	0	0	0	1	0	1	0	0	0	70035	69781	59706	25	40104	30103	10002	30100	10000	616059	3342542	0	49	66973	70056	70056	64649	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	2	0	10001	0	0	1	10000	1	1	0	1	0	2610	1	71	1	1	69819	30006	9	6	6	10000	30100	70057	70057	70042	70057	70057
40204	70056	524	1	0	1	0	0	1	0	0	0	70041	69702	59715	25	40108	30106	10002	30100	10000	616059	3341769	0	49	66976	70056	70041	64652	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	1	10002	1	1	1	10000	0	1	1	1	0	2610	1	71	1	1	69819	30003	9	9	9	10000	30100	70057	70042	70057	70057	70057
40204	70053	525	1	0	1	0	0	1	0	0	0	70041	69702	59715	25	40108	30103	10002	30100	10000	616059	3342494	0	49	66973	70056	70041	64652	3	64944	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	0	10002	0	0	1	10000	0	1	0	1	1	2610	1	71	1	1	69804	30006	9	6	9	10000	30100	70054	70042	70057	70057	70057
40204	70056	525	1	0	1	0	0	2	1	0	0	70026	69787	59712	25	40108	30106	10002	30100	10000	616059	3341769	0	49	66976	70056	70056	64649	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	1	10	10000	1	1	1	1	0	2610	1	71	1	1	69819	30003	9	0	6	10000	30100	70057	70042	70054	70057	70057
40204	70041	525	1	1	0	0	0	2	0	0	1	70041	69702	59715	25	40108	30106	10002	30100	10000	616059	3342494	0	49	66973	70056	70041	64652	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	1	1	10002	0	1	1	10000	1	1	1	1	1	2610	1	71	1	1	69804	30003	0	9	9	10000	30100	70042	70042	70057	70057	70057
40204	70041	525	1	1	0	0	0	2	0	0	0	70026	69702	59715	25	40108	30103	10003	30100	10000	616059	3342494	1	49	66976	70056	70056	64652	3	64959	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10001	0	1	1	10000	0	1	1	1	0	2610	1	71	1	1	69816	30006	9	9	9	10000	30100	70057	70057	70057	70057	70057
40204	70041	524	1	1	1	0	0	1	1	0	0	70041	69792	59715	25	40104	30106	10001	30100	10000	616078	3341769	1	49	66973	70041	70056	64637	3	64944	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	3	0	10002	0	2	1	10000	1	1	1	1	1	2610	1	71	1	1	69819	30003	9	9	9	10000	30100	70057	70057	70054	70054	70057
40204	70056	524	1	1	1	0	0	2	0	0	0	70026	69784	59715	25	40108	30106	10002	30100	10000	616059	3342494	0	49	66976	70056	70041	64652	3	64959	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10003	2	1	10002	0	1	1	10000	1	1	1	1	1	2610	1	71	1	1	69816	30003	0	6	6	10000	30100	70042	70057	70042	70057	70057
40204	70056	525	1	1	0	0	0	2	0	0	0	70041	69787	59712	25	40108	30106	10002	30100	10000	616059	3342350	0	49	66976	70053	70053	64649	3	64944	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	1	10001	0	0	1	10000	1	1	1	1	1	2610	1	71	1	1	69819	30006	0	0	6	10000	30100	70054	70042	70042	70057	70058
40204	70041	524	1	0	0	0	1	14	1	0	0	70078	69787	59701	25	40108	30106	10002	30100	10000	616078	3345362	0	49	66976	70041	70056	64652	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10001	0	2	1	10000	1	1	1	1	1	2610	1	71	1	1	69804	30006	0	0	0	10000	30100	70057	70057	70057	70057	70042

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	525	1	1	1	0	0	0	0	1	0	0	1	70038	69780	59701	25	40018	30016	10002	30010	10000	617009	3342350	0	49	66973	70062	70056	64674	7	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	0	10003	0	2	1	10000	1	1	1	1	0	0	0	2520	1	71	1	1	69819	30006	6	6	6	10000	30010	70079	70042	70057	70054	70054
40024	70053	525	1	1	1	0	0	0	0	1	0	1	0	70038	69780	59715	25	40018	30016	10002	30010	10000	617036	3342494	0	49	66973	70056	70061	64659	0	3	64966	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	3	0	10003	0	2	1	10000	0	1	1	1	3	0	0	2520	1	71	1	1	69819	30006	9	6	0	10000	30010	70173	70054	70042	70055	70057
40024	70041	524	1	0	1	0	0	0	0	2	0	1	1	70026	69702	59715	25	40018	30016	10002	30010	10000	616995	3341769	0	49	66973	70053	70094	64674	0	3	65058	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	1	10002	0	0	1	10000	1	1	1	1	2	0	0	2520	1	71	1	1	69819	30006	9	6	9	10000	30010	70057	70057	70057	70042	70057
40024	70056	524	1	0	1	0	0	0	0	2	0	1	0	70041	69777	59701	25	40014	30016	10002	30010	10000	617036	3342494	0	49	66973	70079	70076	64674	0	3	64981	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	0	10001	0	0	7	10000	1	1	1	1	1	0	0	2520	1	71	1	1	69819	30006	9	6	9	10000	30010	70042	70057	70057	70057	70057
40024	70056	525	1	0	0	0	0	0	0	2	0	1	0	70041	69780	59701	25	40018	30013	10002	30010	10000	617009	3342494	0	49	66973	70056	70059	64659	0	3	64981	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	1	10001	0	1	1	10000	1	1	0	1	0	0	0	2520	1	71	1	1	69816	30003	0	6	6	10000	30010	70057	70054	70042	70042	70042
40024	70056	524	1	1	0	0	0	0	0	1	0	1	1	70041	69777	59715	25	40014	30016	10002	30010	10000	617036	3342494	0	49	66973	70053	70055	64674	0	3	64981	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	0	1	10000	1	1	1	1	1	0	1	2520	1	71	1	1	69816	30006	6	6	6	10000	30010	70042	70042	70042	70054	70042
40024	70063	525	1	0	1	0	0	0	0	1	0	1	0	70041	69777	59715	25	40014	30016	10002	30010	10000	617009	3342494	0	49	66973	70042	70063	64659	0	3	64966	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	1	1	10000	1	1	1	1	0	0	0	2520	1	71	1	1	69816	30003	6	6	6	10000	30010	70042	70042	70042	70042	70054
40024	70041	524	1	1	0	1	1	0	0	2	0	1	0	70026	69777	59712	25	40014	30016	10002	30010	10000	617009	3342350	0	49	63959	70057	70053	64674	0	3	64966	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	1	1	10000	1	1	1	1	1	0	0	2520	1	71	1	1	69819	30006	0	6	6	10000	30010	70054	70057	70054	70042	70054
40024	70041	524	1	0	0	0	0	0	0	2	0	0	0	70038	69780	59712	25	40018	30016	10002	30010	10000	617036	3341769	0	49	66973	70055	70057	64659	0	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10001	0	0	4	10000	1	1	1	1	1	0	0	2520	1	71	1	2	69804	30006	6	6	0	10000	30010	70057	70042	70042	70042	70054
40024	70041	526	1	1	0	1	0	0	0	2	0	0	1	70038	69780	59712	25	40018	30013	10002	30010	10000	616995	3341769	0	49	67070	70055	70053	64674	0	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	2	1	10000	0	1	1	1	2	0	0	2520	1	71	1	1	69819	30006	9	9	9	10000	30010	70057	70042	70057	70057	70042

Test 4: throughput

Count: 8

Code:

  ldrh w0, [x6, x7]
  ldrh w0, [x6, x7]
  ldrh w0, [x6, x7]
  ldrh w0, [x6, x7]
  ldrh w0, [x6, x7]
  ldrh w0, [x6, x7]
  ldrh w0, [x6, x7]
  ldrh w0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26736	201	1	1	1	1	0	0	0	0	0	21	0	0	26699	3	7	7	40	25	80100	100	80000	100	80016	500	1167825	49	23656	26737	26714	16668	6	16671	80116	200	80024	200	160048	26736	64	1	1	80201	100	99	1	100	80000	100	80000	1	100	80020	20	43	0	80058	0	0	0	64	80040	6	1	58	43	19	2	1	1	1	5118	1	16	1	1	26734	13	0	0	80000	100	26739	26737	26723	26737	26738
80204	26714	200	1	1	1	1	1	0	0	0	0	67	0	3	26721	3	7	7	1	25	80100	100	80000	100	80013	500	1167628	49	23656	26736	26714	16664	6	16666	80115	200	80024	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	20	43	0	80059	1	1	2	21	80040	6	1	19	0	19	1	1	1	1	5118	1	16	1	1	26733	10	13	5	80000	100	26739	26737	26740	26746	26738
80204	26737	200	1	1	0	1	1	0	0	0	0	21	0	2	26722	2	7	0	0	25	80100	100	80000	100	80016	500	1167377	49	23657	26736	26736	16664	6	16688	80116	200	80024	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	1	100	80019	20	43	0	80058	0	0	0	60	80040	0	1	58	43	19	1	1	1	1	5118	1	16	1	1	26733	13	0	0	80000	100	26750	26737	26742	26737	26737
80204	26736	200	1	1	0	1	1	0	0	0	0	66	1	2	26699	2	7	7	20	25	80100	100	80000	100	80015	500	1169949	49	23656	26714	26714	16642	6	16688	80115	200	80024	200	160048	26737	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	20	0	0	80019	0	0	0	60	80000	6	1	59	43	19	1	1	1	1	5118	2	16	1	1	26733	13	0	0	80000	100	26724	26737	26743	26715	26737
80204	26736	200	1	1	0	1	1	0	0	0	0	67	0	3	26699	3	7	0	20	25	80100	100	80000	100	80016	500	1166590	49	23634	26736	26736	16642	6	16666	80115	200	80024	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	43	0	80059	0	0	0	61	80039	6	1	58	0	19	1	1	1	1	5118	1	16	1	1	26711	13	0	5	80000	100	26748	26737	26746	26737	26737
80204	26714	200	1	1	0	1	1	0	0	0	0	66	0	0	26721	0	7	7	68	25	80100	100	80000	100	80015	500	1169755	49	23657	26714	26736	16664	6	16688	80116	200	80024	200	160048	26736	65	1	1	80201	100	99	1	100	80000	100	80000	0	100	80020	19	43	0	80058	0	0	0	61	80040	6	1	59	43	19	1	1	1	1	5118	1	16	1	1	26711	13	13	5	80000	100	26738	26741	26745	26720	26716
80204	26714	201	1	1	1	1	1	0	0	0	0	66	0	2	26721	3	7	7	20	25	80100	100	80000	100	80016	500	1167377	49	23657	26736	26736	16664	6	16688	80115	200	80024	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	19	43	0	80019	0	0	1	64	80000	0	1	59	0	19	0	1	1	1	5118	1	16	1	1	26733	13	0	5	80000	100	26737	26738	26738	26715	26737
80204	26736	200	1	1	0	1	0	0	0	0	0	88	0	2	26699	2	7	0	20	25	80100	100	80000	100	80016	500	1167377	49	23657	26714	26736	16664	6	16692	80112	200	80024	200	160048	26736	86	1	1	80201	100	99	0	100	80000	100	80000	0	100	80021	20	43	0	80060	0	0	1	21	80000	0	1	59	43	19	0	1	1	1	5118	1	16	1	1	26711	13	13	5	80000	100	26745	26742	26723	26715	26715
80204	26714	200	1	1	0	1	0	0	0	0	0	70	1	3	26721	0	7	7	1	25	80100	100	80000	100	80015	500	1181321	49	23660	26714	26753	16915	6	16688	80117	200	80024	200	160048	26714	85	1	1	80201	100	99	0	100	80000	100	80000	1	100	80020	20	0	0	80058	1	3	2	61	80039	6	0	60	43	19	0	1	1	1	5118	1	16	1	1	26734	13	0	5	80000	100	26756	26742	27169	26722	26737
80204	26736	200	1	1	1	1	0	0	0	0	0	220	1	3	26699	3	7	0	0	25	80100	100	80000	100	80015	500	1167628	49	23656	26714	26714	16642	6	16691	80116	200	80024	200	160048	26714	85	1	1	80201	100	99	0	100	80000	100	80000	1	100	80020	19	43	0	80059	1	0	0	61	80040	6	1	58	43	19	1	1	1	1	5118	1	16	1	1	26733	0	13	5	80000	100	26723	26737	26748	26738	26737

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	202	1	1	1	0	1	0	0	0	66	0	1	0	3	26700	3	0	7	1	25	80010	10	80000	10	80195	50	1166833	1	49	23647	26727	26727	16672	3	16708	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	0	10	80000	10	80000	1	10	80000	0	43	0	80039	0	0	0	39	80038	0	1	0	0	0	0	0	1	5020	12	16	11	11	26725	0	10	7	80000	10	26729	26729	26732	26709	26728
80024	26728	200	0	0	0	0	0	0	0	0	45	0	0	0	1	26713	2	1	12	0	25	80010	10	80000	10	80000	50	1173870	1	49	23647	26728	26708	16672	3	16708	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	0	80000	0	0	0	39	80039	6	1	58	45	19	0	0	0	5020	16	16	14	14	26711	0	0	5	80000	10	26737	26737	26738	26716	26737
80024	26737	200	1	1	0	0	1	0	0	0	67	0	1	0	2	26699	2	7	7	1	25	80010	10	80000	10	80000	50	1172665	1	49	23648	26727	26727	16672	3	16707	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	0	0	80000	0	0	0	38	80000	6	1	39	43	0	0	0	0	5020	12	16	10	15	26724	14	0	0	80000	10	26728	26732	26729	26729	26728
80024	26728	200	0	0	0	0	0	0	0	0	0	0	0	0	1	26716	2	1	1	16	25	80010	10	80000	10	80000	50	1172435	1	49	23657	26736	26715	16660	3	16716	80010	20	80000	20	160000	26715	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	19	43	0	80058	1	0	0	21	80054	6	1	19	43	19	1	0	0	5020	14	16	15	17	26733	13	13	0	80000	10	26737	26715	26737	26716	26715
80024	26737	200	0	0	0	0	0	0	0	0	0	0	0	0	1	26716	2	1	12	19	25	80010	10	80000	10	80000	50	1171121	1	49	23651	26731	26731	16676	3	16711	80010	20	80000	20	160000	26708	56	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	0	80038	0	0	0	0	80040	6	0	59	43	19	0	0	0	5020	17	16	17	16	26733	13	13	0	80000	10	26716	26737	26737	26738	26737
80024	26736	201	1	0	0	0	0	0	0	0	67	0	0	0	1	26721	3	0	0	19	25	80010	10	80000	10	80000	50	1171615	1	49	23651	26731	26708	16676	3	16711	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	0	80039	0	0	0	39	80040	6	1	19	0	19	0	0	0	5020	17	16	14	11	26733	13	13	5	80000	10	26738	26716	26737	26738	26716
80024	26736	200	1	1	0	0	0	0	0	0	67	0	0	0	3	26721	2	7	0	19	25	80010	10	80000	10	80000	50	1171713	1	49	23628	26731	26731	16676	3	16688	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	0	80038	0	0	0	39	80038	6	1	39	44	0	0	0	0	5020	14	16	13	10	26705	14	14	0	80000	10	26709	26732	26729	26709	26709
80024	26731	200	1	1	0	0	0	0	0	0	70	0	0	0	2	26721	2	7	7	19	25	80010	10	80000	10	80000	50	1171266	1	49	23657	26736	26739	16681	3	16694	80010	20	80000	20	160000	26736	86	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	21	0	0	80059	2	0	0	61	80038	6	0	39	0	0	0	0	0	5020	18	16	15	15	26728	14	10	4	80000	10	26732	26732	26732	26709	26732
80024	26708	201	0	0	0	0	0	0	0	0	104	0	0	0	1	26716	2	1	1	19	25	80010	10	80000	10	80000	50	1171365	1	49	23628	26731	26731	16652	3	16711	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	0	0	80038	0	0	0	38	80040	6	0	59	43	19	0	0	0	5020	17	16	12	16	26733	13	13	5	80000	10	26738	26737	26737	26738	26716
80024	26736	200	1	1	0	0	0	1	1	0	67	0	1	0	2	26722	3	7	7	18	25	80010	10	80000	10	80000	50	1173669	1	49	23651	26708	26731	16676	3	16711	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	0	10	80000	10	80000	1	10	80000	0	43	0	80000	0	0	0	54	80038	6	0	39	43	0	0	0	0	5020	14	16	13	17	26724	14	10	7	80000	10	26732	26732	26732	26732	26729

LDRH (register)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations