Firestorm: MRS (NZCV) measurements

Code:

  mrs x0, nzcv

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	535	4	3	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	73	2	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	9	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	0	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	12	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	0	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536

Count: 8

Code:

  mrs x0, nzcv
  mrs x1, nzcv
  mrs x2, nzcv
  mrs x3, nzcv
  mrs x4, nzcv
  mrs x5, nzcv
  mrs x6, nzcv
  mrs x7, nzcv

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5017

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40185	323	0	0	21	737	60	25	80100	80100	80286	1652000	0	0	49	37055	40135	40135	30050	6	30085	80100	80200	80200	40135	90	1	1	80201	100	99	100	100	544	6	2	3	0	3	2	0	5110	5	1	4	21	3	3	40130	80000	80100	40136	40404	40369	40300	40256
80204	40252	311	0	1	15	139	60	25	80100	80100	80100	1652000	1	5	49	37055	40135	40135	30050	3	30088	80100	80200	80200	40135	90	1	1	80201	100	99	100	100	100	0	0	1	0	3	0	0	5110	5	1	3	21	3	3	40130	80000	80100	40136	40136	40136	40136	40136
80204	40135	311	0	0	0	55	60	25	80100	80100	80100	1652000	1	5	49	37055	40135	40266	30050	3	30088	80100	80200	80200	40135	90	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	5110	5	1	3	21	3	3	40130	80000	80100	40136	40136	40136	40136	40136
80204	40135	311	0	0	0	55	60	25	80100	80100	80100	1652000	1	5	49	37055	40135	40135	30050	3	30088	80100	80200	80200	40135	90	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	5110	5	0	3	21	3	3	40130	80000	80100	40136	40136	40136	40136	40136
80204	40135	311	0	0	0	531	60	25	80100	80100	80100	1652000	1	5	49	37055	40135	40135	30050	3	30088	80100	80200	80200	40135	90	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	5110	5	0	3	21	3	3	40130	80000	80100	40136	40136	40136	40136	40136
80204	40135	311	0	0	0	55	60	25	80100	80100	80100	1652000	1	5	49	37055	40135	40135	30050	3	30088	80100	80200	80200	40135	90	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	5110	5	1	3	21	3	3	40130	80000	80100	40136	40136	40136	40136	40136
80204	40135	311	0	0	0	55	60	25	80100	80100	80100	1652000	1	5	49	37055	40135	40135	30050	3	30088	80100	80200	80200	40135	90	1	1	80201	100	99	100	100	100	0	0	1	0	0	0	0	5110	5	1	3	21	3	3	40130	80000	80100	40136	40136	40136	40136	40136
80204	40135	311	0	0	0	55	60	25	80100	80100	80100	1652000	1	5	49	37055	40308	40135	30050	3	30088	80100	80200	80200	40135	90	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	5110	5	0	3	21	3	3	40130	80000	80100	40136	40136	40136	40136	40136
80204	40135	311	0	0	0	55	60	25	80100	80100	80100	1652000	1	5	49	37055	40135	40135	30050	3	30088	80100	80200	80200	40135	90	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	5110	5	1	3	21	3	3	40130	80000	80100	40136	40136	40136	40136	40136
80204	40135	311	0	0	12	301	60	25	80100	80100	80100	1652000	1	5	49	37055	40135	40135	30050	3	30088	80100	80200	80200	40135	90	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	5110	5	1	3	21	3	3	40130	80000	80100	40136	40136	40136	40136	40136

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9e	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	40061	299	0	0	129	40	25	80010	80010	80010	584075	0	49	36965	40045	40045	29998	3	30021	80010	80020	80020	40045	90	1	1	80021	10	9	10	10	0	10	0	0	0	0	0	0	5020	2	20	2	4	40041	80000	10	80010	40046	40046	40046	40046	40046
80024	40045	300	0	0	0	40	25	80010	80010	80010	584075	0	49	36965	40045	40045	29998	3	30021	80010	80020	80020	40045	90	1	1	80021	10	9	10	10	0	10	1	0	0	0	0	0	5020	3	20	2	3	40041	80000	0	80010	40046	40046	40046	40046	40046
80024	40045	300	0	0	0	40	25	80010	80010	80010	584075	0	49	36965	40045	40045	29998	3	30021	80010	80020	80020	40045	90	1	1	80021	10	9	10	10	0	10	0	0	0	0	0	0	5020	3	20	3	3	40041	80000	0	80010	40046	40046	40046	40046	40046
80024	40045	300	0	0	0	705	109	80010	80010	80010	584075	0	49	36965	40045	40045	29998	3	30021	80010	80020	80112	40045	90	1	1	80021	10	9	10	10	0	10	0	0	0	0	0	0	5020	2	20	3	2	40041	80000	0	80010	40046	40046	40046	40046	40046
80024	40045	300	0	0	0	40	25	80010	80010	80010	584075	0	49	36965	40045	40045	29998	3	30021	80010	80020	80020	40045	90	1	1	80021	10	9	10	10	0	10	0	0	0	0	0	0	5020	3	20	2	3	40041	80000	0	80010	40046	40046	40046	40046	40046
80024	40045	300	0	0	0	40	25	80010	80010	80010	584075	0	49	36965	40045	40045	29998	3	30021	80010	80020	80020	40045	90	1	1	80021	10	9	10	10	0	10	0	1	0	0	0	0	5020	3	20	3	3	40041	80000	0	80010	40046	40046	40046	40046	40046
80024	40045	300	0	0	0	40	25	80010	80010	80010	584075	0	49	36965	40045	40045	29998	3	30021	80010	80020	80020	40045	90	1	1	80021	10	9	10	10	0	10	0	9	0	0	0	0	5020	3	20	3	3	40041	80000	0	80010	40046	40046	40046	40046	40046
80024	40045	300	0	0	0	40	25	80010	80010	80010	584075	0	49	36965	40045	40045	29998	3	30021	80010	80020	80020	40045	90	1	1	80021	10	9	10	10	0	10	0	0	0	0	0	0	5020	3	20	3	3	40041	80000	0	80010	40046	40046	40046	40046	40046
80024	40045	300	0	0	0	40	25	80010	80010	80010	584075	0	49	36965	40045	40045	29998	3	30021	80060	80020	80020	40045	90	1	1	80021	10	9	10	10	0	10	0	0	0	0	0	0	5020	3	20	3	2	40041	80000	0	80010	40046	40046	40046	40046	40046
80024	40045	300	0	0	12	82	25	80010	80010	80010	584075	0	49	36965	40045	40045	29998	3	30021	80010	80020	80020	40045	90	1	1	80021	10	9	10	10	0	10	0	0	0	0	0	1	5020	2	20	4	4	40041	80000	0	80010	40046	40046	40046	40046	40046

MRS (NZCV)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations