Firestorm: LDRSW (register) measurements

Code:

  ldrsw x0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	402	3	1	1	1	1	1	1	21	0	0	1	366	2	7	7	19	25	1000	1000	1000	15577	0	403	403	225	3	261	1000	1000	2000	382	85	1	1	1001	0	1000	1000	0	1019	20	43	1059	1	0	1	21	1039	6	1	58	43	19	2	73	2	16	1	1	379	13	13	5	1000	404	383	404	404	403
1004	403	3	1	1	1	1	0	0	21	0	0	3	388	3	7	7	19	25	1000	1000	1000	14456	1	402	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1020	19	43	1019	1	0	1	61	1000	6	0	58	0	19	1	73	1	16	1	1	400	13	13	5	1000	405	404	404	404	404
1004	402	3	1	0	1	1	0	0	66	1	0	3	388	3	7	7	20	25	1000	1000	1000	15526	1	402	403	204	3	261	1000	1000	2000	402	85	1	1	1001	0	1000	1000	0	1019	20	43	1062	1	0	2	61	1040	6	1	59	43	19	0	73	1	16	1	1	400	0	13	0	1000	404	404	404	403	404
1004	403	3	1	1	1	1	0	0	21	1	0	3	388	2	7	7	18	25	1000	1000	1000	15546	1	403	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	19	43	1060	1	0	2	61	1039	6	1	57	43	19	2	73	1	16	1	1	400	13	0	5	1000	404	404	383	382	404
1004	403	3	1	1	1	1	0	0	67	0	0	2	388	0	7	7	20	25	1000	1000	1000	15501	1	403	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1021	20	43	1019	2	0	2	61	1039	0	1	59	0	19	0	73	1	16	1	1	416	13	13	5	1000	404	404	404	405	404
1004	381	3	1	1	1	0	0	0	21	1	0	1	388	3	7	7	0	25	1000	1000	1000	15480	1	381	403	204	3	261	1000	1000	2000	404	85	1	1	1001	0	1000	1000	0	1021	21	43	1059	0	0	0	21	1040	0	0	19	43	19	1	73	1	16	1	1	378	13	13	5	1000	406	404	383	404	383
1004	403	3	1	1	1	1	0	0	67	1	0	2	366	0	7	7	22	25	1000	1000	1000	15480	1	403	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1020	20	43	1059	1	0	2	64	1040	0	0	19	43	19	1	73	1	16	1	1	400	13	13	5	1000	404	404	403	383	404
1004	403	3	1	1	1	0	0	0	67	1	0	3	388	3	7	7	19	25	1000	1000	1000	15506	0	403	403	225	3	240	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1020	20	43	1059	1	0	1	61	1041	0	1	59	43	19	0	73	1	16	1	1	400	0	0	5	1000	382	404	404	404	382
1004	403	3	1	1	1	1	0	0	67	1	0	0	388	0	7	7	19	25	1000	1000	1000	15524	0	402	403	225	3	261	1000	1000	2000	403	64	1	1	1001	0	1000	1000	0	1019	20	0	1060	1	0	1	60	1040	0	1	58	43	19	1	73	1	16	1	1	399	0	13	5	1000	404	382	403	382	404
1004	403	3	1	0	1	0	0	0	21	1	0	3	388	3	0	7	19	25	1000	1000	1000	15524	1	403	402	225	3	239	1000	1000	2000	382	86	1	1	1001	0	1000	1000	1	1019	21	0	1019	1	0	0	61	1040	0	1	58	45	19	0	73	1	16	1	1	400	13	13	5	1000	383	404	404	404	404

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	1	1	0	1	1	0	70035	69781	59784	25	40104	30103	10001	30100	10000	616005	3342206	49	67022	0	70050	70047	64646	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	100	10000	0	1	10000	0	0	10000	1	1	0	2610	1	71	1	1	69813	30003	9	0	6	10000	30100	70036	70036	70051	70036	70051
40204	70050	524	0	0	0	1	1	0	70035	69781	59709	25	40104	30103	10000	30100	10000	616015	3342062	49	66967	0	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	100	10000	0	1	10005	0	0	10000	1	1	0	2610	1	71	1	1	69800	30000	9	0	9	10000	30100	70051	70051	70051	70051	70051
40204	70050	524	0	0	0	1	0	0	70035	69781	59706	25	40104	30100	10001	30100	10000	616015	3341470	49	66970	0	70035	70035	64646	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	100	10000	0	1	10000	2	0	10000	1	0	0	2610	1	72	1	1	69798	30000	0	6	9	10000	30100	70051	70152	70052	70131	70224
40204	70322	525	0	0	0	18	1	0	70032	69781	59695	25	40104	30103	10001	30100	10000	616005	3341470	49	66955	0	70050	70050	64645	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	100	10000	0	1	10000	1	2426	10000	1	1	0	2610	1	71	1	1	69814	30003	6	0	9	10000	30100	70051	70051	70054	70051	70048
40204	70051	524	0	0	0	6	0	0	70033	69785	59711	25	40100	30103	10001	30100	10000	616005	3341470	49	66970	0	70035	70035	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	100	10000	0	1	10000	0	0	10000	1	0	0	2610	1	71	1	1	69810	30003	0	0	6	10000	30100	70048	70051	70051	70036	70036
40204	70035	525	0	1	1	1	0	0	70035	69781	59709	25	40104	30103	10001	30100	10000	616175	3342206	49	66955	0	70050	70050	64631	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	100	10000	0	0	10000	0	15	10000	1	1	0	2610	1	71	1	1	69813	30000	9	6	0	10000	30100	70036	70051	70036	70051	70051
40204	70047	524	0	0	0	1	0	0	70020	69764	59709	25	40100	30103	10000	30100	10000	616015	3342206	49	66970	0	70050	70047	64646	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	100	10000	0	1	10000	1	3	10000	0	1	0	2610	1	71	1	1	69798	30003	0	9	0	10000	30100	70051	70051	70036	70051	70036
40204	70050	525	0	0	0	0	1	0	70035	69764	59709	25	40104	30103	10001	30100	10000	616015	3342062	49	66955	0	70050	70050	64643	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	100	10000	0	0	10000	0	0	10000	0	1	0	2610	1	71	1	1	69813	30003	0	6	9	10000	30100	70036	70036	70051	70036	70036
40204	70050	525	0	0	0	1	0	0	70020	69781	59709	25	40104	30103	10001	30100	10000	616005	3342062	49	66967	0	70050	70035	64631	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	100	10000	0	0	10000	0	0	10000	1	0	0	2610	1	71	1	1	69798	30003	6	0	6	10000	30100	70036	70048	70051	70051	70051
40204	70035	524	0	0	0	1	1	0	70032	69764	59695	25	40100	30103	10001	30100	10000	616175	3341470	49	66970	0	70050	70047	64715	3	64949	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	100	10000	0	1	10000	0	0	10000	1	0	0	2610	1	71	1	1	69810	30003	6	6	9	10000	30100	70051	70048	70051	70036	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	0	0	0	0	1	1	0	0	1	0	1	0	0	70020	69760	59709	25	40014	30013	10002	30010	10000	616982	3342062	0	49	66955	0	70050	70035	64668	3	64975	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	2520	1	71	1	2	69798	30003	0	6	0	10000	30010	70051	70051	70051	70048	70051
40024	70050	525	0	0	0	0	0	0	0	0	1	0	1	0	0	70035	69760	59709	25	40014	30010	10001	30010	10000	616982	3342062	0	49	66970	0	70050	70050	64659	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	0	0	1	0	0	2520	2	71	1	1	69813	30003	9	6	9	10000	30010	70048	70051	70051	70051	70051
40024	70035	525	0	0	0	0	0	0	0	0	0	0	1	0	0	70035	69760	59695	25	40018	30013	10001	30010	10000	617068	3341470	0	49	66970	0	70050	70035	64668	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	2520	1	71	1	1	69798	30003	9	6	9	10000	30010	70036	70051	70051	70051	70051
40024	70035	524	0	0	0	0	0	0	0	0	1	0	0	0	0	70020	69743	59706	25	40014	30013	10000	30010	10000	616982	3341470	0	49	66970	0	70050	70050	64668	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	0	10000	1	0	0	0	0	2520	1	71	1	1	69813	30003	9	6	0	10000	30010	70036	70051	70048	70036	70051
40024	70091	525	0	0	0	0	0	0	0	0	0	0	0	0	0	70035	69743	59706	25	40010	30013	10000	30010	10000	616982	3342206	1	49	66970	0	70050	70050	64668	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	0	10000	0	0	1	0	0	2520	1	71	1	1	69798	30000	6	6	0	10000	30010	70051	70048	70051	70051	70051
40024	70050	525	0	0	0	0	0	0	0	0	1	0	0	0	0	70035	69760	59706	25	40014	30013	10001	30010	10000	616982	3342062	0	49	66970	0	70035	70035	64653	3	64975	40010	30020	10000	60020	20000	70088	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	2520	1	71	1	1	69813	30000	0	0	9	10000	30010	70048	70048	70036	70048	70036
40024	70050	525	0	0	0	0	0	0	0	0	6	0	0	0	0	70032	69760	59709	25	40010	30013	10001	30010	10000	616982	3342206	0	49	66970	0	70050	70047	64668	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	1	0	0	10001	1	0	1	0	0	2520	1	71	1	1	69810	30003	0	0	0	10000	30010	70036	70048	70037	70036	70051
40024	70035	525	0	0	0	0	0	0	0	0	1	0	1	0	0	70032	69760	59709	25	40014	30010	10000	30010	10000	617068	3342062	0	49	66955	0	70035	70035	64665	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	0	0	1	0	0	2520	2	71	1	1	69810	30000	0	6	9	10000	30010	70036	70051	70051	70051	70051
40024	70035	525	0	0	0	0	0	0	0	0	6	0	0	0	0	70035	69743	59709	25	40010	30013	10000	30010	10000	616952	3342062	0	49	66970	0	70055	70050	64653	3	64975	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	2520	1	71	1	1	69813	30003	9	6	9	10000	30010	70051	70051	70051	70051	70051
40024	70050	525	0	0	0	0	0	0	0	0	0	0	0	0	0	70020	69728	59709	25	40014	30010	10000	30010	10000	616982	3342206	0	49	66970	0	70035	70047	64665	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	2520	1	71	1	1	69810	30003	6	6	9	10000	30010	70051	70048	70051	70051	70036

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70053	525	1	1	1	0	0	0	1	1	0	1	70038	69870	59712	25	40108	30106	10002	30100	10000	616078	3342494	0	49	66961	70073	70052	64637	3	64958	40100	30200	10000	60200	20000	70041	35	1	1	40202	100	99	100	10000	30100	10000	1	100	10002	2	1	10003	0	0	1	10000	1	1	0	1	1	2610	1	71	1	1	69804	30006	9	6	6	10000	30100	70042	70057	70057	70128	70057
40204	70056	524	1	1	1	0	0	0	20	1	0	0	70041	69702	59701	25	40108	30106	10002	30100	10000	616059	3341769	0	49	66961	70083	70057	64649	3	64944	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10001	0	1	1	10000	1	1	0	1	0	2610	1	71	1	1	69819	30006	0	6	6	10000	30100	70057	70042	70057	70057	70042
40204	70041	525	1	1	1	0	0	0	2	0	0	0	70041	69784	59715	74	40104	30106	10002	30250	10000	616105	3342350	0	49	66977	70064	70053	64695	3	64956	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10004	1	1	10002	1	2	1	10000	1	1	1	1	1	2610	1	71	1	1	69816	30003	6	0	6	10000	30100	70057	70057	70054	70054	70042
40204	70056	524	1	0	1	0	0	0	2	0	0	0	70041	69787	59701	25	40108	30103	10001	30100	10000	616059	3342494	0	49	66973	70090	70053	64649	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10007	3	1	10003	0	2	1	10000	1	1	1	1	1	2610	1	71	1	1	69819	30006	9	6	6	10000	30100	70057	70054	70057	70042	70062
40204	70041	524	1	1	0	0	0	0	2	0	0	0	70041	69787	59715	25	40108	30109	10002	30100	10000	616059	3341769	0	49	66973	70076	70064	64637	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10002	0	0	1	10000	1	1	1	1	1	2610	1	71	1	1	69819	30006	6	9	9	10000	30100	70042	70058	70042	70057	70045
40204	70056	525	1	1	0	0	0	0	38	0	0	0	70041	69702	59715	25	40104	30109	10002	30100	10000	616032	3341769	0	49	66976	70061	70057	64649	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	1	1	10000	1	1	1	1	1	2610	1	71	1	1	69804	30003	6	6	6	10000	30100	70042	70057	70042	70054	70057
40204	70041	525	1	1	1	0	0	0	1	1	0	1	70026	69702	59701	25	40104	30103	10002	30100	10000	616032	3342494	0	49	66961	70053	70054	64649	3	64944	40100	30200	10000	60200	20000	70056	35	2	1	40201	100	99	100	10000	30100	10000	0	100	10001	4	1	10002	0	1	1	10000	1	1	1	1	1	2610	1	71	1	1	69816	30006	0	6	0	10000	30100	70042	70057	70057	70054	70054
40205	70056	525	1	0	1	0	0	0	1	1	0	0	70038	69784	59701	25	40108	30106	10002	30100	10000	616078	3342494	0	49	66973	70062	70064	64649	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	1	1	19	10000	1	1	1	1	1	2610	1	71	1	1	69819	30006	0	0	9	10000	30100	70042	70042	70042	70057	70057
40204	70056	524	1	1	1	0	0	0	2	0	0	0	70041	69787	59701	25	40108	30106	10002	30100	10000	616059	3342494	0	49	66961	70057	70056	64637	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	0	10001	0	1	7	10000	0	1	1	1	2	2610	1	71	1	1	69804	30006	9	6	0	10000	30100	70042	70054	70054	70057	70054
40204	70053	524	1	0	0	0	0	0	2	0	0	0	70041	69784	59715	25	40108	30103	10002	30100	10000	616078	3342494	0	49	66976	70074	70060	64652	3	64959	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10001	1	2	1	10000	1	1	0	1	1	2610	1	71	1	1	69804	30006	9	0	9	10000	30100	70042	70042	70057	70057	70057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	525	1	1	0	1	1	1	0	1	1	0	70026	69784	59719	25	40018	30016	10005	30010	10000	616991	3342254	49	66974	70035	70054	64672	3	64960	40010	30020	10000	60020	20000	70054	80	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	0	10000	0	0	10000	1	0	0	0	0	0	2520	1	71	1	2	69817	30003	13	10	10	10000	30010	70052	70052	70055	70055	70052
40024	70051	525	0	0	0	0	0	0	0	0	0	0	70020	69743	59713	25	40010	30010	10001	30010	10000	617068	3342254	49	66974	70059	70054	64672	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	0	0	1	0	0	0	2520	1	71	1	2	69814	30003	10	0	10	10000	30010	70036	70052	70055	70055	70052
40024	70051	524	0	0	0	0	0	0	0	1	1	0	70039	69778	59710	25	40014	30013	10001	30010	10000	616991	3342254	49	66974	70054	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	0	2520	1	71	1	1	69814	30003	0	10	0	10000	30010	70055	70036	70055	70052	70055
40024	70035	525	0	0	0	0	0	0	0	0	0	0	70040	69743	59695	25	40010	30013	10000	30010	10000	617068	3341470	49	66974	70035	70054	64672	3	64979	40010	30020	10000	60020	20000	70054	35	2	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	0	1	0	0	0	2520	1	71	2	1	69817	30003	13	10	13	10000	30010	70052	70055	70055	70055	70052
40024	70051	524	0	0	0	0	0	0	0	7	0	0	70020	69743	59710	25	40014	30013	10001	30010	10000	617068	3342254	49	66971	70035	70054	64653	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10001	0	0	10000	0	0	1	0	0	0	2520	1	71	1	2	69817	30003	13	10	13	10000	30010	70036	70036	70055	70096	70052
40024	70054	525	0	0	0	0	0	0	0	1	0	0	70039	69743	59695	25	40010	30013	10001	30010	10000	617018	3342398	49	66974	70054	70051	64669	3	64976	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	2	9	10000	1	1	0	1	0	0	2520	1	71	1	1	69804	30003	10	0	13	10000	30010	70055	70052	70036	70036	70052
40024	70035	524	0	0	0	0	0	0	0	1	0	0	70036	69743	59713	25	40010	30013	10001	30010	10000	617018	3342398	49	66955	70035	70051	64672	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	0	2520	2	71	2	1	69798	30000	10	13	0	10000	30010	70055	70052	70055	70052	70036
40024	70054	525	0	0	0	0	0	0	0	1	0	0	70036	69778	59713	25	40014	30013	10001	30010	10000	617018	3341470	49	66974	70054	70051	64672	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	0	2520	1	71	1	1	69822	30003	13	13	13	10000	30010	70036	70055	70055	70055	70036
40024	70035	525	0	0	0	0	0	0	0	0	0	0	70039	69743	59713	25	40014	30013	10001	30010	10000	617018	3342254	49	66955	70051	70035	64653	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	0	2520	1	71	2	1	69814	30003	13	10	0	10000	30010	70055	70055	70055	70036	70055
40024	70054	524	0	0	0	0	0	0	0	0	0	0	70020	69743	59710	25	40014	30010	10000	30010	10000	616991	3341470	49	66974	70054	70054	64672	3	64979	40010	30020	10065	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	0	2520	1	71	2	1	69817	30000	0	0	13	10000	30010	70055	70055	70055	70055	70055

Test 4: throughput

Count: 8

Code:

  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	0	1	0	0	0	0	0	41	0	1	0	2	26784	2	12	12	16	25	80100	100	80000	100	80015	500	1165856	0	49	23642	26727	26727	16655	6	16659	80116	200	80024	200	160048	26722	72	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80039	0	0	39	80000	6	0	0	0	0	1	1	1	5118	1	16	0	0	26704	1	6	6	2	80000	100	26728	26708	26728	26723	26728
80204	26722	200	0	0	0	0	0	0	0	45	0	0	0	2	26722	2	12	12	0	25	80100	100	80000	100	80015	500	1166596	0	49	23647	26707	26707	16635	6	16679	80114	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80000	0	0	51	80000	6	1	35	43	0	1	1	1	5118	0	16	0	0	26724	0	6	0	4	80000	100	26728	26728	26708	26728	26708
80204	26727	200	0	0	0	0	0	0	0	45	0	0	0	2	26717	0	0	12	0	25	80100	100	80000	100	80015	500	1166596	0	49	23647	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80039	0	0	0	80039	6	1	35	43	0	1	1	1	5118	0	16	0	0	26719	0	10	10	4	80000	100	26708	26708	26723	26708	26708
80204	26727	200	0	0	0	0	0	0	0	0	0	0	0	2	26704	0	12	12	16	25	80100	100	80000	100	80016	500	1165856	0	49	23647	26727	26707	16655	6	16674	80115	200	80024	200	160048	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80000	0	0	38	80039	6	0	35	43	0	1	1	1	5118	0	16	0	0	26724	0	10	10	0	80000	100	26708	26708	26723	26723	26728
80204	26722	200	0	0	0	0	0	0	0	45	0	0	0	2	26698	0	12	0	16	25	80100	100	80000	100	80015	500	1177116	1	49	23647	26707	26727	16635	6	16659	80114	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80039	0	0	0	80035	6	1	35	0	0	1	1	1	5118	0	16	0	0	26704	0	10	10	0	80000	100	26728	26708	26728	26708	26728
80204	26727	200	0	0	0	0	0	0	0	45	0	1	0	1	26748	3	0	12	0	25	80100	100	80000	100	80014	500	1167875	0	49	23642	26707	26707	16655	6	16659	80115	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	39	0	80035	0	0	35	80000	0	1	0	43	0	1	1	1	5118	0	16	0	0	26712	0	10	6	4	80000	100	26728	26789	26708	26725	26708
80204	26707	200	0	0	0	0	0	0	0	45	0	0	0	1	26715	2	12	12	0	25	80100	100	80000	100	80015	500	1167303	0	49	23627	26727	26727	16635	6	16679	80116	200	80024	200	160048	26727	72	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80039	0	0	39	80039	6	1	36	39	0	1	1	1	5118	0	16	0	0	26719	0	6	6	2	80000	100	26728	26728	26708	26708	26728
80204	26707	200	0	0	0	0	0	0	0	45	0	0	0	1	26721	2	18	0	16	25	80100	100	80000	100	80015	500	1167875	1	49	23642	26727	26727	16635	6	16659	80115	200	80024	200	160048	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	0	80040	0	0	39	80000	6	1	35	43	0	1	1	1	5118	0	16	0	0	26724	0	10	0	0	80000	100	26708	26708	26728	26728	26723
80204	26727	200	0	0	0	0	0	0	0	41	0	1	0	2	26724	2	18	12	16	25	80100	100	80000	100	80015	500	1167875	0	49	23647	26727	26722	16635	6	16659	80114	200	80024	200	160048	26722	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80000	0	0	0	80039	6	0	35	43	0	1	1	1	5118	0	16	0	0	26724	0	10	6	0	80000	100	26708	26708	26708	26728	26728
80204	26707	200	0	0	0	0	1	0	0	45	0	0	0	2	26701	2	0	18	12	25	80100	100	80000	100	80014	500	1177116	1	49	23642	26727	26727	16655	6	16674	80115	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	39	80039	6	1	35	0	0	1	1	1	5118	0	16	0	0	26724	0	6	6	4	80000	100	26728	26728	26728	26708	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26727	200	1	0	0	60	1	0	1	26712	2	0	12	16	25	80010	10	80000	10	80000	50	1166896	0	0	49	23647	26727	26708	16676	3	16708	80010	20	80000	20	160000	26732	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	0	0	0	39	80039	6	1	40	43	0	5020	15	0	9	16	0	8	8	26705	10	10	0	80000	10	26732	26729	26732	26729	26731
80024	26731	200	0	0	0	45	0	0	0	26713	2	12	0	0	25	80010	10	80000	10	80000	50	1168843	0	0	49	23647	26731	26728	16672	3	16707	80010	20	80000	20	160000	26815	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	0	0	39	80038	6	1	39	44	0	5020	12	0	9	16	0	8	6	26710	10	0	7	80000	10	26732	26728	26709	26728	26709
80024	26708	201	0	0	0	0	1	0	0	26712	2	12	12	19	25	80010	10	80000	10	80000	50	1168843	0	0	49	23651	26727	26728	16672	3	16711	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	0	0	0	80039	6	1	39	43	0	5020	12	0	9	16	0	6	7	26724	10	0	4	80000	10	26729	26729	26729	26729	26732
80024	26731	200	0	0	0	44	0	0	1	26716	0	0	12	19	25	80010	10	80000	10	80000	50	1166896	0	0	49	23648	26727	26708	16672	3	16688	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	0	0	0	80039	0	1	39	43	0	5020	12	0	9	16	0	9	9	26705	10	0	4	80000	10	26728	26728	26729	26729	26709
80024	26708	200	0	0	0	44	0	0	1	26716	2	0	12	16	25	80010	10	80000	10	80000	50	1166886	0	0	49	23648	26708	26727	16672	3	16707	80010	20	80000	20	160000	26835	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	0	0	0	80039	6	0	0	0	0	5020	12	0	7	16	0	7	7	26724	25	0	4	80000	10	26894	26729	26711	26728	26728
80024	26727	200	0	0	1	45	1	0	1	26713	2	12	12	0	25	80010	10	80000	10	80000	50	1168843	0	0	49	23647	26728	26708	16672	3	16707	80010	20	80000	20	160000	26729	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	0	0	39	80039	6	1	0	43	0	5020	12	0	7	16	0	7	8	26728	0	0	7	80000	10	26732	26728	26728	26728	26729
80024	26728	201	0	0	0	45	1	0	0	26693	2	0	1	0	25	80010	10	80000	10	80000	50	1168843	0	0	49	23651	26731	26731	16672	3	16711	80010	20	80000	20	160000	26732	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80039	0	0	0	38	80000	6	1	0	44	0	5020	12	0	9	16	0	9	9	26725	10	14	4	80000	10	26732	26732	26709	26728	26732
80024	26731	200	0	0	0	45	1	0	1	26713	2	12	12	19	25	80010	10	80000	10	80000	50	1166886	1	1	49	23647	26731	26708	16672	3	16708	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	0	0	39	80039	6	1	39	44	0	5020	12	0	10	16	0	8	8	26724	14	0	4	80000	10	26729	26729	26728	26728	26732
80024	26731	200	1	0	0	45	0	0	0	26716	2	1	12	16	25	80010	10	80000	10	80000	50	1166750	0	0	49	23647	26728	26731	16672	3	16708	80010	20	80000	20	160000	26732	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	0	0	38	80038	0	1	39	43	0	5020	12	0	8	16	0	8	9	26724	10	14	4	80000	10	26729	26732	26732	26732	26728
80024	26731	200	0	1	0	44	0	0	1	26693	2	0	0	16	25	80010	10	80000	10	80000	50	1167201	1	0	49	23647	26728	26708	16652	3	16707	80010	20	80000	20	160000	26735	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	0	0	39	80039	0	1	0	44	0	5020	12	0	9	16	0	8	6	26705	14	10	0	80000	10	26728	26728	26728	26709	26732

LDRSW (register)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations