Firestorm: STR (register, 32-bit) measurements

Code:

  str w0, [x6, x7]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	543	4	0	3	1	527	16	16	6	25	1000	1000	1000	22448	0	542	542	355	3	412	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	540	1000	544	544	544	544	543
1004	542	4	0	3	1	528	16	16	1	25	1000	1000	1000	22448	0	542	542	367	3	412	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	544	544	544
1004	543	4	0	3	1	527	16	16	1	25	1000	1000	1000	22448	0	542	542	355	3	410	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	540	1000	544	544	544	544	543
1004	542	4	0	3	0	527	16	16	0	25	1000	1000	1000	22448	0	543	542	355	3	412	1000	1000	3000	543	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	555	543
1004	542	4	0	3	1	527	16	16	0	25	1000	1000	1000	22448	0	542	542	355	3	412	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	1	527	16	16	1	25	1000	1000	1000	22472	0	542	543	356	3	412	1000	1000	3000	542	543	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	540	1000	544	544	544	544	544
1004	543	4	0	3	1	527	16	16	1	25	1000	1000	1000	22472	0	542	543	356	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	544	544	543	543	543
1004	542	5	0	3	1	527	16	16	1	25	1000	1000	1000	22472	0	542	543	356	3	412	1000	1000	3000	554	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	544	544	543	543	543
1004	542	4	0	3	1	528	16	16	0	25	1000	1000	1000	22472	1	542	542	355	3	409	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	540	1000	543	543	544	544	588
1004	543	4	0	3	1	527	16	16	1	25	1000	1000	1000	22472	0	542	543	356	3	412	1000	1000	3000	542	543	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	555	543	543	543	543

Count: 8

Code:

  str w0, [x6, x7]
  str w0, [x6, x7]
  str w0, [x6, x7]
  str w0, [x6, x7]
  str w0, [x6, x7]
  str w0, [x6, x7]
  str w0, [x6, x7]
  str w0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	0	0	84	6	0	40027	16	16	29	25	80100	100	80000	100	80007	500	1839455	1	49	36963	40049	40049	29969	7	30002	80107	200	80016	200	240048	40042	32004	1	1	80201	100	99	100	80000	100	80000	100	80060	34	0	80002	1	5	80002	2	0	1	1	1	5118	2	16	2	2	40037	0	80000	100	40052	40043	40051	40041	40043
80204	40042	299	0	0	0	9	1	40027	16	0	0	25	80100	100	80060	100	80007	500	1839455	1	49	36962	40051	40042	29959	7	29994	80107	200	80016	200	240048	40050	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	8	80000	2	34	1	1	1	5118	1	16	1	2	40039	0	80000	100	40043	40050	40041	40041	40041
80204	40040	300	0	0	0	6	1	40027	16	16	0	25	80100	100	80000	100	80007	500	1839455	0	49	36962	40051	40042	29969	7	29992	80107	200	80016	200	240048	40050	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80062	0	5	80002	2	34	1	1	1	5118	2	16	2	1	40039	0	80000	100	40043	40043	40043	40043	40051
80204	40042	300	0	0	0	0	1	40025	16	16	0	25	80100	100	80000	100	80007	500	1839378	1	49	36960	40040	40042	29961	7	29994	80107	200	80016	200	240048	40050	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	1	2	80002	2	0	1	1	1	5118	2	16	2	1	40037	0	80000	100	40050	40041	40051	40043	40043
80204	40040	300	0	0	0	0	1	40025	16	16	0	25	80100	100	80000	100	80007	500	1839378	1	49	36960	40040	40042	29961	7	29994	80107	200	80016	200	240048	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80002	0	2	80002	2	34	1	1	1	5118	1	16	1	2	40037	0	80000	100	40050	40043	40051	40043	40043
80204	40042	300	0	0	72	3	1	40025	0	16	0	25	80100	100	80000	100	80007	500	1839887	1	49	36971	40042	40042	29961	7	30002	80106	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80000	0	2	80002	2	34	1	1	1	5118	2	16	2	1	40037	0	80000	100	40051	40041	40050	40043	40041
80204	40042	300	0	0	6	3	1	40035	16	16	0	25	80100	100	80000	100	80007	500	1839455	1	49	36960	40050	40040	29968	7	29994	80107	200	80016	200	240048	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80002	0	2	80000	2	0	1	1	1	5118	1	16	2	1	40037	0	80000	100	40041	40043	40051	40043	40043
80204	40042	300	0	0	0	3	1	40035	0	0	0	25	80100	100	80000	100	80006	500	1839455	1	49	36962	40049	40042	29961	7	29994	80107	200	80142	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	0	80002	2	34	1	1	1	5118	1	16	2	2	40039	19	80000	100	40043	40052	40041	40052	40050
80204	40042	300	0	0	0	0	0	40025	16	16	0	25	80100	100	80000	100	80006	500	1839378	1	49	36962	40040	40050	29970	7	29994	80107	200	80016	200	240048	40051	32003	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	5	80000	2	34	1	1	1	5118	2	16	2	2	40039	0	80000	100	40041	40041	40041	40041	40043
80204	40050	300	0	0	0	3	1	40027	16	0	0	25	80100	100	80000	100	80007	500	1839455	1	49	36960	40042	40051	29970	7	29994	80106	200	80016	200	240048	40040	32003	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	2	80002	2	34	1	1	1	5118	1	16	2	1	40039	0	80000	100	40051	40043	40051	40043	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	0	19	1	0	1	40043	16	0	0	25	80010	10	80000	10	80000	50	1839424	0	1	49	36962	40179	40040	29977	3	30022	80010	20	80000	20	240000	40050	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	3	0	80002	2	34	5020	0	0	0	4	16	0	0	0	2	4	40039	0	80000	10	40051	40043	40041	40043	40043
80024	40040	300	0	0	0	0	3	1	0	0	40035	16	0	0	25	80010	10	80000	10	80000	50	1839424	0	1	49	36971	40042	40040	29977	3	30030	80010	20	80000	20	240000	40042	40051	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	1	2	80000	2	34	5020	0	0	0	2	16	0	0	0	4	2	40037	0	80000	10	40052	40043	40052	40043	40043
80024	40042	300	0	0	0	0	3	0	0	1	40025	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	1	49	36960	40042	40042	30068	3	30030	80118	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80000	0	810	80000	2	34	5020	0	0	0	2	16	0	0	0	4	2	40048	0	80000	10	40041	40041	40043	40043	40043
80024	40040	300	0	0	0	6	3	1	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839424	0	1	49	36969	40042	40040	29975	3	30030	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80000	0	5	80000	2	0	5020	0	0	0	2	16	0	0	0	4	2	40048	0	80000	10	40043	40041	40043	40043	40043
80024	40050	299	0	0	0	0	3	0	0	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839352	0	0	49	36962	40040	40050	29985	3	30022	80010	20	80000	20	240000	40049	40049	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	0	2	80000	0	34	5020	0	0	0	4	16	0	0	0	4	2	40039	0	80000	10	40051	40041	40041	40043	40052
80024	40042	300	0	0	0	21	0	0	0	0	40027	0	0	0	25	80010	10	80000	10	80000	50	1839856	0	1	49	36960	40042	40051	29977	3	30022	80010	20	80000	20	240000	40040	40051	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	0	2	80002	2	0	5020	0	0	0	4	16	0	0	0	4	2	40039	0	80000	10	40050	40043	40043	40043	40051
80024	40040	300	0	0	0	0	3	1	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	0	49	36962	40042	40040	29975	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	28	0	80000	0	11	80002	0	34	5020	0	0	0	7	16	0	0	0	3	4	40048	0	80000	10	40044	40041	40043	40043	40051
80024	40042	299	0	0	0	0	0	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	1	49	36960	40042	40042	29977	3	30020	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80000	0	0	80000	2	0	5020	0	0	0	4	16	0	0	0	4	2	40039	0	80000	10	40041	40041	40043	40041	40041
80024	40042	299	0	0	0	0	9	1	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839352	1	1	49	36960	40042	40042	29977	3	30031	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80000	5	3	80002	0	0	5020	0	0	0	8	16	0	0	0	2	4	40039	0	80000	10	40041	40041	40043	40192	40043
80024	40042	300	0	0	0	0	9	0	0	0	40036	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	1	49	36960	40051	40042	29977	3	30022	80010	20	80000	20	240000	40050	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	0	2	80000	0	0	5020	0	0	0	4	16	0	0	0	8	4	40039	0	80000	10	40051	40043	40051	40041	40041

STR (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations