Firestorm: STR (register, lsl, 32-bit) measurements

Code:

  str w0, [x6, x7, lsl #2]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	552	4	1	1	0	0	15	21	0	1	544	16	16	5	25	1000	1000	1000	23244	553	557	365	3	416	1000	1000	3000	551	558	1	1	1001	1000	1000	1015	15	36	0	2	1016	0	1	20	1002	16	36	14	2	73	1	16	1	1	549	1000	559	559	553	554	553
1004	552	4	1	0	0	0	0	19	1	1	544	16	16	5	25	1000	1000	1000	23247	558	550	372	3	418	1000	1000	3000	559	551	1	1	1001	1000	1000	1014	16	36	0	0	1016	0	0	18	1002	16	36	14	1	73	1	16	1	1	554	1000	552	561	559	559	559
1004	558	4	1	1	1	0	0	17	1	1	544	16	16	5	25	1000	1000	1000	22908	551	558	366	3	417	1000	1000	3000	552	559	1	1	1001	1000	1000	1015	14	36	0	2	1016	0	0	18	1002	16	36	14	2	73	1	16	1	1	555	1000	561	560	559	559	559
1004	552	4	1	0	1	0	0	18	0	1	537	16	16	5	25	1000	1000	1000	23244	553	557	365	3	416	1000	1000	3000	552	560	1	1	1001	1000	1000	1014	14	36	0	0	1016	0	1	20	1002	16	36	14	0	73	1	16	1	1	555	1000	559	559	559	559	553
1004	553	4	1	1	1	0	0	17	0	1	544	16	16	7	25	1000	1000	1000	23197	558	551	372	3	408	1000	1000	3000	559	552	1	1	1001	1000	1000	1014	15	36	0	1	1016	0	2	18	1002	16	35	14	1	73	1	16	1	1	549	1000	559	553	554	552	551
1004	560	4	1	1	1	0	0	18	1	1	543	16	16	5	25	1000	1000	1000	23316	559	552	372	3	410	1000	1000	3000	559	552	1	1	1001	1000	1000	1014	14	36	0	0	1016	0	1	17	1002	16	35	14	2	73	1	16	1	1	549	1000	560	560	553	553	552
1004	550	4	1	1	0	0	0	19	1	1	537	16	16	5	25	1000	1000	1000	22908	551	558	366	3	417	1000	1000	3000	553	557	1	1	1001	1000	1000	1015	15	36	0	1	1016	0	1	18	1002	16	36	14	1	73	1	16	1	1	555	1000	550	559	559	559	559
1004	558	4	1	1	1	0	0	19	0	1	544	16	16	3	25	1000	1000	1000	22860	559	552	373	3	410	1000	1000	3000	558	552	1	1	1001	1000	1000	1015	15	36	3	0	1016	0	1	19	1002	16	36	14	1	73	1	16	1	1	547	1000	553	553	552	561	562
1004	559	4	1	1	1	0	0	18	0	1	537	16	16	5	25	1000	1000	1000	23244	552	561	372	3	416	1000	1000	3000	552	558	1	1	1001	1000	1000	1016	16	34	0	2	1016	0	2	18	1002	16	36	14	0	73	1	16	1	1	547	1000	553	553	552	561	562
1004	559	4	1	0	1	0	0	19	0	1	544	16	16	5	25	1000	1000	1000	23292	558	553	371	3	410	1000	1000	3000	558	552	1	1	1001	1000	1000	1016	16	36	3	1	1016	0	0	19	1002	16	36	14	1	73	1	16	1	1	549	1000	559	559	559	553	554

Count: 8

Code:

  str w0, [x6, x7, lsl #2]
  str w0, [x6, x7, lsl #2]
  str w0, [x6, x7, lsl #2]
  str w0, [x6, x7, lsl #2]
  str w0, [x6, x7, lsl #2]
  str w0, [x6, x7, lsl #2]
  str w0, [x6, x7, lsl #2]
  str w0, [x6, x7, lsl #2]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	0	0	0	3	1	0	40035	16	16	5	25	80100	100	80000	100	80007	500	1839455	49	36962	40049	40042	29961	7	29994	80107	200	80016	200	240048	40051	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	0	0	80002	2	34	1	1	1	5118	0	16	0	0	40039	80000	100	40043	40041	40051	40044	40041
80204	40042	300	0	0	0	0	0	0	40035	16	16	0	25	80100	100	80000	100	80007	500	1839455	49	36970	40042	40042	29959	7	30001	80107	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	1	0	2	80002	2	0	1	1	1	5118	0	16	0	0	40039	80000	100	40051	40043	40043	40050	40438
80204	40042	300	0	0	27	3	1	0	40027	16	0	0	25	80100	100	80000	100	80007	500	1839455	49	36962	40040	40051	30022	7	30002	80107	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	0	0	80002	0	34	1	1	1	5118	0	16	0	0	40039	80000	100	40043	40041	40045	40043	40043
80204	40040	299	0	0	0	3	1	0	40027	16	16	0	25	80100	100	80000	100	80007	500	1839455	49	36962	40050	40042	29961	7	29994	80107	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80000	0	0	8	80002	2	34	1	1	1	5118	0	16	0	0	40037	80000	100	40050	40053	40052	40043	40052
80204	40040	300	0	0	0	3	1	0	40035	16	0	291	25	80100	100	80000	100	80006	500	1839455	49	36970	40042	40051	29968	7	29994	80106	200	80016	200	240048	40040	32003	1	1	80202	100	99	100	80000	100	80000	100	80000	34	0	80002	0	0	5	80000	0	34	1	1	1	5118	0	16	0	0	40037	80000	100	40043	40043	40043	40041	40043
80204	40042	300	0	0	9	9	1	0	40027	16	16	0	25	80100	100	80000	100	80006	500	1839455	49	33977	40042	40042	29961	7	29992	80107	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80002	0	0	0	80002	2	34	1	1	1	5118	0	16	0	0	40039	80000	100	40043	40043	40051	40041	40041
80204	40042	300	0	0	0	3	1	0	40025	16	0	0	25	80100	100	80000	100	80006	500	1839378	49	36962	40042	40040	29959	7	29994	80107	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	4	0	2	80000	2	34	1	1	1	5118	0	16	0	0	40037	80000	100	40043	40043	40043	40043	40043
80204	40049	300	0	0	0	0	1	0	40025	16	0	0	25	80100	100	80000	100	80007	500	1839378	49	36962	40040	40042	29961	7	29992	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	0	5	80002	2	34	1	1	1	5118	0	16	0	0	40039	80000	100	40043	40043	40191	40043	40043
80204	40042	300	0	0	0	3	1	0	40035	16	0	0	25	80100	100	80000	100	80007	500	1839791	49	36962	40042	40042	29961	7	29994	80107	200	80016	200	240048	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	0	8	80002	0	0	1	1	1	5118	0	16	0	0	40039	80000	100	40051	40044	40043	40043	40050
80204	40042	300	0	0	0	6	1	0	40027	0	16	74	25	80100	100	80000	100	80012	500	1839381	49	36962	40042	40050	29960	10	29982	80112	200	80022	200	240066	40049	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	0	2	80002	2	34	2	2	2	5118	0	16	0	0	40037	80000	100	40050	40043	40051	40043	40052

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	0	0	0	0	0	3	1	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40040	29978	3	30020	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80064	0	42	0	0	80002	0	0	0	80002	2	42	0	0	0	5020	15	16	11	13	40040	0	0	80000	10	40041	40041	40043	40043	40044
80024	40042	300	0	0	0	0	0	0	0	0	3	0	0	40028	0	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36962	40042	40042	29978	3	30023	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	0	0	0	0	5020	12	16	12	14	40037	0	0	80000	10	40043	40041	40041	40043	40043
80024	40042	300	0	0	0	0	0	0	0	0	3	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	1	49	36963	40040	40042	29978	3	30023	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	0	0	2	80000	0	42	0	0	0	5020	7	16	12	11	40037	0	0	80000	10	40043	40041	40041	40043	40053
80024	40040	300	0	0	0	0	0	0	0	0	3	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	1	49	36963	40042	40042	29975	3	30023	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80000	0	0	2	80002	2	42	0	0	0	5020	13	16	11	11	40039	0	0	80000	10	40055	40043	40043	40041	40043
80024	40042	300	0	0	0	0	0	0	0	0	3	0	0	40025	0	16	0	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40040	40042	29989	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80002	0	0	0	80002	2	42	0	0	0	5020	11	16	12	7	40037	0	0	80000	10	40044	40041	40043	40041	40043
80024	40042	300	0	0	0	0	0	0	0	0	3	1	0	40165	16	0	0	25	80010	10	80000	10	80000	50	1839352	1	49	36960	40042	40042	29978	3	30023	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	1	0	0	80000	2	42	0	0	0	5020	6	16	12	10	40037	0	0	80000	10	40043	40044	40041	40053	40044
80024	40042	300	0	0	0	0	0	0	0	0	3	0	0	40027	0	16	1	25	80010	10	80000	10	80000	50	1839448	1	49	36974	40042	40040	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80002	0	0	2	80000	2	42	0	0	0	5020	12	16	10	10	40039	0	0	80000	10	40044	40041	40043	40044	40043
80024	40043	299	0	0	0	0	0	0	0	0	3	0	0	40027	0	0	0	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40050	29977	3	30020	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80000	0	0	2	80000	2	42	0	0	0	5020	11	16	11	11	40037	0	0	80000	10	40043	40043	40041	40043	40043
80024	40040	300	0	0	0	0	0	0	0	0	3	0	0	40027	0	16	1	25	80010	10	80000	10	80000	50	1842460	1	49	36962	40042	40042	29978	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80000	0	0	2	80002	2	42	0	0	0	5020	12	16	7	12	40039	0	0	80000	10	40044	40044	40043	40043	40043
80024	40040	300	0	0	0	0	0	0	0	0	0	1	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839352	1	49	36962	40040	40042	29975	3	30023	80010	20	80000	20	240000	40043	40043	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	0	0	0	80002	2	0	0	0	0	5020	12	16	11	8	40039	0	0	80000	10	40044	40041	40043	40044	40043

STR (register, lsl, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations