Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

BICS (register, 64-bit)

Test 1: uops

Code:

  bics x0, x0, x1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10041035800619172510001000100062250110351035805388210001000200010354011100110000073227229931000100010361036103610361036
10041035800619172510001000100062250110351035805388210001000200010354011100110000073227229931000100010361036103610361036
10041035800619172510001000100062250110351035805388210001000200010354011100110000673227229931000100010361036103610361036
10041035700619172510001000100062250110351035805388210001000200010354011100110000073227229931000100010361036103610361036
10041035800619172510001000100062250110351035805388210001000200010354011100110000073227229931000100010361036103610361036
10041035800829172510001000100062250010351035805388210001000200010354011100110000073227229931000100010361036103610361036
10041035800619172510001000100062250110351035805388210001000200010354011100110000073227229931000100010361036103610361036
10041035803619172510001000100062250110351035805388210001000200010354011100110000073227229931000100010361036103610361036
10041035800619172510001000100062250110351035805388210001000200010354011100110000073227229931000100010361036103610361036
10041035800619172510001000100062250010351035805388210001000200010354011100110000073227229931000100010361036103610361036

Test 2: Latency 1->2

Code:

  bics x0, x0, x1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357501249920251010010100101006471524969551003510035865638732101001020020200100354011102011009910010100100071012711999510000101001003610036100361003610036
10204100357501459920251010010100101006471524969551003510035865638732101001020020200100354011102011009910010100100071012711999510000101001003610036100361003610036
1020410035750619920251010010100101006471524969551003510035865638732101001020020200100354011102011009910010100100071012711999510000101001003610036100361003610036
10204100357504139920251010010100101006471524969551003510035865638732101001020020200100354011102011009910010100100171012711999510000101001003610036100361003610036
1020410035750619920251010010100101006471524969551003510035865638732101001020020200100354011102011009910010100100071012711999510000101001003610036100361003610036
1020410035750619920251010010100101006471524969551003510035865638732101001020020200100354011102011009910010100100071012712999510000101001003610036100361003610036
1020410035750619920251010010100101006471524969551003510035865638732101001020020200100354011102011009910010100100071012711999510000101001003610036100361003610036
1020410035750619920251010010100101006471524969551003510035865638732101001020020200100354011102011009910010100100071012711999510000101001003610036100361003610036
1020410035750619920251010010100101006471524969551003510035865638732101001020020200100354011102011009910010100100071012711999510000101001003610036100361003610036
1020410035750619920251010010100101006471524969551003510035865638732101001020020200100354011102011009910010100100071012711999510000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575061991825100101001010010647246149695510035100358678387541001010020200201003540111002110910100101000064042743999710000100101003610036100361003610036
10024100357506199182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010101404864042744999710000100101003610036100361003610036
1002410035751561991825100101001010010647246149695510035100358678387541001010020200201003540111002110910100101000064042743999710000100101003610036100361003610036
100241003575061991825100101001010010647246149695510035100358678387541001010020200201003540111002110910100101000064042744999710000100101003610036100361003610036
1002410035750619918251001010010100106472461496955100351003586783875410010100202002010035401110021109101001010550064042743999710000100101003610036100361003610036
1002410035750619918251001010010100106472461496955100351003586783875410010100202002010035401110021109101001010300664032734999710000100101003610036100361003610036
1002410035750328991825100101001010010647246149695510035100358678387541001010020200201003540111002110910100101000064042743999710000100101003610036100361003610036
100241003576061991825100101001010010647246149695510035100358678387541001010020200201003540111002110910100101000064042734999710000100101003610036100361003610036
100241003575082991825100101001010010647246149695510035100358678387541001010020200201003540111002110910100101000064042734999710000100101003610036100361003610036
10024100357506199182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010106010264032734999710000100101003610036100361003610036

Test 3: Latency 1->3

Code:

  bics x0, x1, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003575006199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001001071012711999510000101001003610036100361003610036
102041003575006199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001003071012711999510000101001003610036100361003610036
102041003575006199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001000072812711999510000101001003610036100361003610036
102041003575006199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001000071012711999510000101001003610036100361003610036
102041003575006199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001000071012711999510000101001003610036100361003610036
1020410035750031899202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001000071012711999510000101001003610036100361003610036
102041003575006199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001000071012721999510000101001003610036100361003610036
10204100357500619920251010010100101006471524969551003510035865638732101001020020200100354011102011009910010100100027071012711999510000101001003610036100361003610036
102041003575006199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001000071012711999510000101001003610036100361003610036
102041003575006199202510100101001010064715249695510035100358656387321010010200202001003540111020110099100101001003071012711999510000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002410035750061991825100101001010010647246049695510035100358678387541001010020200201003540111002110910100101000064052766999710000100101003610036100361003610036
100241003575390619918251001010010100106472460496955100351003586783875410010100202002010035401110021109101001010009664072777999710000100101003610036100361003610036
1002410035750061991825100101001010010647246049695510035100358678387541001010020200201003540111002110910100101000064062776999710000100101003610036100361003610036
10024100357500619918251001010010100106472460496955100351003586783875410010100202002010035401110021109101001010001264062767999710000100101003610036100361003610036
1002410035750061991825100101001010010647246049695510035100358678387541001010020200201003540111002110910100101000364072777999710000100101003610036100361003610036
1002410035750061991825100101001010010647246049695510035100358678387541001010020200201003540111002110910100101000064072767999710000100101003610036100361003610036
1002410035750061991825100101001010010647246049695510035100358678387541001010020200201003540111002110910100101000064062775999710000100101003610036100361003610036
1002410035750061991825100101001010010647246049695510035100358678387541001010020200201003540111002110910100101000064052757999710000100101003610036100361003610036
1002410035750061991825100101001010010647246049695510035100358678387541001010020200201003540111002110910100101000064072767999710000100101003610036100361003610036
1002410035750061991825100101003210010647246049695510035100358678387541001010020200201003540111002110910100101000064062777999710000100101003610036100361003610036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  bics x0, x1, x2
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)dde0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204200351500611993025201002010020112129957504916955200352003517425817486201122022430236200356411202011009910020100101000011113191612001220000201002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425717485201122022430236200356411202011009910020100101000011113201602001220000201002003620036200362003620036
20204200351501621681993025201222012220112129723304916955200352003517425717485201122022430236200356411202011009910020100101000611113191602001220000201002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425717486201122022430236200356411202011009910020100101000011113191602001220000201002003620036200362003620036
2020420035150121031993025201002010020112129723304916955200352003517425817485201122022430236200356411202011009910020100101000011113201602001220000201002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425717486201122022430236200356411202011009910020100101000011113201602001220000201002003620036200362003620036
202042003515001031993025201002010020112129723304916955200352003517425817486201942022430236200356411202011009910020100101000011113191602001220000201002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425717485201122022430236200356411202011009910020100101000011113201602001220000201002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425717485201122022430236200356411202011009910020100101000011113191602001220000201002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425717486201122022430236200356411202011009910020100101000011113201602001220000201002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200242003515000000061199182520010200102001012972474916955200352003517428031750420010200203002020035641120021109102001010010000000301270127111999520000200102003620036200362003620036
200242003515000000061199182520010200102001012972474916955200352003517428031750420010200203002020035641120021109102001010010000000301270127211999520000200102003620036200362003620036
200242003515000006061199182520010200102001012972474916955200352003517428031750420010200203002020035641120021109102001010010000000001270127111999520000200102003620036200362003620036
200242003515000000061199182520010200102001012972474916955200352003517428031750420010200203002020035641120021109102001010010000000001270127111999520000200102003620036200362003620036
200242003515000000061199182520010200102001012972474916955200352003517428031750420010200203002020035641120021109102001010010000010001270127111999520000200102003620036200362003620036
200242003515000000061199182520010200102001012972474916955200352003517428031750420010200203002020035641120021109102001010010000010001270127111999520000200102003620036200362003620036
200242003515000000061199184820010200102001012972474916955200352003517428031750420010200203002020035641120021109102001010010000000301270127111999520000200102003620036200362003620036
200242003515000000061199182520010200102001012972474916955200352003517428031750420010200203002020035641120021109102001010010000000001270127111999520000200102003620036200362003620036
200242003515000000061199182520010200102001012972474916955200352003517428031750420010200203002020035641120021109102001010010000070001270127111999520000200102003620036200362003620036
2002420035149000000251199182520010200102001012972474916955200352003517428031750420010200203002020035641120021109102001010010000000001270127111999520000200102003620036200362003620036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  bics x0, x1, x2
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020420035150110611993025201002010020112129723314916955020035200351742581748620112202243023620035641120201100991002010010100001111319116112001520000201002003620036200362003620036
2020420035150110611993025201002010020112129723314916955020035200351742581748520112202243038020035641120201100991002010010100001111320116112001520000201002003620036200362003620036
2020420035150110611993025201002010020439129723314916955020035200351742581748520112202243023620035641120201100991002010010100061111319116112005120000201002003620036200362003620036
2020420035150110611993025201002010020112129723314916955020035200351742581748520112202243023620035641120201100991002010010100001111320116112001520000201002003620036200362003620036
20204200351501107261993025201002010020112129723314916955020035200351742581748520112202243023620035641120201100991002010010100001111319116112001520000201002003620036200362003620036
2020420035150110611993025201002010020112129723314916955020035200351742581748620112202243023620035641120201100991002010010100001111319116112001520000201002003620036200362003620036
2020420035150110611993025201002010020112129723314916955020035200351742581748620112202243023620035641120201100991002010010100001111319116112001520000201002003620036200362003620036
2020420035150110611993025201002012220112129723314916955020035200351742571748620112202243023620035641120201100991002010010100031111319116112001520000201002003620036200362003620036
2020420035150110611993025201002010020112129723314916955020035200351742571748620112202243023620035641120201100991002010010100001111319116112001520000201002003620036200362003620036
2020420035150110611993025201002010020112129723314916955020035200351742571748620112202243023620035641120201100991002010010100131111319116112001520000201002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0f18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200242003515000000000006119918252001020010200101297247149169552003520035174283175042001020020300202003564112002110910200101001000000001270127111999520000200102003620036200362003620036
200242003515000000000006119918252001020010200101297247149169552003520035174283175042001020020300202003564112002110910200101001000000001270127111999520000200102003620036200362003620036
200242003515000000000006119918252001020010200101297247149169552003520035174283175042001020020300202003564112002110910200101001000000001270127111999520000200102003620036200362003620036
200242003515000000000006119918252001020010200101297247149169552003520035174283175042001020020300202003564112002110910200101001000000001270227111999520000200102003620036200362003620036
200242003515000000000006119918252001020010200101297247149169552003520035174283175042001020020300202003564112002110910200101001000000001270127111999520000200102003620036200362003620036
200242003515000000000006119918252001020010200101297247149169552003520035174283175042001020020300202003564112002110910200101001000000001270127111999520000200102003620036200362003620036
200242003515000000000008219918252001020010200101297247149169552003520035174283175042001020020300202003564112002110910200101001000000001270127111999520000200102003620036200362003620036
200242003515000000000006119918252001020010200101297247149169552003520035174283175042001020020300202003564112002110910200101001000000001270117111999520000200102003620036200362003620036
200242003515000000000006119918252001020010200101297247149169552003520035174283175042001020020300202003564112002110910200101001000010001287127111999520000200102003620036200362003620036
200242003515000000000006119918252001020010200101297876149169552003520035174393175042001020020300202003564212002110910200101001000000001270127111999520000200102003620036200362003620036

Test 6: throughput

Count: 8

Code:

  bics x0, x8, x9
  bics x1, x8, x9
  bics x2, x8, x9
  bics x3, x8, x9
  bics x4, x8, x9
  bics x5, x8, x9
  bics x6, x8, x9
  bics x7, x8, x9
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020426762200077258010080100801004005001492365526735267351667231669080100802001602002673539118020110099100801001000005110219222673180000801002673626736267362673626736
8020426735200035258010080100801004005001492365526735267351667231669080100802001602002673539118020110099100801001000005110219222673180000801002673626736267362673626736
8020426735200035258010080100801004005000492365526735267351667231669080100802001602002673539118020110099100801001000005110219222673180000801002673626736267362673626736
8020426735200035258010080100801004005000492365526735267351667231669080100802001602002673539118020110099100801001000005110219222673180000801002673626736267362673626736
8020426735200035258010080100801004005001492365526735267351667231669080100802001602002673539118020110099100801001000005110219222673180000801002673626736267362673626736
8020426735200035258010080100801004008450492365526735267351667231669080100802001602002673539118020110099100801001000005110219222673180000801002673626736267362673626736
8020426735200035258010080100801004005000492365526735267351667231669080100802001602002673539118020110099100801001000005110219222673180000801002673626736267362673626736
8020426735200035258010080100801004005000492365526735267351667231669080100802001602002673539118020110099100801001000005110219222673180000801002673626736267362673626736
80204267352000510258010080100801004005001492365526735267351667231669080100802001602002673539118020110099100801001000005110219222673180000801002673626736267362673626736
8020426781201056258010080100801004005000492365526735267351667231669080100802001602002673539118020110099100801001000005110319222673180000801002673626736267362673626736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002426720200352580010800108001040005049236252670526705166653166838001080020160020267053911800211091080010102418485020218222670280000800102670626706267062670626706
8002426705200352580010800108001040005049236252670526763166763166838001080020160020267053911800211091080010100005020218222670280000800102670626706267062670626706
80024267051993546800108001080010400050492362526705267051666531668380010800201600202670539118002110910800101000215020218222670280000800102670626706267062670626706
8002426705200352580010800108001040005049236252670526705166653166838001080020160020267053911800211091080010100005020218222670280000800102670626706267062670626706
8002426705200352580010800108001040005049236252670526705166653166838001080020160020267053911800211091080010100005020218222670280000800102670626706267062670626706
8002426705200352580010800108001040005049236252670526705166653166838001080020160020267053911800211091080010100005020218222670280000800102670626706267482670626706
8002426705199352580010800108001040005049236252670526705166653166838001080020160020267053911800211091080010100005020218222670280000800102670626706267062670626706
8002426705200352580010800108001040005049236252670526705166653166838001080020160020267053911800211091080010100005020218222670280000800102670626706267062670626706
8002426705200352580010800108001040005049236252670526705166653166838001080020160020267053911800211091080010100005020218222670280000800102670626706267062670626706
8002426705200352580010800108001040005049236252670526705166653166838001080020160020267053911800211091080010100005020218222670280000800102670626706267062670626706