Firestorm: LDRSH (register, lsl, 32-bit) measurements

Code:

  ldrsh w0, [x6, x7, lsl #1]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	1	1	0	1	0	0	376	2	18	18	12	25	1000	1000	1000	14838	0	395	394	212	3	247	1000	1000	2000	374	71	1	1	1001	1000	1000	0	1000	39	1000	0	35	1035	6	1	0	39	73	1	16	1	1	386	0	6	2	1000	391	375	390	395	390
1004	389	3	0	0	41	0	0	1	374	2	18	18	12	25	1000	1000	1000	14060	0	389	389	212	3	249	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	1035	0	35	1035	6	1	35	39	73	1	16	1	1	371	6	6	2	1000	375	390	375	375	390
1004	389	2	0	0	0	0	0	1	359	2	0	12	16	25	1000	1000	1000	14838	1	394	389	216	3	252	1000	1000	2000	374	71	1	1	1001	1000	1000	0	1000	39	1039	0	39	1039	6	1	0	43	73	1	16	1	1	371	10	6	4	1000	390	395	375	395	375
1004	389	3	0	0	41	0	0	2	380	0	12	0	16	25	1000	1000	1000	14060	1	398	374	216	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1039	4	35	1039	6	1	39	43	73	1	16	1	1	386	10	6	0	1000	390	395	395	375	378
1004	394	3	0	0	45	1	0	0	374	0	18	12	12	25	1000	1000	1000	14989	1	394	389	197	3	252	1000	1000	2000	394	56	1	1	1001	1000	1000	0	1000	0	1039	0	38	1039	0	1	35	0	73	1	16	1	1	391	0	6	4	1000	375	395	395	395	398
1004	374	2	0	0	45	0	0	0	379	2	18	12	16	25	1000	1000	1000	14989	1	374	394	197	3	232	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1035	0	0	1035	6	1	35	43	73	1	16	1	1	391	4	6	2	1000	375	390	390	390	375
1004	391	3	0	0	45	1	0	0	379	0	12	12	16	25	1000	1000	1000	14060	1	394	394	217	3	252	1000	1000	2000	374	71	1	1	1001	1000	1000	0	1000	0	1035	0	39	1039	0	1	39	0	73	1	16	1	1	371	10	10	0	1000	375	395	395	395	395
1004	374	3	0	0	41	0	0	2	379	2	0	0	0	25	1000	1000	1000	14774	1	394	394	217	3	232	1000	1000	2000	374	71	1	1	1001	1000	1000	0	1000	39	1039	0	39	1039	6	1	35	43	73	1	16	1	1	386	10	0	5	1000	395	395	395	395	395
1004	394	3	0	0	41	0	0	2	374	0	0	12	2	25	1000	1000	1000	14838	1	394	376	216	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1000	1	39	1035	6	1	0	43	73	1	16	1	1	391	10	0	4	1000	395	375	395	375	375
1004	394	2	0	0	45	1	0	2	359	0	12	0	12	25	1000	1000	1000	14989	1	374	394	197	3	232	1000	1000	2000	374	71	1	1	1001	1000	1000	0	1000	39	1000	0	0	1000	6	1	39	43	73	1	16	1	1	391	10	10	2	1000	395	395	395	375	393

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, x7, lsl #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0065

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	3a	3f	43	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70065	525	1	0	0	1	0	0	0	0	147	1	0	70050	1	0	69788	59708	25	40112	30106	10003	30100	10000	616140	3342926	1	49	66985	0	70065	70049	64726	3	64968	40100	30200	10000	60200	20000	70153	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	0	10003	0	1	2	10001	0	2	1	1	1	2610	1	71	1	1	69812	30009	0	10	10	10000	30100	70061	70050	70050	70066	70061
40204	70049	525	1	0	0	1	1	1	0	0	29	0	0	70050	1	1	69796	59724	25	40112	30109	10003	30100	10000	616140	3342158	1	49	66969	0	70057	70065	64757	3	64952	40100	30200	10000	60200	20000	70065	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	1	2	10001	1	1	1	1	1	2610	1	71	1	1	69828	30009	0	10	0	10000	30100	70066	70061	70066	70058	70050
40204	70065	525	1	0	1	1	1	0	0	0	3	1	0	70034	1	1	69796	59708	25	40108	30106	10003	30100	10000	616140	3342926	1	49	66969	0	70065	70049	64758	3	64952	40100	30200	10000	60200	20000	70049	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	0	10002	0	0	2	10001	0	2	1	1	1	2610	1	71	1	1	69828	30006	0	10	10	10000	30100	70066	70050	70066	70066	70066
40204	70065	524	1	0	1	1	0	0	0	0	36	1	0	70050	1	1	69796	59724	25	40108	30109	10003	30100	10000	616140	3342158	1	49	66985	0	70049	70065	64767	3	64968	40100	30200	10000	60200	20000	70065	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	0	10002	0	1	5	10001	1	2	0	1	0	2610	1	71	1	1	69812	30006	10	10	10	10000	30100	70066	70066	70066	70178	70050
40204	70049	524	1	1	1	1	0	0	0	0	36	1	2	70050	1	0	69780	59724	25	40108	30109	10003	30100	10000	616140	3342158	1	49	66969	3	70065	70065	64677	3	64952	40100	30200	10000	60200	20000	70065	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	2	10002	0	1	2	10001	1	2	1	1	0	2610	1	71	1	1	69812	30006	0	0	10	10000	30100	70066	70066	70050	70050	70066
40204	70049	525	1	1	1	0	0	0	0	0	29	0	0	70050	1	0	69796	59708	25	40108	30106	10003	30100	10000	616140	3342158	1	49	66969	0	70065	70065	64755	3	64968	40100	30200	10000	60200	20000	70049	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10003	0	1	2	10001	1	2	0	1	0	2610	1	71	1	1	69914	30006	0	10	10	10000	30100	70066	70061	70058	70061	70058
40204	70065	525	1	0	0	0	0	0	0	0	54	1	0	70050	1	0	69780	59724	25	40108	30109	10003	30100	10000	616140	3342158	1	49	66985	0	70049	70049	64700	3	64952	40100	30200	10000	60200	20000	70065	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	0	10002	0	0	2	10001	0	2	1	1	0	2610	1	71	1	1	69828	30006	10	10	10	10000	30100	70066	70050	70066	70066	70061
40204	70065	524	1	0	1	0	0	0	0	0	39	1	0	70050	1	1	69780	59724	25	40112	30109	10003	30100	10000	616140	3342926	1	49	66969	0	70065	70049	64730	3	64952	40100	30200	10000	60200	20000	70065	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10002	0	1	2	10001	1	2	0	1	1	2610	1	71	1	1	69828	30006	10	10	10	10000	30100	70050	70068	70066	70066	70050
40204	70065	524	1	1	0	0	0	0	0	0	30	0	0	70050	1	0	69796	59724	25	40108	30106	10003	30100	10000	616140	3342926	1	49	66985	0	70049	70049	64772	3	64968	40100	30200	10000	60200	20000	70065	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	3	2	10002	0	2	2	10001	1	2	0	1	1	2610	1	71	1	1	69828	30009	0	10	10	10000	30100	70066	70066	70066	70066	70050
40204	70049	525	1	0	0	1	0	0	0	0	39	0	0	70050	1	1	69796	59708	25	40112	30109	10002	30100	10000	615996	3342926	0	49	66969	0	70065	70065	64727	3	64963	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	1	10002	0	1	2	10001	1	2	1	1	0	2610	1	71	1	1	69828	30006	10	10	10	10000	30100	70066	70066	70050	70050	70066

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	524	1	1	1	0	0	1	0	0	70039	69775	59710	25	40014	30013	10002	30010	10000	617045	3342542	1	49	66971	0	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	0	4	71	4	4	69814	30003	10	0	10	10000	30010	70052	70036	70052	70052	70052
40024	70051	525	0	0	0	0	1	1	1	0	70036	69775	59710	25	40010	30013	10001	30010	10000	616991	3342254	1	49	67029	0	70035	70051	64653	3	64960	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	0	3	71	4	4	69814	30003	10	10	10	10000	30010	70036	70036	70052	70052	70036
40024	70094	525	0	0	0	0	0	1	0	0	70036	69775	59695	25	40010	30013	10001	30010	10000	616991	3342254	1	49	66958	0	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	3	10000	1	1	1	0	2520	0	2	71	2	6	69798	30003	0	10	13	10000	30010	70055	70052	70052	70052	70052
40024	70035	524	0	0	0	0	0	1	1	0	70036	69775	59710	25	40014	30010	10001	30010	10000	616991	3342254	1	49	66971	0	70052	70035	64672	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	1	0	2520	0	4	71	3	5	69814	30003	0	10	10	10000	30010	70052	70052	70052	70090	70052
40024	70051	524	0	0	0	0	0	1	1	0	70020	69778	59710	25	40014	30010	10001	30010	10000	617068	3341470	1	49	66971	0	70051	70035	64669	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	1	0	2520	0	2	71	4	2	69815	30003	10	0	10	10000	30010	70052	70052	70052	70036	70036
40024	70051	525	0	0	0	0	0	0	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	1	49	66971	0	70035	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	1	0	2520	0	2	71	2	4	69814	30003	10	10	10	10000	30010	70036	70052	70052	70052	70036
40024	70051	524	0	0	0	0	0	1	1	0	70036	69775	59695	25	40010	30010	10001	30010	10000	616991	3342254	1	49	66955	0	70051	70051	64653	3	64960	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	0	4	71	3	4	69814	30003	10	0	10	10000	30010	70052	70052	70052	70055	70052
40024	70051	524	0	0	0	0	0	6	1	0	70020	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	1	49	66971	0	70035	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	1	0	2520	0	4	71	4	2	69804	30006	10	10	10	10000	30010	70058	70170	70058	70052	70036
40024	70035	525	0	0	0	0	0	0	0	0	70036	69775	59696	25	40014	30010	10000	30010	10000	617068	3342254	1	49	67006	0	70051	70035	64653	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	1	0	2520	0	4	71	4	2	69817	30000	10	10	10	10000	30010	70052	70052	70036	70052	70052
40024	70051	525	0	0	0	0	0	0	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	617068	3341470	1	49	66971	0	70035	70035	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	0	0	1	0	2520	0	4	71	4	2	69816	30000	10	10	10	10000	30010	70052	70055	70052	70036	70036

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, x7, lsl #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	543	0	0	9	8	1750	1320	1	0	70036	70109	59866	25	40104	30103	10002	30100	10000	616032	3342254	0	49	66971	0	70116	70051	64680	3	64957	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10010	0	0	10000	1	1	0	0	2610	1	71	1	1	69810	30003	6	6	6	10000	30100	70048	70048	70048	70048	70048
40204	70047	525	0	0	0	0	1	0	0	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3342062	0	49	66967	0	70047	70047	64713	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69810	30003	6	6	6	10000	30100	70048	70048	70048	70036	70048
40204	70047	525	0	0	0	0	7	0	0	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3342062	0	49	66967	0	70047	70047	64749	3	64950	40100	30200	10000	60594	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69810	30000	6	6	6	10000	30100	70048	70048	70048	70048	70048
40204	70047	524	0	0	0	0	19	0	0	1	70032	69735	59706	25	40104	30100	10004	30413	10000	616015	3342062	0	49	66967	0	70047	70035	64656	3	65318	40100	30200	10111	60200	20000	70047	35	3	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	1	0	2610	1	71	1	1	69798	30003	6	6	0	10000	30100	70048	70036	70048	70048	70048
40204	70047	525	0	0	0	0	46	0	0	1	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3342062	0	49	66955	3	70047	70035	64690	3	64938	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69810	30003	6	6	6	10000	30100	70048	70048	70048	70159	70048
40204	70047	525	0	0	0	0	13	0	0	1	70032	69735	59695	25	40104	30103	10000	30100	10000	616015	3342062	0	49	66967	0	70047	70047	64675	3	64938	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	3	10000	1	1	0	0	2610	1	71	1	1	69810	30003	0	6	6	10000	30100	70048	70048	70048	70048	70048
40204	70035	524	0	0	0	0	28	0	0	0	70032	69764	59706	25	40104	30103	10000	30100	10000	616015	3342062	0	49	66967	0	70047	70047	64719	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	1	0	0	2610	1	71	1	1	69810	30003	6	6	6	10000	30100	70048	70048	70048	70048	70084
40204	70047	525	1	0	0	0	19	0	0	1	70032	69735	59706	25	40100	30103	10001	30100	10000	616015	3342062	1	49	66967	0	70047	70035	64716	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69798	30003	6	6	6	10000	30100	70036	70048	70048	70048	70048
40204	70047	524	0	0	0	0	28	0	0	1	70032	69735	59706	25	40104	30100	10001	30100	10000	616015	3342062	0	49	66967	0	70047	70047	64717	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	3	0	10000	1	1	0	0	2610	1	71	1	1	69810	30003	6	6	6	10000	30100	70048	70048	70048	70048	70048
40204	70047	524	0	0	0	0	28	0	0	0	70032	69735	59706	25	40104	30100	10001	30100	10000	616015	3342062	0	49	66955	0	70047	70047	64743	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69798	30003	6	6	6	10000	30100	70036	70148	70048	70048	70048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	524	0	0	0	0	0	0	2	0	0	70036	69743	59709	25	40010	30013	10002	30010	10000	617072	3344606	0	1	49	66976	70057	70057	64675	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	1	1	1	1	0	2520	0	0	0	2	71	0	0	0	1	1	69804	30003	9	0	9	10000	30010	70054	70057	70042	70057	70094
40024	70060	525	1	1	1	0	0	0	7	0	0	70041	69779	59705	25	40063	30016	10001	30010	10000	617009	3342494	0	1	49	66961	70053	70041	64674	3	64981	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10001	39	1	4	10000	0	1	1	1	0	0	2520	0	1	0	3	71	0	0	0	1	1	69804	30006	6	0	9	10000	30010	70042	70042	70042	70057	70108
40024	70053	524	1	2	1	0	0	0	2	1	0	70038	69780	59712	25	40018	30013	10002	30010	10000	617036	3342494	0	0	49	66973	70053	70053	64671	3	64978	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10001	45	2	10	10000	1	1	0	1	0	0	2520	0	0	0	1	99	0	0	0	1	1	69819	30012	9	9	9	10000	30010	70051	70058	70411	70054	70110
40024	70050	525	0	0	0	0	0	0	13	0	0	70036	69743	59709	25	40010	30013	10000	30010	10000	616991	3342206	0	1	49	66967	70050	70050	64658	3	64960	40010	30020	10000	60020	20000	70037	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	9	0	0	10000	1	0	0	0	0	0	2520	0	0	0	3	71	0	0	0	1	1	69810	30003	6	6	6	10000	30010	70036	70036	70051	70048	70089
40024	70048	524	0	0	0	0	0	0	0	0	0	70036	69728	59695	25	40014	30010	10001	30010	10000	616991	3341470	0	1	49	66970	70035	70035	64654	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	43	0	0	10001	0	0	0	0	0	0	2520	0	0	0	1	71	0	0	0	1	1	69798	30000	21	9	9	10000	30010	70051	70036	70051	70049	70103
40024	70047	524	0	0	0	0	0	0	0	1	0	70035	69760	59709	25	40014	30013	10004	30302	10000	617077	3342254	0	1	49	66955	70035	70047	64668	3	65202	40010	30020	10000	60020	20000	70035	35	2	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	1	0	0	10000	1	0	1	0	0	0	2520	0	0	1	2	71	1	1	0	2	3	69813	30003	6	0	0	10000	30010	70048	70048	70048	70036	70038
40024	70035	524	0	0	0	0	0	0	6	0	0	70032	69760	59695	25	40014	30010	10001	30010	10000	617068	3341470	0	0	49	66970	70050	70050	64668	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	38	0	0	10000	0	0	1	0	0	0	2520	0	0	0	1	71	1	0	1	3	2	69810	30000	6	0	9	10000	30010	70048	70036	70051	70051	70103
40024	70419	524	0	0	0	0	0	0	0	0	0	70032	69743	59709	25	40010	30013	10001	30010	10204	617077	3342062	0	1	49	66967	70035	70050	64653	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10012	53	0	6	10000	1	0	1	0	0	0	2520	0	0	0	1	71	0	0	0	1	1	69811	30003	30	9	0	10000	30010	70036	70036	70048	70036	70090
40024	70050	525	0	0	0	0	0	0	12	1	0	70032	69760	59706	25	40014	30013	10000	30010	10000	617068	3341470	0	1	49	66972	70035	70050	64668	3	64975	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	43	0	3	10000	1	0	1	0	0	0	2520	0	0	0	1	71	0	0	0	1	1	69798	30003	21	27	9	10000	30010	70051	70036	70036	70052	70094
40024	70052	525	0	0	0	0	0	0	13	0	0	70020	69744	59709	25	40014	30010	10000	30010	10000	617068	3342206	0	0	49	66970	70047	70050	64665	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	0	10000	38	0	9126	10000	0	0	0	0	0	0	2520	0	0	0	1	71	0	0	0	1	1	69813	30000	9	9	6	10000	30010	70048	70048	70048	70048	70114

Test 4: throughput

Count: 8

Code:

  ldrsh w0, [x6, x7, lsl #1]
  ldrsh w0, [x6, x7, lsl #1]
  ldrsh w0, [x6, x7, lsl #1]
  ldrsh w0, [x6, x7, lsl #1]
  ldrsh w0, [x6, x7, lsl #1]
  ldrsh w0, [x6, x7, lsl #1]
  ldrsh w0, [x6, x7, lsl #1]
  ldrsh w0, [x6, x7, lsl #1]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26732	200	1	0	0	0	0	0	147	1	2	26707	2	12	12	16	25	80100	100	80000	100	80014	500	1167303	1	49	23647	26840	26736	16707	6	16684	80116	200	80024	200	160048	26733	81	1	1	80201	100	99	100	80000	100	80000	0	100	80018	20	0	80054	0	0	1	59	80038	6	1	57	42	19	2	1	1	1	5118	0	16	0	0	26729	9	9	2	80000	100	26733	26734	26734	26734	26734
80204	26732	201	1	0	0	0	1	1	63	0	1	26712	2	12	0	16	25	80100	100	80000	100	80014	500	1167303	0	49	23647	26834	26735	16747	6	16684	80116	200	80024	200	160048	26733	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	80057	1	0	1	59	80038	6	1	57	42	0	0	1	1	1	5118	0	16	0	0	26724	10	10	4	80000	100	26708	26728	26723	26728	26728
80204	26727	200	0	0	0	0	0	0	60	0	2	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1167303	0	49	23627	26726	26731	16655	6	16663	80116	200	80024	200	160048	26708	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80035	0	0	0	39	80000	6	1	35	39	0	0	1	1	1	5118	0	16	0	0	26704	0	6	4	80000	100	26723	26723	26728	26723	26723
80204	26727	200	0	0	0	0	0	0	77	0	1	26717	0	18	18	16	25	80100	100	80000	100	80016	500	1167348	0	49	23652	26835	26738	16666	6	16684	80115	200	80024	200	160048	26732	82	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80039	0	0	0	39	80000	6	1	35	39	19	3	1	1	1	5118	0	16	0	0	26729	9	9	2	80000	100	26733	26733	26733	26733	26734
80204	26732	200	1	1	0	0	0	0	95	1	3	26717	2	18	18	14	25	80100	100	80000	100	80014	500	1169563	0	49	23652	26840	26732	16661	6	16679	80115	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	39	80039	6	1	0	43	0	0	1	1	1	5118	0	16	0	0	26724	10	6	2	80000	100	26728	26723	26728	26728	26728
80204	26707	200	0	0	0	0	0	0	72	0	1	26712	0	0	0	16	25	80100	100	80000	100	80016	500	1167303	0	49	23647	26836	26732	16661	6	16674	80115	200	80024	200	160048	26727	128	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80039	0	0	0	39	80039	6	1	35	43	19	0	1	1	1	5118	0	16	0	0	26729	0	9	2	80000	100	26740	26733	26733	26733	26734
80204	26733	201	1	0	0	0	0	0	83	0	3	26717	2	0	18	15	25	80100	100	80000	100	80016	500	1167733	0	49	23652	26827	26718	16742	6	16684	80116	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	19	42	80019	0	0	0	59	80037	6	1	57	42	19	1	1	1	1	5118	0	16	0	0	26729	0	9	2	80000	100	26733	26733	26715	26715	26733
80204	26732	200	1	1	1	0	0	0	101	1	2	26707	2	12	12	16	25	80100	100	80000	100	80015	500	1159814	0	49	23647	26843	26736	16663	6	16679	80114	200	80024	200	160048	26727	72	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80039	0	4	0	39	80039	6	1	39	43	19	0	1	1	1	5118	0	16	0	0	26711	9	9	0	80000	100	26733	26733	26715	26733	26734
80204	26733	200	1	1	1	1	0	0	68	0	2	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1167303	0	49	23647	26840	26737	16667	6	16684	80116	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	19	42	80019	1	0	0	59	80037	6	1	57	42	0	0	1	1	1	5118	0	16	0	0	26724	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	0	84	1	2	26712	2	12	12	16	25	80100	100	80000	100	80016	500	1165856	0	49	23647	26835	26741	16667	6	16685	80115	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	1	100	80019	19	42	80057	1	0	1	59	80000	0	0	19	42	0	0	1	1	1	5118	0	16	0	0	26724	6	6	2	80000	100	26728	26728	26728	26728	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26733	201	1	0	0	0	1	0	0	65	0	3	26700	2	18	18	15	25	80010	10	80000	10	80000	50	1166960	0	1	49	23652	26732	26732	16659	3	16712	80010	20	80000	20	160000	26794	82	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	80058	0	0	0	59	80038	6	1	57	0	19	0	5020	0	0	0	1	16	0	0	0	1	1	26729	9	9	2	80000	10	26733	26716	26734	26734	26733
80024	26732	200	1	0	1	0	1	1	0	65	1	3	26718	2	18	18	16	25	80010	10	80000	10	80000	50	1167599	0	1	49	23634	26732	26715	16677	3	16712	80010	20	80000	20	160000	26733	81	1	1	80021	10	9	10	80000	10	80000	0	10	80152	22	42	80057	1	0	1	59	80038	6	1	19	0	19	2	5020	0	0	0	1	16	0	0	0	1	1	26737	9	9	2	80000	10	26733	26733	26733	26715	26733
80024	26732	200	1	0	1	1	0	0	0	24	1	2	26721	2	18	0	17	25	80010	10	80000	10	80000	50	1167660	0	1	49	23652	26714	26732	16678	3	16713	80010	20	80000	20	160000	26816	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	42	80058	1	0	1	59	80039	0	1	58	42	19	0	5020	0	0	0	1	16	0	0	0	1	1	26729	9	9	2	80000	10	26716	26733	26733	26716	26734
80024	26714	200	1	0	0	0	1	0	0	21	0	2	26699	0	18	18	0	25	80010	10	80000	10	80000	50	1166960	0	1	49	23635	26732	26732	16677	3	16694	80010	20	80000	20	160000	26777	64	1	1	80021	10	9	10	80000	10	80000	0	10	80020	19	0	80057	1	0	1	60	80000	6	1	57	42	19	0	5020	0	0	0	1	16	0	0	0	1	1	26729	9	0	2	80000	10	26716	26734	26733	26715	26716
80024	26732	200	1	0	1	0	0	0	0	65	0	2	26717	2	0	18	0	25	80010	10	80000	10	80000	50	1165304	0	1	49	23652	26715	26732	16677	3	16712	80010	20	80000	20	160000	26758	82	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	0	80057	0	0	0	59	80000	0	0	19	42	19	0	5020	0	0	0	1	16	0	0	0	1	1	26729	9	0	2	80000	10	26733	26716	26733	26733	26734
80024	26733	201	1	0	0	1	1	0	0	65	1	1	26700	2	18	18	16	25	80010	10	80000	10	80000	50	1167298	0	1	49	23652	26732	26715	16678	3	16695	80010	20	80000	20	160000	26813	64	1	1	80021	10	9	10	80000	10	80000	0	10	80019	20	0	80057	0	0	0	242	80038	6	1	57	42	19	1	5020	0	0	0	1	16	0	0	0	1	1	26729	0	9	2	80000	10	26734	26734	26749	26716	26733
80024	26732	200	1	0	1	0	1	0	0	65	0	3	26699	2	18	18	15	25	80010	10	80000	10	80000	50	1172201	0	1	49	23653	26715	26732	16677	3	16712	80010	20	80000	20	160000	26714	81	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	80056	0	0	0	59	80000	0	0	57	42	19	0	5020	0	0	0	1	17	0	0	0	1	1	26712	9	0	0	80000	10	26733	26715	26733	26733	26733
80024	26733	200	1	0	1	1	0	0	0	64	0	3	26717	0	18	18	15	25	80010	10	80000	10	80000	50	1167599	0	1	49	23653	26732	26733	16677	3	16712	80010	20	80000	20	160000	26798	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	21	42	80057	1	0	1	59	80038	6	1	57	42	19	1	5020	0	0	0	1	16	0	0	0	1	1	26730	9	0	2	80000	10	26734	26715	26733	26733	26733
80024	26732	200	1	0	1	1	0	0	0	65	0	3	26718	2	18	18	15	25	80010	10	80000	10	80000	50	1166960	0	1	49	23634	26715	26733	16677	3	16694	80010	20	80000	20	160000	26944	64	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	42	80019	1	0	1	21	80000	6	0	57	0	19	1	5020	0	0	0	1	16	0	0	0	1	1	26729	9	0	2	80000	10	26733	26715	26733	26716	26716
80024	26733	200	1	0	1	0	1	0	0	21	1	2	26699	2	18	18	17	25	80010	10	80000	10	80000	50	1170204	0	1	49	23652	26732	26715	16677	3	16712	80010	20	80000	20	160000	26794	64	1	1	80021	10	9	10	80000	10	80000	0	10	80019	20	0	80058	1	0	1	21	80038	0	0	57	42	19	0	5020	0	0	0	1	16	0	0	0	1	1	26729	9	9	2	80000	10	26716	26733	26733	26716	26715

LDRSH (register, lsl, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations