Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CSDB

Test 1: uops

Code:

  csdb

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)6066696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)st unit uop (a7)acbccfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
4004270282020100027013220251000100010005000126000492394827028270282600032601010001000270282702811100120001000100073116112700010002702927029270292702927029
4004270282030100027013220251000100010005000126000492394827028270282600032601010001000270282702811100120001000100073116112700010002702927029270292702927029
4004270282020100027013220251000100010005000126000492394827028270282600032601010001000270282702811100120001000100073116112700010002702927029270292702927029
4004270282020100027013220251000100010005000126000492394827028270282600032601010001000270282702811100120001000100073116112700010002702927029270292702927029
4004270282020100027013220251000100010005000126000492394827028270282600032601010001000270282702811100120001000100073116112700010002702927029270292702927029
4004270282020100027013220251000100010005000126000492394827028270282600032601010001000270282702811100120001000100073116112700010002702927029270292702927029
4004270282030100027013220251000100010005000126000492394827028270282600032601010001000270282702811100120001000100073116112700010002702927029270292702927029
4004270282020100027013220251000100010005000126000492394827028270282600032601010001000270282702811100120001000100073116112700010002702927029270292702927029
4004270282020100027013220251000100010005000126000492394827028270282600032601010001000270282702811100120001000100073116112700010002702927029270292702927029
4004270282020100027013220251000100010005000126000492394827028270282600032601010001000270282702811100120001000100073116112700010002702927029270292702927029

Test 2: throughput

Code:

  csdb

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 27.0135

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6066696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acbcc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
4020427018720230000000010000270120220124101001001000010010000500500001260099982670550270135270135260099326011710100200100002002701352160951110201100991001001000002000000100001000007103352227023510000100270136270136270136270136270136
40204270135202400000001210000270120220124101001001000010010000500500001260099492670550270135270135260099326011710100200100002002701352160951110201100991001001000002000000100001000007232172227010610000100270136270165270136270136270136
4020427013520230000000010000270120220124101001001000010010000500500001260099492670550270135270135260099326011710100200100002002701352160951110201100991001001000002000000100001000007102172127010610000100270136270136270136270136270136
4020427013520230000000010000270120220124101001001000010010000500500001260099492670553270135270135260099326011710100200100002002701352160951110201100991001001000002000000100001000007102172227010610000100270136270136270136270136270136
4020427013520230000000010000270120220124101001001000010010000500500001260099492670550270135270135260099326011710100200100002002701352160951110201100991001001000002000000100001000007102172227010610000100270165270136270136270136270136
4020427013520240000000010000270120220124101001001000010010000500500001260099492670550270135270135260099326011710100200100002002701352160951110201100991001001000002000000100001000007102172227010610000100270136270136270136270136270136
4020427013520230000000010000270120220124101001001000010010000500500001260099492670550270135270135260099326011710100200100002002701352160951110201100991001001000002000000100001000007462172227010610000100270136270136270136270136270136
4020427013520240000000010000270120220124101001001000010010000500500001260099492670550270135270135260099326011710100200100002002701352160951110201100991001001000002000000100001000007102172227010610000100270136270136270136270136270136
4020427013520230000000010000270120220124101001001000010010000500500001260099492670550270135270135260099326011710100200100002002701352160951110201100991001001000002000000100001000007102172227010610000100270136270136270136270136270136
4020427013520230000000010000270120220124101001001000010010000500500001260099492670550270135270135260120326011710100200100002002701352160951110201100991001001000002000000100001000007102172227010610000100270136270136270136270136270136

1000 unrolls and 10 iterations

Result (median cycles for code): 27.0045

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6066696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fst unit uop (a7)l1d cache writeback (a8)a9acbcc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
400242700612023003391000027003022003410010101000010100005050005126000949266965027004527004526000932600271001020100002027004527004511100211091010102000000100001000000640417232700161000010270046270046270046270046270046
40024270045202300331000027003022003410010101000010100005050000026000949266965027004527004526000932600271001020100002027004527004511100211091010102000000100001000000640317232700161000010270046270046270046270046270046
4002427004520230011551000027003022003410010101000010100005050000026000949266965027004527004526000932600271001020100002027004527004511100211091010102000010100001000001640217332700161000010270046270046270046270046270046
40024270045202200361000027003022003410010101000010100005050000026000949266965027004527007426000932600271001020100002027004527004511100211091010102000000100001000000640317222700161000010270046270046270046270046270046
40024270045202300181000027003022003410010101000210100005050000026000949266965027004527004526000932600271001020100002027004527004511100211091010102000000100001000000640217332700161000010270046270046270046270046270046
40025270045202200151000027003022003410010101000010100005050000126000949266965027004527004526000932600271001020100002027004527004511100211091010102000050100001000000640217332700161000010270046270046270046270046270046
40025270045202300691000027003022003410010101000010100005050000126000949266965027004527004526000932600271001020100002027004527004511100211091010102000000100031000000640217222700161000010270046270046270046270046270046
40024270045202300241000027003022028010013101000210100005050000026000949266965027004527004526000932600271001020100002027004527004511100211091010102000000100001000000640317222700161000010270046270046270046270046270046
4002427004520230001000027003022003410010101000010100005050000026000949266965027004527004526000932600271001020100002027004527004511100211091010102000000100271000000640317332700161000010270046270046270046270046270046
4002427004520230011251000027003022003410010101000010100005050000026000949266965027004527004526000932600271001020100002027004527004511100211091010102000000100031000000640317222700161000010270046270046270046270046270046