Firestorm: STR (32-bit) measurements

Code:

  str w0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	3	1	527	16	16	0	25	1000	1000	1000	22448	542	554	355	3	401	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	3	16	1	1	539	1000	543	543	543	543	543
1004	542	3	3	1	528	16	16	0	25	1000	1000	1000	22448	542	542	355	3	400	1000	1000	2000	542	543	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	2	16	1	2	539	1000	543	543	543	543	543
1004	542	4	3	0	527	16	16	1	25	1000	1000	1000	22448	542	542	367	3	400	1000	1000	2000	543	543	1	1	1001	1000	1000	1000	42	0	1002	5	1002	2	42	73	2	16	1	1	539	1000	543	543	543	544	544
1004	543	4	3	0	527	16	16	0	25	1000	1000	1000	22448	542	542	355	3	412	1000	1000	2000	543	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	2	16	1	1	540	1000	543	544	544	544	544
1004	543	4	3	0	527	16	16	0	25	1000	1000	1000	22448	543	543	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	7	0	528	16	16	1	25	1000	1000	1000	22472	542	543	356	3	400	1000	1000	2000	542	543	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	540	1000	544	544	544	544	543
1004	542	4	3	0	527	16	16	1	25	1000	1000	1000	22472	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	3	0	528	16	16	0	25	1000	1000	1000	22472	542	543	356	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	3	0	527	16	16	1	25	1000	1000	1000	22472	542	543	356	3	400	1000	1000	2000	543	543	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	2	16	1	1	539	1000	543	543	543	543	543
1004	542	4	3	0	527	16	16	0	25	1000	1000	1000	23000	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	2	16	1	1	540	1000	544	543	543	543	544

Count: 8

Code:

  str w0, [x6]
  str w0, [x6]
  str w0, [x6]
  str w0, [x6]
  str w0, [x6]
  str w0, [x6]
  str w0, [x6]
  str w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	l2 tlb miss data (0b)	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40054	300	0	0	0	0	3	1	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839448	1	49	36963	40042	40040	29955	3	30012	80100	200	80000	200	160000	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80002	0	2	80002	0	42	0	0	5110	2	16	2	2	40037	80000	100	40041	40043	40044	40041	40044
80204	40040	300	0	0	0	0	3	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839352	1	49	36963	40042	40043	29953	3	30000	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80002	0	2	80002	0	42	0	0	5110	2	16	2	2	40039	80000	100	40043	40055	40044	40043	40044
80204	40042	300	1	0	0	0	3	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839472	1	49	36963	40042	40043	29953	3	30001	80100	200	80000	200	160000	40043	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80000	0	2	80002	0	42	0	0	5110	2	16	2	2	40039	80000	100	40043	40043	40044	40041	40041
80204	40042	300	0	0	0	0	3	1	0	40028	0	16	0	25	80100	100	80000	100	80000	500	1839352	0	49	36963	40054	40043	29955	3	30001	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80002	0	2	80002	2	42	0	1	5110	2	16	2	2	40040	80000	100	40043	40043	40041	40043	40043
80204	40042	299	0	0	0	0	3	1	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839448	0	49	36962	40042	40042	29955	3	29998	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80002	0	0	80002	2	42	0	0	5110	2	16	2	2	40039	80000	100	40043	40041	40044	40055	40044
80204	40042	300	0	0	0	6	3	0	0	40028	16	16	0	25	80100	100	80000	100	80000	500	1839448	0	49	36960	40040	40042	29953	3	29998	80100	200	80000	200	160000	40042	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80002	0	2	80002	2	42	0	0	5110	2	16	2	2	40039	80000	100	40043	40043	40043	40044	40041
80204	40040	300	0	0	0	0	3	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839352	0	49	36962	40040	40042	29953	3	29998	80100	200	80000	200	160000	40043	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80063	6	0	80002	2	42	0	0	5110	2	16	2	2	40039	80000	100	40043	40043	40043	40043	40043
80204	40040	300	0	0	0	0	0	1	0	40039	16	16	1	25	80100	100	80000	100	80000	500	1839352	0	49	36962	40040	40042	29955	3	30000	80100	200	80000	200	160000	40042	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80002	0	5	80002	2	0	0	0	5110	2	16	2	2	40039	80000	100	40041	40043	40043	40044	40043
80204	40042	299	0	0	0	0	0	0	1	40028	16	16	0	25	80100	100	80000	100	80000	500	1839352	1	49	36962	40040	40042	29953	3	30012	80100	200	80000	200	160000	40054	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80002	0	0	80000	2	42	0	0	5110	2	16	2	2	40039	80000	100	40044	40041	40043	40043	40043
80204	40043	300	0	0	0	0	3	0	0	40027	16	0	29	25	80100	100	80000	100	80000	500	1839352	1	49	36960	40042	40042	29956	3	30000	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80000	0	2	80002	0	42	0	0	5110	2	16	2	2	40037	80000	100	40055	40043	40043	40041	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d0	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	0	0	0	3	0	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	1	49	36962	40040	40042	29977	3	30022	80010	20	80139	20	160000	40040	40051	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80000	0	0	2	80000	2	0	0	5020	0	14	16	0	6	0	12	10	40048	20	80000	10	40043	40043	40043	40043	40041
80024	40042	300	0	0	0	0	0	0	6	0	0	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	1	49	36962	40040	40040	29985	3	30020	80010	20	80000	20	160000	40048	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	0	0	0	80002	2	34	0	5020	0	12	16	0	6	0	8	13	40039	0	80000	10	40043	40051	40043	40041	40043
80024	40049	300	0	0	0	0	0	0	0	0	0	0	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839424	0	0	49	36960	40042	40040	29984	3	30022	80010	20	80000	20	160000	40042	40050	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	0	0	2	80000	0	34	0	5020	0	7	16	0	6	0	9	9	40047	0	80000	10	40041	40043	40041	40041	40041
80024	40040	300	0	0	0	0	0	0	0	1	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	1	49	36962	40042	40042	29977	3	30029	80010	20	80000	20	160000	40048	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80000	1	0	8	80000	0	34	0	5020	0	14	16	0	6	0	9	12	40039	0	80000	10	40041	40043	40051	40041	40043
80024	40042	300	0	0	0	0	0	0	3	0	0	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	1	49	36960	40042	40040	29977	3	30022	80010	20	80000	20	160000	40042	40051	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80000	1	0	2	80000	2	0	0	5020	0	11	16	0	6	0	15	14	40039	0	80000	10	40043	40043	40043	40043	40051
80024	40042	300	0	0	0	0	0	0	3	0	0	0	0	40025	16	0	4	25	80010	10	80000	10	80000	50	1839424	0	0	49	36962	40040	40040	29975	3	30020	80010	20	80000	20	160000	40049	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	0	0	0	80002	0	34	0	5020	0	10	16	0	5	0	10	12	40046	0	80000	10	40041	40043	40051	40043	40043
80024	40042	300	0	0	0	0	0	0	3	0	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	0	49	36962	40040	40042	29977	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	0	0	5	80002	2	34	0	5020	0	7	16	0	6	0	10	10	40039	0	80000	10	40041	40043	40051	40041	40052
80024	40040	300	0	0	0	0	0	0	0	1	0	0	0	40025	0	16	0	25	80010	10	80000	10	80000	50	1839808	0	1	49	36960	40042	40051	29977	3	30022	80010	20	80000	20	160000	40042	40051	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80000	0	0	5	80002	2	0	0	5020	0	12	16	0	5	2	6	10	40039	0	80000	10	40041	40043	40043	40043	40043
80024	40050	300	0	0	0	0	0	0	3	0	0	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839352	1	1	49	36962	40042	40042	29975	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	0	0	2	80002	2	0	0	5020	0	11	16	0	5	0	11	6	40047	0	80000	10	40043	40043	40050	40041	40043
80024	40042	300	0	0	0	0	0	6	3	0	0	0	0	40097	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	1	49	36962	40040	40042	29975	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	0	0	2	80002	0	0	0	5020	0	12	16	0	5	0	10	10	40039	0	80000	10	40051	40041	40051	40043	40043

STR (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations