Firestorm: ANDS (register, 64-bit) measurements

Code:

  ands x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	84	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	159	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	76	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	120	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  ands x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10082	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	189	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4d	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	0	61	9918	10019	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	3	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	10019	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	3	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	562	9918	0	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	0	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	462	9918	0	25	10010	10010	10093	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10085	10036	10036	10036	10036
10024	10035	76	0	156	88	61	9918	0	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	0	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	1	2	0	640	2	27	2	2	9997	10000	10010	10036	10036	10084	10084	10036
10024	10035	75	0	0	0	61	9918	0	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	254	9918	0	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	1	0	0	61	9918	0	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  ands x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	76	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	0	875	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	1	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	895	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	314	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	3	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	84	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	595	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	103	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	3	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10045	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	82	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	105	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	72	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  ands x0, x1, x2
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	126	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	145	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17434	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	1	1	1	1319	16	20012	20000	20100	20071	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	166	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	846	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	5	27	6	5	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	5	27	4	6	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	353	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	5	27	5	5	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	5	27	4	5	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	6	5	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	103	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	5	27	6	5	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	5	5	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	6	27	6	6	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	5	27	6	5	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20080	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	4	5	19995	20000	20010	20036	20036	20036	20036	20036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  ands x0, x1, x2
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	149	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	1	0	1	1	1	1320	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17485	20192	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	966	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	149	143	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	1270	1	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	597	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	631	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	1270	1	27	2	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	61	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	2	1270	1	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	1270	1	27	2	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	61	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	1270	2	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	61	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	61	19918	25	20010	20010	20102	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036

Test 6: throughput

Count: 8

Code:

  ands x0, x8, x9
  ands x1, x8, x9
  ands x2, x8, x9
  ands x3, x8, x9
  ands x4, x8, x9
  ands x5, x8, x9
  ands x6, x8, x9
  ands x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	18	19	1e	1f	3f	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26763	200	0	0	0	0	0	0	0	33	0	29	80115	80115	80121	400590	1	49	23661	26741	26741	16679	8	16689	80121	80232	160264	26741	39	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5120	0	16	1	0	26738	80015	80100	26742	26742	26741	26742	26742
80204	26741	200	0	0	0	0	0	0	0	28	0	29	80115	80115	80121	400590	1	49	23661	26741	26741	16679	8	16689	80121	80232	160264	26741	39	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5120	1	16	1	1	26771	80015	80100	26742	26742	26742	26742	26742
80204	26741	200	0	0	0	0	0	0	0	28	0	53	80115	80181	80121	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	201	0	0	0	0	0	0	0	35	0	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	19	2	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	35	0	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80187	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	2	19	2	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	35	0	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	35	12	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	19	2	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	35	0	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	2	19	1	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	35	0	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	2	19	1	1	26731	80000	80100	26736	26736	26736	26736	26778
80204	26735	200	0	0	0	0	0	0	0	35	0	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	2	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26720	200	0	42	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80075	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	5020	2	18	2	2	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	300	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	5020	2	18	2	2	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	1	27	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	5020	2	18	2	2	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	66	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	5020	2	18	2	2	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	63	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	5020	2	18	2	2	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	15	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	5020	2	18	2	2	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	9	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	5020	2	18	2	2	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	5020	2	18	2	2	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	5020	2	18	2	2	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	5020	2	18	2	2	26702	80000	80010	26706	26706	26706	26706	26706

ANDS (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations