Firestorm: STLXP (64-bit) measurements

Code:

  stlxp w0, x1, x2, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 50.673

Integer unit issues: 0.000

Load/store unit issues: 50.673

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	1f	22	23	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	64	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	38001	284	1	0	1	0	1	0	1998	15	1	0	37986	0	7267	50672	50674	87816	1003588	1	1000	49	34921	38001	38002	13147	5949	24414	87818	91438	274338	38002	38001	1001	1	1001	1000	1000	44981	15	44967	2	44981	0	1	2012	44966	1000	14	1000	1	0	16595	12	2062	6	7	37917	1000	38002	38002	38002	38002	38002
1004	38001	284	1	0	1	0	1	0	1998	14	1	0	37986	0	7267	50673	50672	87816	1003606	1	1000	49	34921	38001	38001	13147	5949	24402	87838	91438	274314	38001	38001	1001	1	1001	1000	1000	44980	14	44967	0	44981	0	0	2012	44967	1000	14	1000	1	0	16595	7	2062	7	7	37917	1000	38002	38002	38002	38002	38002
1004	38001	284	1	1	1	0	1	0	1998	15	1	0	37986	4	7267	50672	50673	87816	1003603	1	1000	49	34921	38001	38001	13147	5937	24402	87816	91438	274314	38001	38001	1001	1	1001	1000	1000	44981	16	44967	1	44981	0	0	2012	44967	1000	14	1000	1	2	16595	8	2062	8	7	37917	1000	38002	38002	38002	38002	38002
1004	38001	284	1	0	0	1	0	0	1998	14	1	0	37986	0	7267	50672	50673	87816	1003603	1	1000	49	34921	38001	38001	13147	5943	24412	87848	91438	274314	38001	38001	1001	1	1001	1000	1000	44982	15	44966	0	44981	0	1	2012	44966	1000	14	1000	1	2	16595	5	2062	5	5	37917	1000	38002	38002	38002	38002	38002
1004	38001	284	1	0	1	0	0	0	2007	14	1	0	37986	0	7267	50672	50673	87816	1003603	1	1000	49	34921	38001	38001	13147	5937	24402	87815	91438	274314	38001	38001	1002	1	1001	1000	1000	44981	16	44967	1	44981	0	1	2012	44966	1000	14	1000	1	2	16595	5	2062	5	7	37917	1000	38002	38002	38002	38002	38002
1004	38001	284	1	0	0	0	1	0	1998	14	1	0	37986	0	7267	50673	50672	87816	1003606	1	1000	49	34921	38001	38001	13147	5941	24403	87838	91438	274314	38001	38001	1001	1	1001	1000	1000	44982	16	44966	1	44980	0	1	2013	44966	1000	14	1000	1	1	16595	7	2054	5	5	37917	1000	38002	38002	38002	38002	38002
1004	38001	284	1	0	0	0	1	0	1998	14	1	0	37986	1	7267	50673	50672	87816	1003606	0	1000	49	34921	38001	38001	13148	5937	24402	87831	91438	274314	38001	38001	1001	1	1001	1000	1000	44982	15	44966	0	44981	0	2	2012	44966	1000	14	1000	1	0	16595	8	2054	7	8	37917	1000	38002	38002	38002	38002	38002
1004	38001	285	1	0	0	0	0	0	1998	14	1	0	37986	4	7267	50673	50672	87816	1003595	0	1000	49	34921	38001	38001	13147	5937	24402	87816	91438	274314	38001	38001	1001	1	1001	1000	1000	44981	15	44967	1	44981	0	0	2013	44966	1000	14	1000	1	1	16595	7	2061	5	5	37925	1000	38002	38002	38002	38002	38002
1004	38001	284	1	0	0	0	1	0	2007	14	1	0	37986	2	7267	50672	50673	87816	1003603	1	1000	49	34921	38001	38001	13147	5937	24402	87828	91438	274314	38001	38001	1001	1	1001	1000	1000	44982	16	44966	1	44981	0	1	2012	44967	1000	14	1000	1	1	16595	7	2062	5	5	37917	1000	38002	38002	38002	38002	38002
1004	38001	284	1	0	1	0	0	0	1998	14	1	0	37986	0	7267	50672	50673	87816	1003603	0	1000	49	34921	38001	38001	13147	5937	24485	87816	91438	274314	38001	38001	1001	1	1001	1000	1000	44982	15	44967	0	44980	0	0	2012	44966	1000	14	1000	1	2	16595	7	2061	7	7	37917	1000	38002	38002	38002	38002	38002

Test 2: throughput

Code:

  stlxp w0, x1, x2, [x6]
  add x6, x6, 16

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 38.9265

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20214	389275	2916	2	0	0	2	0	0	22154	7	2229	1	2256	114	124	389255	2026	4	69280	558524	298939	259605	788783	697541	12746096	11718360	0	10000	0	49	386188	389269	389143	83543	59203	181314	1486310	794517	778684	794521	2336031	389268	44	10001	1	20201	100	99	100	10000	10100	10000	100	232177	7	32705	1561	0	1882	230312	91	0	2513	48	20278	232205	10000	7	1648	1	0	0	0	209453	1	56	10979	33	59	389154	291433	10000	10100	389167	389276	389266	389144	389137
20204	389268	2916	1	0	1	0	0	0	22526	7	2217	1	2360	121	124	389255	2029	4	69279	558520	298937	259595	788798	697508	12745913	11718582	1	10000	0	49	386068	389266	389264	83543	59083	181183	1486278	794508	778672	794497	2335860	389273	44	10001	1	20201	100	99	100	10000	10100	10000	100	232200	8	29586	1572	0	1882	230279	82	1	2522	80	20207	232159	10000	7	1628	1	4	0	0	209453	1	55	10976	53	59	389077	291447	10000	10100	389269	389146	389268	389268	389138
20204	389142	2915	2	2	0	0	0	0	22143	7	2211	1	2352	105	124	389248	2107	4	69279	558524	298944	259593	788818	697499	12746470	11718348	0	10000	0	49	386058	389268	389138	83539	59079	181311	1486304	794517	778612	794489	2335875	389149	44	10001	1	20201	100	99	100	10000	10100	10000	100	232203	21	36916	1553	0	1886	230285	71	0	2481	50	20272	232152	10000	7	1560	1	0	0	0	209453	1	38	10978	53	59	389079	291438	10000	10100	389263	389147	389266	389138	389148
20204	389262	2915	1	0	1	0	0	0	22578	7	2199	1	2296	119	124	389250	2099	3	69279	558541	298936	259593	788817	697500	12745338	11718582	0	10000	0	49	386182	389272	389139	83536	59079	181179	1486312	794605	778687	794494	2336043	389138	44	10001	1	20201	100	99	100	10000	10100	10000	100	232195	7	35576	1550	0	1892	230294	80	1	2517	66	20227	232194	10000	7	1568	1	0	0	0	209453	1	55	10972	53	59	389082	291435	10000	10100	389267	389264	389137	389139	389272
20204	389270	2915	1	1	0	1	0	0	22630	7	2228	1	2312	121	124	389257	2029	3	69279	558538	298937	259590	788790	697497	12745660	11718273	1	10000	0	49	386185	389185	389276	83483	59202	181314	1486319	794520	778703	794505	2335839	389267	44	10001	1	20201	100	99	100	10000	10100	10000	100	232178	8	37657	1644	0	1912	230309	67	0	2497	112	20240	232169	10000	8	1384	1	2	0	0	209453	1	55	10976	53	59	389216	291435	10000	10100	389144	389145	389263	389266	389146
20204	389141	2914	2	0	0	0	0	0	22194	7	2232	1	2320	117	116	389247	2161	3	69402	558528	298939	259588	788790	697508	12745458	11717575	1	10000	0	49	386060	389263	389270	83474	59202	181188	1486315	794505	778756	794521	2335833	389141	44	10001	1	20201	100	99	100	10000	10100	10000	100	232185	15	41243	1631	0	1878	230273	72	2	2494	62	20277	232216	10000	8	1616	1	1	0	0	209455	1	55	10976	53	59	389201	291439	10000	10100	389263	389142	389145	389143	389142
20204	389264	2915	1	0	0	0	0	0	22045	7	2224	1	2336	105	124	389125	2001	2	69402	558532	298965	259595	788817	697502	12745295	11718423	0	10000	0	49	386189	389268	389237	83550	59079	181307	1486295	794505	778616	794485	2336436	389145	44	10001	1	20201	100	99	100	10000	10100	10000	100	232225	15	38591	1596	0	1882	230275	76	1	2484	52	20238	232169	10000	7	1748	1	1	0	0	209455	1	55	10978	53	59	389206	291447	10000	10100	389269	389270	389264	389265	389143
20204	389265	2915	1	1	1	0	4	4	22398	359	2247	1	2344	126	124	389123	2160	3	69404	558526	298943	259586	788813	697499	12745471	11718172	0	10000	0	49	386063	389140	389138	83473	59201	181175	1486306	794510	778624	794505	2335857	389263	44	10001	1	20202	100	99	100	10000	10100	10000	100	232160	7	32812	1574	0	1894	230278	80	0	2527	54	20241	232160	10000	7	1652	1	0	0	0	209453	1	55	10975	53	59	389086	291440	10000	10100	389264	389143	389141	389141	389141
20204	389268	2914	1	1	1	1	0	0	21923	7	2216	1	2336	120	124	389248	2036	3	69460	558536	298938	259591	788810	697501	12745393	11718344	0	10000	0	49	386184	389142	389260	83479	59080	181181	1486313	794510	778689	794517	2336031	389140	187122	10001	1	20201	100	99	100	10000	10100	10000	100	232161	15	36846	1657	0	1891	230305	88	1	2537	54	20250	232185	10000	7	1552	1	1	0	0	209454	1	55	10978	53	59	389094	291434	10000	10100	389271	389269	389142	389274	389260
20204	389143	2915	1	1	1	0	0	0	22000	7	2230	1	2312	133	236	389128	2137	3	69402	558534	298964	259591	788811	697497	12745524	11718206	0	10000	0	49	386184	389140	389138	83534	59206	181182	1486303	794486	778616	794505	2335851	389145	44	10001	1	20201	100	99	100	10000	10100	10000	100	232183	9	36025	1629	9	1880	230304	97	0	2514	54	20233	232201	10000	7	1600	1	0	0	0	209453	1	55	10978	53	59	389078	291438	10000	10100	389262	389262	389151	389138	389140

1000 unrolls and 10 iterations

Result (median cycles for code): 38.9955

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3c	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20034	390191	2921	4	1	0	1	4	22049	7	2261	2	1960	90	0	252	389931	2184	4	70099	550232	290557	259685	760276	697581	12692060	11765276	1	10000	0	49	386881	0	389946	389964	70824	59898	188864	1457882	760831	759234	760831	2277573	390185	44	10001	1	20021	10	9	10	10000	10010	10000	10	232266	24	37171	1627	0	1909	230304	79	0	2506	102	20248	232252	10000	0	1708	0	0	0	200995	45	11095	40	47	390074	289798	10000	10010	390234	389952	389960	390220	389955
20024	389955	2921	4	0	0	1	4	21953	0	2273	2	1344	94	0	236	390215	2164	0	70276	550206	290554	259767	760286	697570	12690655	11765170	1	10000	0	49	386864	0	389944	389944	70827	59909	188939	1457817	760927	759187	760818	2278077	389949	389944	10001	1	20021	10	9	10	10000	10010	10000	10	232260	44	40668	1561	0	1912	230326	85	6	2514	178	20242	232201	10000	0	1760	0	0	0	201060	49	10976	43	45	389883	289802	10000	10010	389955	389940	389954	390193	389950
20024	389958	2923	3	1	4	1	0	22213	7	2400	2	2096	101	0	244	389928	2125	0	70099	550220	290619	259663	760397	697570	12689497	11765087	0	10000	0	49	387114	0	389989	389943	70849	59899	188851	1457831	760821	759181	760823	2277546	389940	390158	10001	1	20021	10	9	10	10000	10010	10000	10	232368	40	42899	1636	0	1925	230225	79	0	2572	104	20204	232223	10000	0	1720	0	4	0	200997	45	10976	41	48	389876	289793	10000	10010	389955	389951	389958	389953	390239
20024	389957	2920	3	0	3	1	3	21885	0	2238	2	2120	89	3	248	389939	2177	0	70100	550204	290549	259661	760250	697571	12690022	11765343	0	10000	0	49	386868	0	389953	389953	70822	59892	188851	1457845	760823	759200	760816	2277594	389949	359593	10001	1	20021	10	9	10	10000	10010	10000	10	232259	16	40030	1572	0	1933	230348	66	3	2481	206	20251	232213	10000	0	1656	0	6	0	201000	48	10977	45	40	389893	289804	10000	10010	389957	389961	389945	389943	389948
20024	389945	2921	3	1	3	0	3	21740	0	2252	2	2128	79	0	620	389942	2120	0	70099	550206	290554	259664	760270	697571	12689735	11764967	0	10000	0	49	386874	0	389941	389943	70832	59890	188861	1457842	760836	759183	760831	2277543	389939	359588	10001	1	20021	10	9	10	10000	10010	10000	10	232307	16	38559	1628	0	1931	230291	69	3	2536	240	20229	232185	10000	0	1500	0	0	0	201003	46	10977	45	40	389895	289799	10000	10010	389951	389953	389959	389949	389946
20024	389941	2921	3	0	0	0	3	21908	0	2258	2	2168	78	0	236	389924	2172	0	70088	550206	290549	259661	760254	697569	12689631	11764923	0	10000	0	49	386879	0	389958	389945	70829	59895	188846	1457833	760834	759177	760826	2277570	389944	389951	10001	1	20021	10	9	10	10000	10010	10000	10	232257	24	38484	1623	0	1940	230316	85	6	2510	126	20263	232199	10000	0	1708	0	0	0	201002	46	10976	41	47	389889	289801	10000	10010	390192	389965	389953	389956	389943
20024	389953	2921	3	1	3	0	0	21873	0	2228	2	2088	92	0	224	389933	2179	0	70099	550214	290570	259674	760268	697571	12689570	11765051	0	10000	0	49	386874	0	389958	389946	70829	59888	188858	1457833	760852	759194	760844	2277567	389988	389954	10001	1	20021	10	9	10	10000	10010	10000	10	232272	24	38086	1632	0	1936	230348	82	0	2476	108	20252	232248	10000	0	1704	0	3	0	200996	47	10970	45	43	389899	289796	10000	10010	389960	389938	389963	389958	389958
20024	389957	2921	3	0	0	1	0	21748	0	2254	2	2168	89	0	248	389943	2059	0	70099	550214	290563	259665	760266	697577	12689543	11765004	1	10000	0	49	386858	0	389945	389958	70826	59901	188856	1457847	760841	759185	760842	2278140	389940	389954	10001	1	20021	10	9	10	10000	10010	10000	10	232230	27	40774	1553	0	1907	230356	88	0	2477	158	20206	232238	10000	0	1728	0	0	0	200997	39	10974	43	44	389878	289798	10000	10010	389957	389945	389943	389953	389938
20024	389957	2921	3	1	3	1	3	21796	0	2250	2	2112	71	0	240	389935	2106	0	70099	550214	290551	259664	760263	697573	12689512	11765081	1	10000	0	49	386869	0	389945	389941	70849	59900	188847	1457811	760810	759193	760855	2277579	389958	389937	10001	1	20021	10	9	10	10000	10010	10000	10	232264	30	37770	1572	0	1927	230190	81	0	2570	164	20206	232232	10000	0	1578	0	0	0	200997	46	10972	37	45	389878	289808	10000	10010	389944	389953	389952	389963	389942
20024	389943	2921	3	1	0	0	0	22007	0	2246	2	2088	75	0	124	390169	2194	0	70088	550220	290551	259665	760487	697572	12689955	11765158	0	10000	0	49	386859	0	389954	389945	70838	59888	188847	1457811	760820	759171	760832	2277552	389953	344710	10001	1	20021	10	9	10	10000	10010	10000	10	232260	16	27615	1607	0	1954	230343	77	0	2513	152	20205	232246	10000	0	1772	0	0	0	200999	46	10978	41	47	389882	289801	10000	10010	389938	389988	389942	389954	389956

Test 3: throughput

Code:

  stlxp w0, x1, x2, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 38.0107

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	22	23	24	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	l1d cache miss st nonspec (c0)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10205	380107	2848	19998	0	0	0	0	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	1	10000	49	377027	0	380107	380109	130446	59947	248989	926433	19100	938544	19100	2815329	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	458866	0	0	458866	0	0	19998	458866	10000	10000	0	4	172682	1	136	11070	129	129	380040	1197	10000	100	380110	380108	380109	380109	380108
10204	380107	2847	20001	1	0	0	180	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	1	10000	49	377027	0	380107	380107	130437	59945	248979	926443	19100	938443	19100	2815329	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	458866	0	0	458866	0	0	19998	458866	10000	10000	0	10	172636	1	130	11072	130	130	380040	1199	10000	100	380108	380108	380776	380109	380108
10204	380108	2847	19998	1	0	0	180	380116	0	70271	529272	10697	518575	10697	915736	54384	10461863	1	10000	49	377027	0	380107	380521	130437	59947	248979	926433	19100	938443	19100	2815329	380108	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	458866	0	0	458866	0	0	20001	458866	10000	10000	0	10	172638	1	130	11071	130	129	380040	1197	10000	100	380108	380109	380108	380108	380108
10204	380107	2848	19998	0	0	0	180	380118	0	70271	529272	10697	518575	10697	915736	54384	10461863	1	10000	49	377028	0	380107	380107	130437	59947	248979	926433	19100	938443	19100	2815329	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	458868	0	0	458866	0	0	20208	458866	10000	10000	0	10	172638	1	130	11072	130	130	380040	1197	10000	100	380108	380108	380108	380108	380108
10204	380107	2847	19998	1	0	0	181	380113	0	70271	529272	10697	518575	10697	915736	54384	10461863	1	10000	49	377028	0	380110	380107	130437	59960	248979	926433	19100	938443	19100	2815329	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	458866	0	0	458866	0	0	19998	458868	10000	10000	0	10	172636	1	130	11069	130	130	380040	1197	10000	100	380108	380108	380108	380108	380108
10204	380107	2847	19998	1	0	0	181	380109	0	70271	529272	10697	518575	10697	915758	54384	10461868	0	10000	49	377027	0	380107	380107	130437	59956	249002	926435	19100	938443	19100	2815329	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	458866	0	0	458866	0	4	20004	458866	10000	10000	0	10	172639	1	130	11059	129	129	380138	1197	10000	100	380110	380108	380108	380108	380108
10204	380107	2847	19998	0	1	0	181	380106	0	70271	529272	10697	518587	10697	915736	54384	10461863	1	10000	49	377027	0	380109	380108	130437	59951	248979	926433	19100	938443	19100	2815329	380108	380108	10001	1	10201	100	99	100	10000	100	10000	100	458866	459168	0	0	458866	0	0	19998	458866	10000	10000	0	10	172638	1	130	11070	130	43	380054	1197	10000	100	380108	380109	380108	380108	380108
10204	380107	2847	20010	0	0	0	181	380111	0	70271	529272	10697	518575	10697	915736	54384	10461863	1	10000	49	377037	0	380107	380107	130440	59947	248987	926433	19100	938443	19100	2815329	380109	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	458866	0	0	458866	0	0	19998	458866	10000	10000	0	10	172640	1	129	11062	130	130	380040	1197	10000	100	380108	380108	380108	380108	380108
10204	380107	2847	19998	0	1	0	181	380101	0	70271	529272	10697	518575	10697	915736	54384	10461863	0	10000	49	377027	0	380107	380109	130437	59950	248989	926433	19102	938507	19100	2815329	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	458866	0	0	458866	1	0	19998	458866	10000	10000	0	10	172638	1	130	11072	130	130	380040	1197	10000	100	380108	380109	380110	380108	380108
10204	380107	2847	19998	0	1	0	180	380092	0	70271	529272	10697	518575	10697	915766	54384	10461863	1	10000	98	377034	0	380107	380107	130437	59947	248987	926433	19100	938443	19100	2815329	380107	380108	10001	1	10201	100	99	100	10000	100	10000	100	458866	458866	0	0	458866	0	0	19998	458866	10000	10000	0	10	172636	1	130	11062	130	41	380042	1197	10000	100	380108	380108	380108	380108	380108

1000 unrolls and 10 iterations

Result (median cycles for code): 38.0011

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10025	380011	2847	0	0	0	0	0	0	19998	0	0	379996	0	70268	519732	1067	518664	1067	915805	5424	10470486	0	10000	49	376931	0	380011	380011	138348	59939	249327	916872	1910	953892	1910	2861661	380011	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169646	56	11080	43	41	379944	117	0	10000	10	380012	380012	380012	380014	380012
10024	380013	2846	0	0	0	0	0	0	20172	0	1	379996	0	70267	519732	1067	518665	1067	915805	5424	10470399	0	10000	49	376931	0	380011	380011	138348	59947	249337	916872	1910	953892	1910	2861670	380012	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458962	10000	0	10000	0	0	0	169646	48	11078	40	40	379944	117	0	10000	10	380012	380012	380014	380012	380012
10024	380012	2846	0	0	0	0	0	0	19998	0	0	379996	0	70267	519732	1067	518665	1067	915805	5424	10470336	0	10000	49	376931	0	380011	380013	138348	59947	249327	916872	1910	953892	1910	2861667	380021	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169646	62	11058	41	41	379971	117	0	10000	10	380012	380012	380013	380012	380012
10024	380013	2846	0	0	0	0	0	0	19998	0	0	379996	0	70267	519732	1067	518665	1067	915805	5424	10470394	0	10000	49	376931	0	380013	380011	138348	59939	249327	916872	1910	953892	1910	2861673	380011	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	4	169646	57	11068	41	41	379944	117	0	10000	10	380013	380012	380012	380012	380013
10024	380011	2846	0	0	0	0	0	0	19998	0	0	379996	0	70267	519732	1067	518665	1067	915881	5424	10470394	1	10000	49	376932	0	380012	380011	138366	59939	249330	916872	1910	953892	1910	2861865	380011	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169646	48	11080	42	42	379944	117	0	10000	10	380012	380012	380012	380012	380012
10024	380012	2847	0	0	0	0	0	0	19998	0	0	379996	0	70267	519731	1067	518665	1067	915805	5424	10470394	0	10000	49	370856	0	380011	380011	138348	59943	249337	916872	1910	953892	1910	2861985	380011	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169650	50	11079	40	41	379944	117	0	10000	10	380035	380014	380023	380012	380012
10024	380011	2847	0	0	0	0	0	0	19998	0	0	379996	0	70267	519732	1067	518665	1067	915805	5424	10470394	1	10000	49	376931	0	380011	380012	138348	59947	249327	916872	1910	953892	1910	2861937	380011	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169648	58	11083	41	40	379944	117	0	10000	10	380012	380035	380027	380012	380012
10024	380011	2846	0	0	0	0	0	0	19998	0	0	379997	0	70267	519732	1067	518665	1067	915805	5424	10470995	1	10000	49	376931	0	380011	380011	138348	59939	249327	916872	1914	956485	1914	2862246	380013	380011	10001	1	10021	10	9	10	10000	10	10000	10	458955	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169646	51	11070	42	42	379944	117	0	10000	10	380012	380012	380012	380012	380012
10024	380011	2846	0	0	0	0	0	0	19998	0	1	379996	0	70267	519732	2255	518663	1067	915805	5424	10470394	0	10000	49	376931	0	380011	380011	138348	59941	249330	916872	1910	953900	1910	2861673	380011	380011	10002	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458958	63	0	19998	458955	10000	0	10000	0	0	0	169646	54	11078	40	40	379944	117	0	10000	10	380012	380012	380012	380036	380012
10024	380011	2846	0	0	0	0	0	0	19998	0	0	379997	0	70269	519735	1067	518664	1067	915804	5424	10470394	0	10000	49	376933	0	380011	380011	138348	59945	249327	916872	1910	953892	1910	2861676	380012	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169646	63	11078	41	41	379944	117	0	10000	10	380012	380014	380012	380012	380013

STLXP (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations