Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
str x0, [x6], #8
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int store (96) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 1005 | 1040 | 8 | 0 | 0 | 0 | 0 | 0 | 7 | 36 | 1 | 0 | 0 | 0 | 1025 | 16 | 0 | 0 | 0 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1022 | 0 | 56 | 5 | 14 | 1000 | 0 | 0 | 14 | 12 | 0 | 1014 | 7 | 56 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1099 |
| 1004 | 1040 | 8 | 1 | 0 | 0 | 0 | 6 | 12 | 14 | 1 | 0 | 5 | 4 | 1025 | 16 | 2 | 0 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1022 | 8 | 56 | 4 | 33 | 1007 | 0 | 0 | 20 | 2 | 7 | 1008 | 7 | 32 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 1 | 1 | 0 | 10 | 26 | 1 | 0 | 6 | 4 | 1025 | 12 | 3 | 17 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1036 | 7 | 48 | 1 | 16 | 1008 | 0 | 1 | 14 | 24 | 7 | 1014 | 7 | 48 | 7 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 0 | 1 | 1 | 0 | 10 | 16 | 0 | 0 | 5 | 0 | 1025 | 6 | 1 | 0 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1022 | 7 | 46 | 5 | 22 | 1012 | 2 | 0 | 26 | 14 | 7 | 1000 | 7 | 52 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 6 | 0 | 1025 | 10 | 0 | 3 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50746 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1021 | 8 | 40 | 1 | 15 | 1012 | 0 | 1 | 0 | 12 | 7 | 1012 | 7 | 48 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 0 | 0 | 1 | 0 | 10 | 12 | 1 | 0 | 1 | 12 | 1025 | 10 | 1 | 2 | 4 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1025 | 7 | 40 | 1 | 22 | 1007 | 0 | 1 | 12 | 12 | 7 | 1022 | 8 | 52 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 0 | 1 | 0 | 0 | 10 | 20 | 0 | 0 | 7 | 0 | 1025 | 10 | 3 | 1 | 4 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1018 | 7 | 72 | 2 | 16 | 1008 | 3 | 1 | 0 | 0 | 7 | 1000 | 7 | 34 | 7 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 0 | 0 | 1 | 0 | 10 | 0 | 0 | 0 | 8 | 0 | 1025 | 8 | 3 | 1 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1031 | 8 | 40 | 3 | 12 | 1008 | 1 | 0 | 19 | 6 | 7 | 1028 | 7 | 40 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 1 | 0 | 1 | 0 | 10 | 14 | 2 | 0 | 7 | 0 | 1025 | 8 | 3 | 2 | 4 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1022 | 8 | 56 | 5 | 20 | 1007 | 1 | 2 | 20 | 6 | 7 | 1020 | 8 | 48 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1091 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 1 | 1 | 1 | 0 | 10 | 14 | 1 | 0 | 5 | 0 | 1025 | 8 | 3 | 3 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1022 | 7 | 48 | 5 | 12 | 1007 | 0 | 1 | 14 | 2 | 7 | 1018 | 7 | 48 | 7 | 1 | 73 | 1 | 25 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
Code:
str x0, [x6], #8
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 44 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10209 | 10040 | 75 | 0 | 2274 | 91 | 828 | 1 | 696 | 69 | 120 | 10025 | 804 | 0 | 56 | 56 | 32 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522171 | 468824 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10904 | 1295 | 381 | 0 | 694 | 10250 | 247 | 902 | 40 | 833 | 10916 | 9 | 1164 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 2 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2217 | 87 | 826 | 1 | 768 | 72 | 120 | 10025 | 797 | 0 | 100 | 73 | 26 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522067 | 468824 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10882 | 1299 | 357 | 0 | 678 | 10249 | 272 | 906 | 36 | 901 | 10948 | 16 | 1159 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2178 | 82 | 788 | 1 | 720 | 82 | 96 | 10025 | 814 | 0 | 57 | 52 | 36 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522171 | 468824 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10886 | 1261 | 397 | 0 | 671 | 10236 | 258 | 880 | 32 | 720 | 10924 | 11 | 1145 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2151 | 78 | 830 | 1 | 816 | 72 | 96 | 10025 | 826 | 0 | 64 | 65 | 45 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522203 | 468824 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10195 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10906 | 1253 | 367 | 0 | 689 | 10256 | 254 | 882 | 42 | 830 | 10921 | 10 | 1191 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 7 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2043 | 98 | 832 | 1 | 720 | 75 | 120 | 10025 | 814 | 0 | 89 | 107 | 24 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522163 | 468824 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10934 | 1351 | 383 | 0 | 681 | 10244 | 275 | 920 | 32 | 843 | 10909 | 15 | 1191 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2190 | 95 | 835 | 1 | 704 | 86 | 116 | 10025 | 791 | 0 | 80 | 75 | 28 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522115 | 468824 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10938 | 1320 | 375 | 2 | 663 | 10236 | 279 | 936 | 40 | 838 | 10911 | 5 | 1164 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 4 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2379 | 84 | 834 | 1 | 600 | 70 | 100 | 10025 | 794 | 0 | 77 | 76 | 27 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522171 | 468824 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10936 | 1355 | 379 | 6 | 678 | 10255 | 297 | 934 | 40 | 778 | 10922 | 15 | 1291 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2142 | 74 | 795 | 1 | 696 | 74 | 120 | 10025 | 770 | 0 | 63 | 101 | 19 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522187 | 468824 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10886 | 1271 | 381 | 0 | 668 | 10249 | 269 | 894 | 38 | 835 | 10937 | 16 | 1214 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 4 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2094 | 91 | 832 | 1 | 704 | 70 | 120 | 10025 | 781 | 0 | 85 | 107 | 28 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522203 | 468824 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10878 | 1298 | 367 | 0 | 664 | 10244 | 244 | 886 | 32 | 792 | 10935 | 13 | 1217 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2115 | 90 | 803 | 1 | 752 | 78 | 100 | 10025 | 795 | 0 | 113 | 67 | 38 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522203 | 468824 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10930 | 1354 | 397 | 0 | 670 | 10244 | 249 | 932 | 32 | 850 | 10905 | 16 | 1298 | 7 | 1 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 4 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10029 | 10040 | 75 | 1953 | 87 | 825 | 2 | 560 | 87 | 0 | 272 | 10025 | 834 | 108 | 154 | 21 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521113 | 468824 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10894 | 1390 | 375 | 0 | 658 | 10231 | 286 | 878 | 90 | 819 | 10933 | 13 | 1316 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1821 | 86 | 809 | 2 | 592 | 92 | 1 | 276 | 10025 | 797 | 113 | 87 | 37 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521115 | 468824 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10944 | 1197 | 369 | 0 | 658 | 10251 | 256 | 864 | 58 | 787 | 10913 | 18 | 1218 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 2 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 76 | 2118 | 96 | 840 | 2 | 576 | 69 | 0 | 276 | 10025 | 796 | 67 | 102 | 26 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521121 | 468824 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10938 | 1312 | 386 | 0 | 707 | 10237 | 265 | 886 | 64 | 877 | 10943 | 17 | 1248 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2037 | 98 | 840 | 2 | 568 | 98 | 0 | 248 | 10025 | 829 | 139 | 77 | 40 | 25 | 20010 | 10010 | 10052 | 10010 | 10000 | 521123 | 468824 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10876 | 1403 | 389 | 0 | 643 | 10255 | 262 | 910 | 64 | 871 | 10914 | 20 | 1249 | 640 | 2 | 16 | 3 | 3 | 10037 | 10000 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2103 | 95 | 840 | 2 | 576 | 83 | 0 | 240 | 10025 | 780 | 122 | 96 | 20 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521113 | 468824 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10944 | 1468 | 392 | 0 | 669 | 10236 | 274 | 910 | 80 | 805 | 10929 | 21 | 1176 | 640 | 3 | 16 | 2 | 3 | 10037 | 10000 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1965 | 99 | 839 | 2 | 544 | 77 | 1 | 244 | 10025 | 775 | 127 | 122 | 20 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521129 | 468824 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10874 | 1378 | 383 | 0 | 710 | 10248 | 270 | 910 | 118 | 847 | 10932 | 16 | 1162 | 640 | 3 | 16 | 2 | 2 | 10037 | 10000 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 76 | 2070 | 85 | 849 | 2 | 544 | 96 | 0 | 216 | 10025 | 761 | 108 | 79 | 26 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521113 | 468824 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10918 | 1479 | 363 | 0 | 664 | 10243 | 255 | 908 | 86 | 801 | 10891 | 13 | 1188 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2019 | 86 | 843 | 2 | 608 | 76 | 0 | 228 | 10025 | 833 | 129 | 116 | 28 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521137 | 468824 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10896 | 1355 | 378 | 0 | 664 | 10260 | 262 | 932 | 64 | 930 | 10933 | 21 | 1208 | 640 | 2 | 16 | 3 | 2 | 10037 | 10000 | 2 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2121 | 95 | 811 | 2 | 544 | 85 | 0 | 268 | 10025 | 786 | 131 | 145 | 25 | 25 | 20117 | 10010 | 10000 | 10010 | 10000 | 521075 | 468824 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10924 | 1274 | 398 | 0 | 671 | 10242 | 272 | 850 | 62 | 767 | 10943 | 22 | 1128 | 640 | 3 | 16 | 2 | 2 | 10037 | 10000 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2262 | 91 | 822 | 2 | 568 | 88 | 1 | 228 | 10025 | 851 | 131 | 109 | 30 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521145 | 468824 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10888 | 1320 | 392 | 0 | 683 | 10225 | 281 | 934 | 84 | 817 | 10938 | 22 | 1205 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
Count: 8
Code:
str x0, [x6], #8 str x0, [x7], #8 str x0, [x8], #8 str x0, [x9], #8 str x0, [x10], #8 str x0, [x11], #8 str x0, [x12], #8 str x0, [x13], #8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5104
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 19 | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c3 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80209 | 40626 | 307 | 1 | 0 | 0 | 0 | 0 | 1860 | 914 | 831 | 1 | 720 | 147 | 112 | 40799 | 783 | 1732 | 1848 | 183 | 25 | 160892 | 80701 | 80025 | 80100 | 80000 | 403278 | 1877468 | 0 | 455 | 49 | 37734 | 40889 | 40780 | 30694 | 3 | 30854 | 160100 | 200 | 80000 | 200 | 160000 | 40871 | 85 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80999 | 16 | 4419 | 460 | 8 | 901 | 80618 | 279 | 1 | 917 | 32 | 1710 | 81486 | 508 | 4220 | 14 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40826 | 81055 | 80000 | 80100 | 40921 | 40925 | 40844 | 40846 | 40967 |
| 80204 | 40830 | 305 | 1 | 0 | 0 | 0 | 0 | 1890 | 855 | 833 | 1 | 728 | 128 | 112 | 40738 | 807 | 2027 | 1855 | 152 | 25 | 160484 | 85835 | 80000 | 80100 | 80000 | 426381 | 1880564 | 0 | 356 | 49 | 37690 | 40839 | 40800 | 30701 | 3 | 30945 | 160100 | 200 | 80000 | 200 | 160000 | 40929 | 87 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80995 | 14 | 4971 | 480 | 5 | 873 | 80553 | 283 | 1 | 893 | 38 | 1656 | 81467 | 543 | 4772 | 14 | 1 | 0 | 0 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 40836 | 80930 | 80000 | 80100 | 40822 | 40918 | 40912 | 40881 | 40888 |
| 80204 | 40830 | 306 | 0 | 0 | 0 | 0 | 0 | 1926 | 855 | 827 | 1 | 744 | 119 | 100 | 40730 | 832 | 1897 | 2026 | 163 | 25 | 165265 | 82845 | 80000 | 80100 | 80000 | 402568 | 1877813 | 0 | 318 | 49 | 37816 | 40848 | 40891 | 30672 | 3 | 30812 | 160100 | 200 | 80000 | 200 | 160000 | 40860 | 87 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 81039 | 16 | 4441 | 479 | 4 | 919 | 80555 | 269 | 0 | 919 | 28 | 1614 | 81470 | 511 | 4076 | 14 | 1 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40921 | 83417 | 80000 | 80100 | 40912 | 40839 | 40867 | 40768 | 40919 |
| 80204 | 40844 | 305 | 1 | 0 | 1 | 0 | 0 | 1923 | 895 | 795 | 1 | 744 | 122 | 120 | 40744 | 805 | 1792 | 1812 | 255 | 25 | 160793 | 80774 | 80000 | 80100 | 80000 | 402238 | 1872453 | 1 | 395 | 49 | 37872 | 40729 | 40856 | 30731 | 3 | 30790 | 160100 | 200 | 80000 | 200 | 160000 | 40832 | 87 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 81013 | 15 | 4946 | 489 | 1 | 903 | 80587 | 273 | 0 | 941 | 74 | 1698 | 81503 | 556 | 4949 | 14 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40773 | 80301 | 80000 | 80100 | 40870 | 40792 | 40749 | 40941 | 40833 |
| 80204 | 40791 | 306 | 1 | 0 | 1 | 0 | 0 | 1914 | 911 | 805 | 1 | 704 | 128 | 228 | 40751 | 786 | 2117 | 2028 | 270 | 25 | 160964 | 84685 | 80000 | 80100 | 80000 | 401632 | 1878466 | 1 | 1354 | 49 | 37669 | 40795 | 40816 | 30674 | 3 | 30888 | 160100 | 200 | 80000 | 200 | 160000 | 41024 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 81031 | 0 | 5135 | 464 | 11 | 908 | 80598 | 301 | 0 | 927 | 90 | 1786 | 81472 | 542 | 4339 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 40808 | 81139 | 80000 | 80100 | 40828 | 40847 | 40831 | 40910 | 40844 |
| 80204 | 40864 | 306 | 0 | 0 | 0 | 0 | 0 | 2055 | 789 | 799 | 1 | 752 | 121 | 160 | 40747 | 788 | 1922 | 1713 | 175 | 25 | 160675 | 81337 | 80009 | 80100 | 80000 | 401849 | 1882456 | 0 | 265 | 49 | 37858 | 40723 | 40804 | 30715 | 3 | 30842 | 160100 | 200 | 80000 | 200 | 160000 | 40767 | 85 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80993 | 0 | 4216 | 509 | 9 | 921 | 80507 | 269 | 0 | 888 | 36 | 1752 | 81458 | 525 | 4346 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 40838 | 88841 | 80000 | 80100 | 40830 | 40697 | 40837 | 40809 | 40904 |
| 80204 | 40850 | 305 | 0 | 0 | 0 | 0 | 0 | 1938 | 997 | 819 | 1 | 712 | 126 | 120 | 40733 | 794 | 1948 | 1895 | 255 | 25 | 160731 | 80904 | 80001 | 80100 | 80000 | 404153 | 1874800 | 1 | 266 | 49 | 37884 | 40907 | 40731 | 30741 | 3 | 30852 | 160100 | 200 | 80000 | 200 | 160000 | 40813 | 76 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 81025 | 13 | 4567 | 500 | 7 | 947 | 80541 | 292 | 0 | 929 | 66 | 1661 | 81488 | 565 | 4602 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 40714 | 80505 | 80000 | 80100 | 40800 | 40945 | 40796 | 40896 | 40821 |
| 80204 | 40760 | 306 | 1 | 1 | 1 | 1 | 0 | 1812 | 798 | 820 | 1 | 712 | 115 | 108 | 40788 | 810 | 1942 | 1994 | 175 | 25 | 161045 | 80668 | 80030 | 80100 | 80000 | 402297 | 1875623 | 1 | 213 | 49 | 37730 | 40834 | 40743 | 30753 | 3 | 30727 | 160100 | 200 | 80000 | 200 | 160000 | 40915 | 87 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80978 | 30 | 4779 | 492 | 14 | 898 | 80617 | 262 | 1 | 937 | 26 | 1512 | 81460 | 531 | 4572 | 14 | 0 | 271 | 0 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 40772 | 80612 | 80000 | 80100 | 40827 | 40877 | 40839 | 40793 | 40842 |
| 80204 | 40829 | 307 | 1 | 0 | 1 | 1 | 0 | 1914 | 844 | 877 | 1 | 744 | 127 | 108 | 40937 | 771 | 1829 | 1865 | 203 | 25 | 166454 | 84572 | 80000 | 80100 | 80000 | 404246 | 1875860 | 1 | 69 | 49 | 37687 | 40882 | 40835 | 30763 | 3 | 30806 | 160100 | 200 | 80000 | 200 | 160000 | 40871 | 76 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80990 | 16 | 4795 | 514 | 4 | 895 | 80576 | 288 | 0 | 932 | 124 | 1700 | 81594 | 576 | 4697 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 40934 | 80937 | 80000 | 80100 | 40890 | 40814 | 40705 | 40894 | 40913 |
| 80204 | 40863 | 306 | 0 | 0 | 0 | 0 | 0 | 1908 | 866 | 810 | 1 | 784 | 120 | 116 | 40895 | 779 | 2039 | 1916 | 155 | 25 | 162619 | 80754 | 80000 | 80100 | 80000 | 402405 | 1877296 | 1 | 402 | 49 | 37748 | 40773 | 40792 | 30625 | 3 | 30817 | 160100 | 200 | 80000 | 200 | 160000 | 40832 | 76 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80893 | 0 | 4342 | 461 | 2 | 902 | 80556 | 271 | 0 | 885 | 74 | 1716 | 81493 | 577 | 4239 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 40735 | 80990 | 80000 | 80100 | 40800 | 40857 | 40805 | 40873 | 40861 |
Result (median cycles for code divided by count): 0.5102
| retire uop (01) | cycle (02) | 03 | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6a | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | cf | d2 | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80029 | 40779 | 307 | 1848 | 887 | 795 | 1 | 800 | 133 | 144 | 40747 | 770 | 1647 | 1695 | 144 | 25 | 167570 | 80628 | 80002 | 80010 | 80000 | 401416 | 1878952 | 0 | 154 | 49 | 37712 | 0 | 40783 | 40851 | 30891 | 3 | 30884 | 160010 | 20 | 80000 | 20 | 160000 | 40809 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80869 | 3495 | 456 | 4 | 861 | 80531 | 268 | 861 | 32 | 1697 | 81343 | 504 | 3903 | 5020 | 0 | 6 | 5 | 16 | 5 | 6 | 40807 | 83307 | 80000 | 80010 | 40827 | 40716 | 40904 | 40741 | 40731 |
| 80024 | 40829 | 305 | 1776 | 843 | 760 | 1 | 680 | 101 | 116 | 40760 | 800 | 1682 | 1677 | 129 | 25 | 160419 | 81937 | 80000 | 80010 | 80000 | 420095 | 1877080 | 0 | 274 | 49 | 37748 | 0 | 40815 | 40821 | 30683 | 3 | 30786 | 160010 | 20 | 80000 | 20 | 160000 | 40786 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80838 | 4600 | 473 | 4 | 838 | 80558 | 257 | 874 | 34 | 1642 | 81457 | 549 | 3692 | 5020 | 0 | 6 | 5 | 17 | 5 | 6 | 40807 | 80772 | 80000 | 80010 | 40779 | 40814 | 40810 | 40788 | 40862 |
| 80024 | 40873 | 306 | 1914 | 839 | 793 | 1 | 640 | 105 | 140 | 40765 | 743 | 1842 | 1701 | 169 | 25 | 160556 | 80588 | 80000 | 80010 | 80000 | 401535 | 1870504 | 0 | 188 | 98 | 37756 | 0 | 40812 | 40927 | 30710 | 3 | 30793 | 160010 | 20 | 80000 | 20 | 160000 | 40837 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80907 | 4529 | 524 | 12 | 853 | 80564 | 288 | 892 | 42 | 1521 | 81408 | 508 | 4455 | 5020 | 0 | 6 | 5 | 16 | 6 | 6 | 40823 | 82566 | 80000 | 80010 | 40898 | 40894 | 40937 | 40788 | 40798 |
| 80024 | 40831 | 306 | 1710 | 805 | 763 | 1 | 656 | 99 | 136 | 40824 | 768 | 1952 | 1758 | 153 | 25 | 160473 | 80581 | 80000 | 80010 | 80000 | 418675 | 1874800 | 0 | 4387 | 49 | 37708 | 0 | 40764 | 40747 | 30742 | 3 | 30743 | 160010 | 20 | 80000 | 20 | 160000 | 40853 | 82 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80835 | 3738 | 442 | 7 | 862 | 80495 | 252 | 809 | 40 | 1519 | 81459 | 495 | 3735 | 5020 | 0 | 6 | 5 | 16 | 6 | 6 | 40761 | 86617 | 80000 | 80010 | 40826 | 40795 | 40743 | 40812 | 40803 |
| 80024 | 40719 | 305 | 1839 | 726 | 758 | 1 | 784 | 94 | 128 | 40854 | 758 | 1744 | 1628 | 143 | 25 | 160506 | 80415 | 80051 | 80010 | 80000 | 423909 | 1877344 | 1 | 257 | 49 | 37782 | 0 | 40806 | 40787 | 30809 | 3 | 30862 | 160010 | 20 | 80000 | 20 | 160000 | 40829 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80871 | 4317 | 456 | 7 | 842 | 80497 | 286 | 869 | 36 | 1614 | 81324 | 566 | 3666 | 5020 | 0 | 6 | 5 | 16 | 6 | 6 | 40769 | 80413 | 80000 | 80010 | 40798 | 40864 | 40828 | 40863 | 40797 |
| 80024 | 40875 | 305 | 1563 | 876 | 758 | 1 | 704 | 97 | 124 | 40781 | 735 | 1717 | 1936 | 130 | 25 | 163405 | 80560 | 80000 | 80010 | 80000 | 402640 | 1878832 | 0 | 280 | 49 | 37731 | 0 | 40856 | 40871 | 30765 | 3 | 30700 | 160010 | 20 | 80000 | 20 | 160000 | 40817 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80847 | 4365 | 458 | 12 | 853 | 80610 | 261 | 914 | 36 | 1643 | 81445 | 452 | 3525 | 5020 | 0 | 6 | 5 | 16 | 5 | 5 | 40893 | 80324 | 80000 | 80010 | 40732 | 40746 | 40813 | 40813 | 40877 |
| 80024 | 40853 | 305 | 1899 | 853 | 786 | 1 | 712 | 109 | 144 | 40666 | 772 | 1577 | 1663 | 81 | 25 | 160525 | 80492 | 80072 | 80010 | 80000 | 401652 | 1874464 | 0 | 281 | 49 | 37723 | 0 | 40819 | 40844 | 30771 | 3 | 30861 | 160010 | 20 | 80000 | 20 | 160000 | 40855 | 82 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80835 | 4089 | 451 | 6 | 882 | 80470 | 274 | 871 | 36 | 1432 | 81388 | 532 | 4346 | 5020 | 0 | 6 | 6 | 16 | 5 | 6 | 40783 | 84446 | 80000 | 80010 | 40987 | 40892 | 40879 | 40876 | 40745 |
| 80024 | 40761 | 306 | 1845 | 888 | 820 | 1 | 712 | 108 | 112 | 40784 | 773 | 1827 | 1744 | 181 | 25 | 164671 | 84714 | 80000 | 80010 | 80000 | 402437 | 1878424 | 0 | 284 | 49 | 37713 | 0 | 40767 | 40771 | 30858 | 3 | 30825 | 160010 | 20 | 80000 | 20 | 160000 | 40856 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80888 | 3926 | 467 | 8 | 873 | 80540 | 273 | 842 | 38 | 1569 | 81474 | 551 | 3762 | 5020 | 0 | 6 | 5 | 16 | 5 | 5 | 40817 | 83753 | 80000 | 80010 | 40914 | 40822 | 40815 | 40741 | 40770 |
| 80024 | 40791 | 306 | 1854 | 725 | 774 | 1 | 688 | 119 | 84 | 40728 | 746 | 1713 | 1791 | 143 | 25 | 167731 | 80518 | 80000 | 80010 | 80000 | 401835 | 1876829 | 0 | 285 | 49 | 37729 | 0 | 40802 | 40904 | 30709 | 3 | 30868 | 160010 | 20 | 80000 | 20 | 160000 | 40800 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80849 | 3760 | 444 | 11 | 884 | 80500 | 263 | 895 | 50 | 1649 | 81450 | 520 | 3872 | 5020 | 0 | 7 | 5 | 18 | 5 | 5 | 40819 | 82918 | 80000 | 80010 | 40898 | 40757 | 40762 | 40798 | 40797 |
| 80024 | 40791 | 305 | 1635 | 870 | 809 | 1 | 776 | 108 | 152 | 40747 | 736 | 1863 | 1903 | 153 | 25 | 167924 | 80580 | 80000 | 80010 | 80000 | 401692 | 1879000 | 0 | 245 | 49 | 37723 | 0 | 40771 | 40762 | 30814 | 3 | 30723 | 160010 | 20 | 80000 | 20 | 160000 | 40769 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80819 | 3815 | 467 | 4 | 852 | 80484 | 267 | 870 | 42 | 1550 | 81426 | 462 | 4329 | 5020 | 0 | 6 | 6 | 17 | 5 | 5 | 40907 | 84560 | 80000 | 80010 | 40836 | 40790 | 40732 | 40813 | 40803 |