Firestorm: STURB measurements

Code:

  sturb w0, [x6, #1]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	552	5	1	1	1	1	0	19	1	0	1	537	15	16	1	25	1000	1000	1000	22448	1	542	542	367	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	2	0	2	1002	2	42	0	73	1	16	1	1	540	1000	543	543	544	544	543
1004	542	4	0	0	0	0	0	3	0	0	0	527	16	16	0	25	1000	1000	1000	22448	1	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	2	0	2	1002	2	42	0	73	1	16	1	1	539	1000	543	543	543	543	544
1004	543	3	0	0	0	0	9	3	0	0	0	527	16	16	0	25	1000	1000	1000	22448	1	542	542	367	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	0	0	2	1002	2	42	0	73	1	16	1	1	540	1000	544	544	544	544	544
1004	543	4	0	0	0	0	0	3	1	0	0	528	16	16	1	25	1000	1000	1000	22448	1	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	0	0	6	1002	2	42	0	73	1	16	1	1	551	1000	543	543	543	543	544
1004	543	4	0	0	0	0	0	3	1	0	0	527	16	16	6	25	1000	1000	1000	22448	1	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	1	0	1016	0	0	2	1002	2	42	0	73	1	16	1	1	539	1000	543	543	543	543	544
1004	543	4	0	0	0	0	0	3	0	0	0	527	16	16	1	25	1000	1000	1000	22448	1	542	542	355	3	401	1000	1000	2000	542	543	1	1	1001	1000	1000	1000	0	42	0	0	1016	2	0	2	1002	2	42	0	73	1	16	1	1	540	1000	543	544	544	543	543
1004	542	4	0	0	0	0	0	3	0	0	0	527	16	16	0	25	1000	1000	1000	22448	1	542	542	356	3	400	1000	1000	2000	543	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	0	0	2	1002	2	42	0	73	1	16	1	1	540	1000	543	543	544	544	543
1004	542	4	0	0	0	0	0	3	0	0	0	528	16	16	0	25	1000	1000	1000	22448	1	542	543	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	1	0	1016	3	0	2	1002	2	42	0	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	0	0	0	9	3	0	0	0	527	16	16	1	25	1000	1000	1000	22448	1	542	542	356	3	401	1000	1000	2000	543	543	1	1	1001	1000	1000	1000	0	42	0	0	1016	0	0	2	1002	2	42	0	73	1	16	1	1	551	1000	543	543	543	543	543
1004	542	4	0	0	0	0	0	3	1	0	0	527	16	16	1	25	1000	1000	1000	22448	1	543	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	0	0	2	1002	2	42	0	73	1	16	1	1	539	1000	543	543	543	543	544

Count: 8

Code:

  sturb w0, [x6, #1]
  sturb w0, [x6, #1]
  sturb w0, [x6, #1]
  sturb w0, [x6, #1]
  sturb w0, [x6, #1]
  sturb w0, [x6, #1]
  sturb w0, [x6, #1]
  sturb w0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40043	300	0	0	0	0	0	0	0	3	1	0	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839448	1	49	36960	40042	40042	29955	3	30001	80100	200	80000	200	160000	40040	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80002	0	0	5	80002	0	0	0	0	5110	15	16	9	10	40037	80000	100	40043	40043	40044	40044	40041
80204	40042	300	0	0	0	0	0	0	0	3	1	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839352	1	49	37100	40043	40043	29953	29	30246	80316	200	80000	200	160000	40043	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80002	2	2	1072	80122	2	42	0	0	5144	12	16	11	11	40039	80000	100	40438	40424	40089	40195	40598
80204	40204	301	0	0	0	1	4	10	1332	792	1	0	0	40027	16	16	72	145	80100	100	80000	100	80108	500	1839472	1	49	36962	40043	40040	29953	3	29998	80316	200	80240	202	160000	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80184	2	42	0	0	80000	0	0	5	80002	2	0	0	0	5110	11	16	11	13	40039	80000	100	40045	40043	40045	40041	40044
80204	40043	300	0	0	0	0	0	0	0	3	0	0	0	40025	16	16	5	25	80100	100	80000	100	80000	500	1839693	1	49	36967	40047	40052	29976	3	30011	80100	200	80000	200	160000	40063	32004	1	1	80201	100	99	100	80000	100	80000	100	80016	14	44	0	1	80016	0	1	19	80002	16	44	14	0	5110	7	16	11	12	40051	80000	100	40053	40048	40054	40055	40048
80204	40047	299	1	0	0	1	0	0	0	17	0	0	1	40032	16	16	5	25	80100	100	80000	100	80000	500	1839933	1	49	36972	40047	40052	29965	3	30009	80100	200	80000	200	160000	40047	32016	1	1	80201	100	99	100	80000	100	80000	100	80014	15	44	0	2	80016	0	1	14	80002	16	44	14	1	5110	10	16	10	10	40044	80000	100	40055	40067	40055	40048	40048
80204	40063	300	1	0	1	1	0	0	0	14	1	0	1	40039	15	16	4	25	80100	100	80000	100	80000	500	1839933	1	49	36972	40054	40047	29961	3	30005	80100	200	80000	200	160000	40063	32000	1	1	80201	100	99	100	80000	100	80000	100	80014	15	0	0	1	80014	0	1	16	80000	14	44	14	1	5110	10	16	10	11	40048	80000	100	40056	40054	40048	40048	40055
80204	40047	299	1	0	0	0	0	0	0	20	0	0	1	40032	16	16	1	25	80100	100	80000	100	80000	500	1839692	1	49	36975	40047	40054	29960	3	30005	80100	200	80000	200	160000	40052	32000	1	1	80201	100	99	100	80000	100	80000	100	80014	15	0	0	1	80014	0	0	16	80002	16	0	14	0	5110	11	16	10	13	40052	80000	100	40055	40055	40055	40053	40048
80204	40063	300	1	1	0	0	0	0	0	14	1	0	1	40048	16	16	6	25	80100	100	80000	100	80000	500	1839692	1	49	36974	40047	40054	29967	3	30021	80100	200	80000	200	160000	40054	32000	1	1	80201	100	99	100	80000	100	80000	100	80016	14	44	0	0	80016	0	0	17	80002	14	0	14	1	5110	11	16	11	10	40050	80000	100	40053	40048	40053	40055	40065
80204	40054	300	1	0	1	0	0	0	0	19	0	0	1	40037	0	16	1	25	80100	100	80000	100	80000	500	1839692	1	49	36967	40051	40054	29960	3	30012	80100	200	80000	200	160000	40052	32007	1	1	80201	100	99	100	80000	100	80000	100	80014	14	42	0	0	80014	0	0	20	80002	16	44	14	1	5110	12	16	11	13	40044	80000	100	40064	40055	40049	40048	40056
80204	40054	300	1	0	1	0	0	0	0	19	1	0	1	40032	15	0	5	25	80100	100	80000	100	80000	500	1839692	0	49	36974	40052	40053	29965	3	30012	80100	200	80000	200	160000	40052	32007	1	1	80201	100	99	100	80000	100	80000	100	80015	15	44	0	1	80016	0	1	14	80002	16	44	14	1	5110	12	16	11	11	40060	80000	100	40055	40056	40055	40054	40048

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	299	0	0	0	0	0	0	21	1	0	0	1	40044	0	16	0	25	80010	10	80000	10	80000	50	1839424	0	1	0	49	36960	40042	40040	29977	3	30029	80010	20	80000	20	160000	40047	40059	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80000	1	0	0	80002	16	36	14	1	5020	5	0	0	12	16	7	9	40039	80000	10	40043	40051	40041	40044	40043
80024	40042	300	0	0	0	0	0	0	0	0	0	0	0	40035	16	16	0	25	80010	10	80000	10	80000	50	1839760	0	0	5	49	36962	40042	40042	29977	3	30029	80010	20	80000	20	160000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	0	0	2	80002	2	34	0	0	5020	5	0	0	12	16	10	10	40039	80000	10	40049	40054	40048	40060	40048
80024	40059	300	1	1	0	1	0	0	14	1	0	0	1	40043	16	16	0	25	80010	10	80000	10	80000	50	1840197	0	1	0	49	36979	40052	40059	29993	3	30031	80010	20	80000	20	160000	40051	40047	1	1	80021	10	9	10	80000	10	80000	10	80014	16	0	0	1	80016	0	2	14	80002	16	36	14	1	5020	0	0	0	9	16	10	8	40055	80000	10	40048	40062	40053	40061	40053
80024	40051	300	1	0	1	1	0	3	14	0	0	0	1	40043	16	16	3	25	80010	10	80000	10	80000	50	1839956	0	1	0	49	36980	40048	40060	29995	3	30039	80010	20	80000	20	160000	40059	40059	1	1	80021	10	9	10	80000	10	80000	10	80015	14	0	0	0	80016	0	0	14	80002	16	36	14	0	5020	5	0	0	9	16	9	8	40050	80000	10	40060	40048	40062	40052	40059
80024	40047	300	1	1	0	1	0	0	14	1	0	0	1	40044	16	16	2	25	80010	10	80000	10	80000	50	1839692	0	0	5	49	36972	40060	40052	29987	3	30038	80010	20	80000	20	160000	40058	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	15	35	0	2	80014	0	0	19	80000	16	36	14	0	5020	5	0	0	10	16	10	13	40055	80000	10	40061	40048	40061	40060	40061
80024	40047	300	1	0	0	1	0	0	19	1	0	0	1	40045	0	16	5	25	80010	10	80000	10	80000	50	1839956	0	1	0	49	36980	40047	40060	29995	3	30039	80010	20	80000	20	160000	40059	40059	1	1	80021	10	9	10	80000	10	80000	10	80015	14	36	0	0	80014	5	1	22	80002	16	36	14	1	5020	5	0	0	10	16	9	7	40139	80000	10	40060	40048	40048	40053	40048
80024	40047	299	1	1	0	1	0	0	14	0	0	0	1	40032	0	16	3	25	80010	10	80000	10	80000	50	1839692	0	0	5	49	36980	40059	40060	29995	3	30027	80010	20	80000	20	160000	40058	40058	1	1	80021	10	9	10	80000	10	80000	10	80014	14	36	0	1	80016	0	0	18	80002	14	36	14	0	5020	5	0	0	7	16	10	12	40050	80000	10	40061	40061	40048	40048	40059
80024	40052	300	1	0	1	1	0	0	14	0	0	0	1	40038	16	16	1	25	80010	10	80000	10	80000	50	1839692	0	0	5	49	36978	40047	40058	29994	3	30032	80010	20	80000	20	160000	40052	40059	1	1	80021	10	9	10	80000	10	80000	10	80014	15	0	0	1	80016	0	1	17	80002	16	36	14	0	5020	5	0	0	8	16	10	10	40532	80000	10	40133	40060	40054	40060	40191
80024	40047	300	1	0	0	1	4	12	18	1	0	0	1	40032	16	16	5	85	80070	10	80240	10	80000	50	1840220	0	1	5	49	36979	40188	40336	29994	3	30261	80010	20	80000	20	160000	40052	40059	1	1	80021	10	9	10	80000	10	80000	10	80015	14	36	2	1	80016	4	0	19	80002	14	36	14	0	5020	5	1	0	10	16	9	7	40057	80000	10	40053	40059	40056	40061	40048
80024	40051	300	1	1	0	0	0	0	19	0	0	0	1	40032	16	16	2	25	80010	10	80000	10	80000	50	1839908	0	0	5	49	36970	40058	40050	29982	3	30039	80010	20	80000	20	160000	40059	40058	1	1	80021	10	9	10	80000	10	80000	10	80014	15	36	0	0	80016	0	1	24	80002	16	36	14	0	5020	0	0	0	6	16	11	9	40054	80000	10	40052	40060	40055	40062	40054

STURB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations