Firestorm: PRFM (register, PSTL2KEEP) measurements

Code:

  prfm pstl2keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1618	12	35	18	32	2453	1612	906	25	1000	1000	1000	68077	1	1546	1577	1319	3	1457	1000	1000	1000	1566	1556	1	1	1001	258	2269	2255	3268	0	2447	2282	1000	73	1	16	1	1	1494	1000	1579	1616	1624	1595	1600
1004	1579	12	33	18	33	2454	1574	893	25	1000	1000	1000	69294	1	1571	1575	1278	3	1477	1000	1000	1000	1553	1579	1	1	1001	246	2298	2274	3288	0	2431	2237	1000	73	1	16	1	1	1505	1000	1581	1618	1547	1594	1566
1004	1607	12	33	17	33	2465	1608	881	25	1000	1000	1000	69220	1	1591	1586	1276	3	1440	1000	1000	1000	1578	1599	1	1	1001	259	2258	2253	3263	0	2462	2283	1000	73	1	16	1	1	1495	1000	1624	1574	1602	1605	1670
1004	1591	12	34	18	35	2458	1599	875	25	1000	1000	1000	70381	1	1599	1580	1284	3	1472	1000	1000	1000	1555	1548	1	1	1001	263	2255	2292	3285	0	2466	2272	1000	73	1	16	1	1	1513	1000	1629	1618	1592	1572	1617
1004	1573	12	34	16	32	2474	1616	870	25	1000	1000	1000	69377	1	1592	1596	1310	3	1446	1000	1000	1000	1610	1587	1	1	1001	219	2253	2264	3266	0	2447	2258	1000	73	1	16	1	1	1507	1000	1600	1572	1602	1595	1599
1004	1593	11	33	19	34	2480	1588	879	25	1000	1000	1000	69086	1	1575	1610	1306	3	1464	1000	1000	1000	1640	1571	1	1	1001	251	2265	2275	3276	1	2441	2283	1000	73	1	16	1	1	1490	1000	1574	1576	1624	1577	1593
1004	1582	12	33	19	34	2441	1647	874	25	1000	1000	1000	68113	1	1582	1581	1304	3	1422	1000	1000	1000	1581	1568	1	1	1001	238	2268	2279	3245	0	2449	2271	1000	73	1	16	1	1	1502	1000	1602	1578	1597	1572	1594
1004	1599	12	32	18	34	2440	1556	850	25	1000	1000	1000	68584	1	1601	1567	1283	3	1454	1000	1000	1000	1575	1596	1	1	1001	236	2274	2255	3271	0	2441	2252	1000	73	1	16	1	1	1490	1000	1573	1616	1584	1619	1610
1004	1618	11	32	16	34	2447	1601	876	25	1000	1000	1000	68987	1	1571	1617	1320	3	1469	1000	1000	1000	1603	1592	1	1	1001	250	2259	2259	3272	0	2457	2240	1000	73	1	16	1	1	1477	1000	1587	1602	1594	1611	1628
1004	1590	13	33	16	33	2447	1602	882	25	1000	1000	1000	68884	1	1564	1597	1276	3	1463	1000	1000	1000	1561	1601	1	1	1001	242	2310	2265	3246	0	2439	2248	1000	73	1	16	1	1	1501	1000	1632	1629	1601	1602	1574

Test 2: throughput

Code:

  prfm pstl2keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5581

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15666	116	369	192	373	0	24755	15585	9560	25	20241	10220	10000	10104	10000	128563	727172	1	42	49	12474	15454	15682	12807	7	13116	20116	10204	10004	10216	10016	15558	156	1	1	20201	100	99	2180	100	10100	100	23246	23156	33043	0	24829	23016	10000	1	1	1	1317	0	16	0	0	15649	10085	10000	10100	15626	15593	15655	15499	15521
20204	15573	116	373	191	375	0	24876	15488	9560	25	20226	10193	10000	10104	10000	130609	727236	1	40	49	12451	15511	15678	12936	6	12975	20108	10208	10008	10204	10020	15631	154	1	1	20201	100	99	2107	100	10100	100	23350	22896	33190	0	24667	23013	10000	1	1	1	1317	0	16	0	0	15527	10093	10000	10100	15633	15582	15653	15509	15619
20204	15592	116	376	196	370	0	24819	15488	9674	25	20193	10214	10000	10100	10000	130406	727995	1	44	49	12384	15464	15621	12823	3	12960	20100	10200	10000	10200	10000	15584	155	1	1	20201	100	99	2259	100	10100	100	23035	23195	32997	0	25091	23225	10000	0	0	0	1311	1	16	1	1	15359	10123	10000	10100	15461	15614	15639	15662	15708
20204	15439	116	369	198	372	0	24683	15495	9648	25	20217	10163	10000	10100	10000	130668	732456	1	33	49	12349	15566	15713	12884	3	13003	20100	10200	10000	10200	10000	15662	155	1	1	20201	100	99	2124	100	10100	100	23141	23016	33146	0	24972	23167	10000	0	0	0	1310	1	16	1	1	15435	10126	10000	10100	15603	15659	15620	15571	15691
20204	15625	116	375	194	373	0	24888	15524	9639	25	20214	10199	10000	10100	10000	128689	726619	1	35	49	12572	15610	15507	12761	3	13013	20100	10200	10000	10200	10000	15569	154	1	1	20201	100	99	2236	100	10100	100	23025	23163	33184	0	24747	23073	10000	0	0	0	1310	1	16	1	1	15353	10102	10000	10100	15566	15618	15626	15571	15479
20204	15658	117	375	198	371	0	24852	15466	9731	25	20181	10205	10000	10100	10000	130889	724994	1	40	49	12350	15591	15573	12918	3	12998	20100	10200	10000	10200	10000	15505	155	1	1	20201	100	99	2158	100	10100	100	23146	23228	33236	0	24823	23419	10000	0	0	0	1310	1	17	1	1	15529	10087	10000	10100	15571	15590	15602	15552	15540
20204	15576	117	375	193	371	0	24806	15631	9638	25	20235	10202	10000	10100	10000	131781	726130	1	33	49	12436	15627	15609	12747	3	13041	20100	10200	10000	10200	10000	15606	156	1	1	20201	100	99	2126	100	10100	100	23134	23095	33175	0	24918	23013	10000	0	0	0	1310	1	16	1	1	15408	10126	10000	10100	15552	15608	15635	15522	15641
20204	15583	117	375	195	370	0	24708	15571	9516	25	20247	10208	10000	10100	10000	130671	736000	1	32	49	12419	15465	15537	12847	3	13100	20100	10200	10000	10200	10000	15497	156	1	1	20201	100	99	2178	100	10100	100	23100	23004	33197	0	24922	23005	10000	0	0	0	1310	1	16	1	1	15460	10084	10000	10100	15652	15545	15545	15532	15541
20204	15647	117	375	196	382	0	24763	15540	9493	25	20217	10217	10000	10100	10000	130271	729401	1	26	49	12575	15533	15524	12788	3	12987	20100	10200	10000	10200	10000	15500	155	1	1	20201	100	99	2230	100	10100	100	23246	23171	33167	0	24819	23215	10000	0	0	0	1310	1	16	1	1	15632	10132	10000	10100	15459	15668	15602	15431	15558
20204	15567	117	372	191	373	0	24699	15435	9639	25	20223	10208	10000	10100	10000	128099	727497	1	31	49	12439	15523	15592	12786	7	13046	20100	10200	10000	10200	10000	15623	154	1	1	20201	100	99	2153	100	10100	100	23190	23053	33140	0	24573	23096	10000	0	0	0	1310	1	16	1	1	15382	10090	10000	10100	15560	15581	15532	15551	15661

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5513

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15514	116	387	200	387	24985	15598	9573	25	20130	10136	10000	10010	10000	129749	720073	36	49	12371	15433	15502	12863	3	12966	20010	10020	10000	10020	10000	15584	148	1	1	20021	10	9	2055	10	10010	10	23600	23387	33506	25104	23299	10000	1271	1	16	1	1	15453	10150	10000	10010	15526	15542	15474	15485	15560
20024	15591	117	391	200	385	25176	15518	9522	25	20124	10139	10000	10010	10000	129373	724147	44	49	12307	15504	15505	12788	3	13071	20010	10020	10000	10020	10000	15464	149	1	1	20021	10	9	2206	10	10010	10	23291	23234	33122	25108	23215	10000	1270	1	16	2	1	15353	10117	10000	10010	15483	15488	15497	15461	15611
20024	15502	115	392	203	387	25021	15575	9622	25	20157	10160	10000	10010	10000	129710	730863	40	49	12479	15474	15553	12882	3	12932	20010	10020	10000	10020	10000	15513	152	1	1	20021	10	9	2165	10	10010	10	23387	23422	33271	25076	23118	10000	1270	1	16	1	1	15503	10153	10000	10010	15423	15534	15559	15484	15465
20024	15562	115	388	203	385	25250	15347	9539	25	20175	10148	10000	10010	10000	129279	733533	42	49	12391	15452	15556	12941	3	12868	20010	10020	10000	10020	10000	15492	154	1	1	20021	10	9	2057	10	10010	10	23555	23081	33218	25015	23317	10000	1270	1	16	1	1	15507	10141	10000	10010	15489	15544	15385	15505	15614
20024	15591	115	387	195	382	25027	15521	9446	25	20112	10130	10000	10010	10000	130467	725313	36	49	12462	15533	15650	12919	3	13039	20010	10020	10000	10020	10000	15502	146	1	1	20021	10	9	2171	10	10010	10	23223	23393	33200	25211	23513	10000	1270	1	16	4	1	15400	10147	10000	10010	15667	15462	15578	15415	15586
20024	15489	115	391	208	387	25154	15407	9488	25	20148	10121	10000	10010	10000	129630	726395	41	49	12429	15484	15459	12852	3	12963	20010	10020	10000	10020	10000	15649	175	1	1	20021	10	9	2082	10	10010	10	23072	23197	33628	25149	23208	10000	1270	1	16	1	1	15401	10126	10000	10010	15515	15538	15648	15452	15577
20024	15548	117	389	202	389	24957	15557	9495	25	20154	10133	10000	10010	10000	131478	726476	46	49	12334	15460	15623	12828	3	12906	20010	10020	10000	10020	10000	15531	176	1	1	20021	10	9	2096	10	10010	10	23436	23567	33469	24868	23297	10000	1270	1	16	2	1	15352	10129	10000	10010	15518	15490	15463	15461	15418
20024	15457	115	397	203	387	25104	15459	9595	25	20163	10172	10000	10010	10000	128903	724469	42	49	12421	15490	15373	12780	3	12971	20010	10020	10000	10020	10000	15536	146	1	1	20021	10	9	2095	10	10010	10	23204	23287	33667	25059	23387	10000	1270	1	16	1	1	15498	10138	10000	10010	15559	15489	15514	15506	15607
20024	15504	116	389	197	397	25007	15618	9582	25	20127	10148	10000	10010	10000	130084	731689	55	49	12411	15579	15486	12836	3	13032	20010	10020	10000	10020	10000	15365	178	1	1	20021	10	9	2243	10	10010	10	23244	23284	33422	24941	23269	10000	1270	1	16	1	1	15366	10141	10000	10010	15348	15556	15520	15472	15469
20024	15399	116	385	200	385	24926	15528	9536	25	20118	10136	10000	10010	10000	130052	724160	48	49	12485	15558	15587	12843	3	13011	20010	10020	10000	10020	10000	15551	175	1	1	20021	10	9	2078	10	10010	10	23241	23438	33240	25167	23143	10000	1270	1	16	1	1	15409	10135	10000	10010	15622	15532	15440	15370	15433

Test 3: throughput

Code:

  prfm pstl2keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5415

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15364	116	307	151	306	24246	0	0	15503	9539	25	10100	100	10000	100	10005	500	722704	1	49	12300	15566	15365	14302	7	14094	10220	200	10127	200	10000	15400	12176	1	1	10201	100	99	2589	100	100	100	22426	22438	32426	0	24206	22492	10000	0	1	1	1	718	0	16	0	0	15415	10000	100	15430	15407	15422	15362	15425
10204	15365	115	307	152	307	24235	0	0	15417	9489	25	10149	100	10000	100	10000	511	732771	1	49	12550	15360	15473	13947	7	14280	10100	200	10000	200	10000	15417	12204	1	1	10201	100	99	2528	100	100	100	22461	22475	32566	0	24322	22466	10000	2	1	1	1	722	2	24	2	2	15370	10000	100	15346	15333	15364	15445	15450
10204	15414	115	308	154	309	24231	0	1	15417	9431	25	10100	100	10000	100	10000	500	719731	1	49	12296	15450	15395	13887	6	14339	10100	200	10000	200	10000	15446	12125	1	1	10201	100	99	2571	100	100	100	22459	22473	32494	0	24288	22483	10000	0	1	1	1	764	2	24	2	2	15353	10000	100	15428	15369	15384	15477	15398
10204	15405	116	302	157	309	24356	176	1	15394	9436	25	10100	100	10000	100	10000	500	724760	0	49	12270	15339	15351	13989	6	14132	10100	200	10000	200	10000	15342	12271	1	1	10201	100	99	2491	100	100	100	22507	22496	32471	0	24262	22447	10000	0	1	1	1	722	2	24	2	2	15339	10000	100	15445	15343	15362	15505	15436
10204	15414	115	305	153	310	24263	0	1	15469	9552	25	10100	100	10000	100	10000	500	723679	1	49	12734	15396	15451	13980	6	14095	10100	200	10000	200	10000	15381	12244	1	1	10201	100	99	2508	100	100	100	22552	22487	32524	0	24329	22546	10000	0	1	1	1	722	2	24	3	2	15309	10000	100	15435	15382	15472	15401	15448
10204	15393	116	307	153	306	24260	0	0	15370	9449	25	10100	100	10000	100	10000	500	725501	0	49	12224	15390	15364	13952	6	14160	10100	200	10000	200	10000	15409	12218	1	1	10201	100	99	2530	100	100	100	22405	22420	32473	0	24293	22498	10000	0	1	1	1	722	3	24	2	2	15413	10000	100	15456	15398	15487	15433	15413
10204	15377	116	308	154	308	24308	0	1	15418	9488	25	10100	100	10000	100	10000	500	724147	0	49	12336	15400	15326	13962	6	14033	10100	200	10000	200	10000	15422	12117	1	1	10201	100	99	2527	100	100	100	22513	22504	32498	0	24264	22467	10000	0	1	1	1	722	2	24	2	2	15358	10000	100	15423	15463	15436	15374	15461
10204	15480	115	310	152	308	24239	0	1	15443	9488	25	10100	100	10000	100	10000	500	719839	0	49	12284	15452	15363	13980	6	14119	10100	200	10000	200	10000	15419	12223	1	1	10201	100	99	2507	100	100	100	22480	22484	32534	0	24239	22465	10000	0	1	1	1	722	2	24	2	2	15337	10000	100	15474	15404	15386	15386	15349
10204	15438	118	308	153	302	24253	0	1	15390	9457	25	10100	100	10000	100	10000	500	719519	0	49	12391	15423	15709	14076	6	14091	10100	200	10000	200	10000	15343	12176	1	1	10201	100	99	2544	100	100	100	22420	22529	32519	0	24236	22583	10000	0	1	1	1	722	2	24	2	2	15370	10000	100	15467	15327	15434	15475	15423
10204	15384	115	304	156	305	24259	0	1	15358	9483	25	10100	100	10000	100	10000	500	722961	1	49	12336	15350	15376	14063	6	14065	10100	200	10000	200	10000	15391	12290	1	1	10201	100	99	2574	100	100	100	22487	22438	32470	1	24278	22584	10000	0	1	1	1	722	2	24	2	2	15247	10000	100	15423	15355	15456	15397	15386

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5399

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15446	116	323	175	327	24585	15334	9476	25	10010	10	10000	10	10000	50	722873	0	49	12291	0	15377	15398	13979	3	14087	10010	20	10000	20	10000	15387	15384	1	1	10021	10	9	2604	10	10	10	22789	22781	32660	0	24461	22690	10000	0	640	2	16	2	2	15354	10000	10	15350	15430	15408	15372	15473
10024	15340	115	335	163	330	24594	15405	9488	25	10010	10	10000	10	10000	50	718615	0	49	12343	0	15323	15461	13968	3	14075	10010	20	10000	20	10000	15416	15338	1	1	10021	10	9	2533	10	10	10	22851	22807	32909	0	24608	22736	10000	0	640	2	16	2	2	15250	10000	10	15430	15572	15440	15385	15440
10024	15448	115	323	168	333	24510	15374	9426	25	10010	10	10000	10	10000	50	720543	0	49	12378	0	15378	15433	13930	3	14273	10010	20	10000	20	10000	15458	15478	1	1	10021	10	9	2536	10	10	10	22773	22778	32772	0	24507	22726	10000	0	640	2	16	2	2	15454	10000	10	15427	15389	15464	15464	15367
10024	15363	115	331	170	329	24598	15395	9470	25	10010	10	10000	10	10000	50	727278	1	49	12268	0	15392	15466	13963	3	14200	10010	20	10000	20	10000	15386	15420	1	1	10021	10	9	2589	10	10	10	22804	22767	32666	0	24566	22803	10000	0	640	2	16	2	2	15270	10000	10	15394	15447	15416	15385	15397
10024	15409	115	330	167	333	24566	15453	9385	25	10010	10	10000	10	10000	50	719274	1	49	12312	0	15373	15344	13933	3	14173	10010	20	10000	20	10000	15411	15367	1	1	10021	10	9	2557	10	10	10	22814	22682	32753	0	24534	22700	10000	0	640	2	16	2	2	15315	10000	10	15330	15444	15350	15386	15438
10024	15480	115	325	171	332	24616	15347	9469	25	10010	10	10000	10	10000	50	724730	0	49	12258	3	15458	15468	13873	3	14184	10010	20	10000	20	10000	15360	15429	1	1	10021	10	9	2460	10	10	10	22838	22730	32741	0	24569	22787	10000	0	640	2	16	2	2	15329	10000	10	15440	15344	15359	15285	15444
10024	15354	115	330	168	329	24626	15306	9538	25	10010	10	10000	10	10000	50	722257	0	49	12249	0	15368	15405	13979	3	14080	10010	20	10000	20	10000	15403	15360	1	1	10021	10	9	2556	10	10	10	22786	22689	32757	0	24606	22751	10000	0	640	2	16	2	2	15342	10000	10	15564	15351	15392	15378	15417
10024	15415	116	332	165	327	24504	15451	9537	25	10010	10	10000	10	10000	50	723213	0	49	12302	0	15405	15426	14046	3	14132	10010	20	10000	20	10000	15402	15465	1	1	10021	10	9	2587	10	10	10	22700	22762	32804	0	24662	22742	10000	0	640	2	16	2	2	15284	10000	10	15344	15359	15443	15412	15414
10024	15443	115	330	170	334	24606	15348	9466	25	10010	10	10000	10	10000	50	718971	1	49	12385	0	15343	15411	13982	3	14113	10010	20	10000	20	10000	15402	15419	1	1	10021	10	9	2490	10	10	10	22817	22755	32790	1	24600	22702	10000	0	640	2	16	2	2	15310	10000	10	15393	15454	15516	15468	15400
10024	15350	115	326	171	333	24548	15440	9426	25	10010	10	10000	10	10000	50	720387	1	49	12335	0	15396	15365	13972	3	14080	10010	20	10000	20	10000	15392	15443	1	1	10021	10	9	2556	10	10	10	22773	22775	32707	0	24483	22701	10000	0	640	2	16	2	2	15387	10000	10	15402	15366	15456	15443	15418

PRFM (register, PSTL2KEEP)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations