Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
dmb osh
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | 1e | 3f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst barrier (9c) | st unit uop (a7) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | f5 | f6 | f7 | f8 | fd |
| 1004 | 3027 | 23 | 3 | 3020 | 2009 | 1000 | 1000 | 1000 | 6000 | 0 | 34 | 3027 | 3035 | 3 | 2884 | 1000 | 1000 | 3027 | 3035 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3032 | 1000 | 3028 | 3036 | 3028 | 3036 | 3036 |
| 1004 | 3035 | 23 | 0 | 3020 | 2009 | 1000 | 1000 | 1000 | 6000 | 1 | 42 | 3035 | 3026 | 3 | 2885 | 1000 | 1000 | 3151 | 3035 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3023 | 1000 | 3036 | 3027 | 3036 | 3028 | 3027 |
| 1004 | 3026 | 22 | 0 | 3020 | 2009 | 1000 | 1000 | 1000 | 6000 | 1 | 42 | 3035 | 3026 | 3 | 2885 | 1000 | 1000 | 3026 | 3035 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3032 | 1000 | 3027 | 3036 | 3028 | 3036 | 3036 |
| 1004 | 3035 | 22 | 0 | 3011 | 2009 | 1000 | 1000 | 1000 | 6000 | 1 | 42 | 3035 | 3027 | 3 | 2885 | 1000 | 1000 | 3027 | 3035 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3024 | 1000 | 3036 | 3027 | 3036 | 3026 | 3028 |
| 1004 | 3027 | 22 | 0 | 3020 | 2009 | 1000 | 1000 | 1000 | 6000 | 0 | 42 | 3035 | 3027 | 3 | 2885 | 1000 | 1000 | 3027 | 3035 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3024 | 1000 | 3027 | 3036 | 3028 | 3036 | 3036 |
| 1004 | 3035 | 23 | 3 | 3012 | 2009 | 1000 | 1000 | 1000 | 6000 | 0 | 42 | 3035 | 3026 | 3 | 2885 | 1000 | 1000 | 3026 | 3035 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3024 | 1000 | 3036 | 3027 | 3036 | 3027 | 3036 |
| 1004 | 3035 | 23 | 0 | 3011 | 2009 | 1000 | 1000 | 1000 | 6000 | 0 | 42 | 3035 | 3027 | 3 | 2893 | 1000 | 1000 | 3035 | 3026 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3024 | 1000 | 3036 | 3028 | 3036 | 3028 | 3028 |
| 1004 | 3027 | 22 | 0 | 3012 | 2009 | 1000 | 1000 | 1000 | 6000 | 0 | 34 | 3027 | 3035 | 3 | 2893 | 1000 | 1000 | 3035 | 3026 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3023 | 1000 | 3036 | 3028 | 3036 | 3027 | 3028 |
| 1004 | 3027 | 23 | 0 | 3010 | 2001 | 1000 | 1000 | 1000 | 6000 | 1 | 42 | 3035 | 3025 | 3 | 2885 | 1000 | 1000 | 3025 | 3035 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3023 | 1000 | 3036 | 3028 | 3036 | 3027 | 3027 |
| 1004 | 3026 | 23 | 0 | 3020 | 2000 | 1000 | 1000 | 1000 | 6000 | 1 | 34 | 3027 | 3035 | 3 | 2893 | 1000 | 1000 | 3035 | 3026 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3032 | 1000 | 3028 | 3036 | 3027 | 3036 | 3026 |
Code:
dmb osh
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.9043
| retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst barrier (9c) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10204 | 29040 | 218 | 0 | 0 | 0 | 0 | 0 | 29012 | 19008 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 26055 | 29035 | 29135 | 3 | 27743 | 10100 | 200 | 10000 | 200 | 29035 | 23295 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 2 | 3 | 0 | 710 | 1 | 16 | 1 | 1 | 29132 | 10000 | 100 | 29044 | 29136 | 29036 | 29136 | 29136 |
| 10204 | 29135 | 217 | 0 | 0 | 0 | 0 | 0 | 29019 | 19008 | 10100 | 100 | 10000 | 100 | 10000 | 516 | 60232 | 0 | 49 | 25955 | 29135 | 29027 | 3 | 27742 | 10100 | 200 | 10000 | 200 | 29035 | 23295 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 1 | 914 | 0 | 710 | 1 | 16 | 1 | 1 | 29032 | 10000 | 100 | 29136 | 29037 | 29136 | 29043 | 29044 |
| 10204 | 29043 | 218 | 0 | 0 | 0 | 0 | 0 | 29120 | 19008 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 25955 | 29135 | 29027 | 3 | 27742 | 10100 | 200 | 10000 | 200 | 29035 | 23295 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29033 | 10000 | 100 | 29136 | 29044 | 29136 | 29036 | 29036 |
| 10204 | 29035 | 218 | 0 | 0 | 0 | 0 | 0 | 29120 | 18917 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 26055 | 29043 | 29135 | 3 | 27843 | 10100 | 200 | 10000 | 200 | 29135 | 23214 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29132 | 10000 | 100 | 29136 | 29043 | 29136 | 29044 | 29044 |
| 10204 | 29043 | 219 | 0 | 0 | 0 | 0 | 0 | 29120 | 18908 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 26055 | 29034 | 29135 | 3 | 27843 | 10100 | 200 | 10000 | 200 | 29135 | 23222 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 36 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29132 | 10000 | 100 | 29028 | 29136 | 29037 | 29136 | 29136 |
| 10204 | 29135 | 218 | 0 | 0 | 0 | 0 | 0 | 29120 | 18899 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 26055 | 29025 | 29135 | 3 | 27843 | 10100 | 200 | 10000 | 200 | 29135 | 23223 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 48 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29132 | 10000 | 100 | 29136 | 29044 | 29136 | 29044 | 29035 |
| 10204 | 29034 | 217 | 0 | 0 | 0 | 0 | 0 | 29020 | 18908 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 1 | 49 | 25962 | 29135 | 29043 | 3 | 27742 | 10100 | 200 | 10000 | 200 | 29035 | 23295 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 7 | 10000 | 40 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29132 | 10000 | 100 | 29035 | 29136 | 29026 | 29136 | 29136 |
| 10204 | 29135 | 217 | 0 | 0 | 0 | 0 | 0 | 29020 | 19008 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 25955 | 29135 | 29044 | 3 | 27751 | 10100 | 200 | 10000 | 200 | 29043 | 23295 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29040 | 10000 | 100 | 29136 | 29028 | 29136 | 29037 | 29036 |
| 10204 | 29035 | 218 | 0 | 0 | 0 | 6 | 0 | 29120 | 18916 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 26055 | 29042 | 29135 | 3 | 27843 | 10100 | 200 | 10000 | 200 | 29135 | 23216 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 1 | 3 | 0 | 710 | 1 | 16 | 1 | 1 | 29132 | 10000 | 100 | 29044 | 29136 | 29036 | 29136 | 29136 |
| 10204 | 29135 | 217 | 0 | 0 | 0 | 3 | 0 | 29028 | 19008 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 25956 | 29135 | 29042 | 3 | 27751 | 10100 | 200 | 10000 | 200 | 29043 | 23295 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 4 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29132 | 10000 | 100 | 29036 | 29136 | 29028 | 29136 | 29136 |
Result (median cycles for code): 2.9867
| retire uop (01) | cycle (02) | 03 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst barrier (9c) | 9f | st unit uop (a7) | l1d cache writeback (a8) | ac | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10024 | 29867 | 223 | 0 | 29936 | 19832 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59982 | 1 | 49 | 26871 | 29865 | 29951 | 3 | 28595 | 10010 | 20 | 10000 | 20 | 29865 | 29951 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 3 | 3 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29948 | 10000 | 10 | 29868 | 29952 | 29868 | 29952 | 29952 |
| 10024 | 29951 | 224 | 0 | 29852 | 19915 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59982 | 1 | 49 | 26786 | 29951 | 29865 | 3 | 28597 | 10010 | 20 | 10000 | 20 | 29864 | 29951 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 1 | 3 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29948 | 10000 | 10 | 29866 | 29952 | 29865 | 29952 | 29952 |
| 10024 | 29951 | 224 | 0 | 29850 | 19915 | 10010 | 10 | 10000 | 14 | 10000 | 50 | 59982 | 1 | 49 | 26787 | 29951 | 29867 | 3 | 28596 | 10010 | 20 | 10000 | 20 | 29866 | 29951 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 0 | 60 | 0 | 0 | 651 | 3 | 16 | 2 | 3 | 29948 | 10000 | 10 | 29867 | 29952 | 29868 | 29952 | 29868 |
| 10024 | 29867 | 225 | 0 | 29936 | 19829 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59982 | 1 | 49 | 26871 | 29866 | 29951 | 3 | 28681 | 10010 | 20 | 10000 | 20 | 29951 | 29865 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 1 | 3 | 0 | 0 | 640 | 3 | 16 | 2 | 2 | 29863 | 10000 | 10 | 29952 | 29868 | 29952 | 29868 | 29952 |
| 10024 | 29951 | 223 | 0 | 29852 | 19915 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59982 | 1 | 49 | 26785 | 29951 | 29866 | 3 | 28597 | 10010 | 20 | 10000 | 20 | 29867 | 29951 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 0 | 78 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29864 | 10000 | 10 | 29952 | 29868 | 29952 | 29868 | 29868 |
| 10024 | 29867 | 224 | 0 | 29850 | 19915 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59982 | 1 | 49 | 26871 | 29865 | 29951 | 3 | 28681 | 10010 | 20 | 10011 | 20 | 29865 | 29951 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 31 | 12 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29948 | 10000 | 10 | 29868 | 29952 | 29868 | 29952 | 29952 |
| 10024 | 29951 | 224 | 0 | 29849 | 19915 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59982 | 1 | 49 | 26871 | 29866 | 29951 | 3 | 28681 | 10010 | 20 | 10000 | 20 | 29951 | 29866 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 1 | 3 | 0 | 0 | 640 | 3 | 16 | 2 | 2 | 29948 | 10000 | 10 | 29868 | 29952 | 29867 | 29952 | 29952 |
| 10024 | 29951 | 224 | 0 | 29936 | 19831 | 10010 | 10 | 10008 | 12 | 10000 | 50 | 59982 | 1 | 49 | 26871 | 29866 | 29951 | 3 | 28681 | 10010 | 20 | 10000 | 20 | 29951 | 29866 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 0 | 3 | 0 | 0 | 640 | 2 | 16 | 3 | 3 | 29862 | 10000 | 10 | 29952 | 29867 | 29952 | 29867 | 29867 |
| 10024 | 29866 | 223 | 0 | 29851 | 19915 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59982 | 1 | 49 | 26787 | 29951 | 29867 | 3 | 28681 | 10010 | 20 | 10000 | 20 | 29951 | 29867 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 1 | 3 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29862 | 10000 | 10 | 29952 | 29867 | 29952 | 29868 | 29868 |
| 10024 | 29867 | 224 | 0 | 29852 | 19832 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59982 | 1 | 49 | 26871 | 29867 | 29951 | 3 | 28681 | 10010 | 20 | 10000 | 20 | 29951 | 29867 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 30 | 87 | 0 | 0 | 640 | 2 | 16 | 3 | 3 | 29863 | 10000 | 10 | 29952 | 29866 | 29952 | 29867 | 29867 |