Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
dsb st
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | 19 | 1e | 1f | 3f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst barrier (9c) | st unit uop (a7) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | eb | ? ldst retires (ed) | f5 | f6 | f7 | f8 | fd |
| 1004 | 17032 | 127 | 0 | 24 | 0 | 17017 | 15801 | 1000 | 1000 | 1000 | 6000 | 1 | 49 | 13957 | 14863 | 17032 | 3 | 16890 | 1000 | 1000 | 17032 | 17032 | 1 | 1 | 1001 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 16838 | 0 | 1000 | 17033 | 17033 | 17033 | 17033 | 17033 |
| 1004 | 17032 | 127 | 0 | 0 | 0 | 17017 | 15801 | 1000 | 1000 | 1000 | 6000 | 0 | 49 | 13957 | 14859 | 17032 | 3 | 16890 | 1000 | 1000 | 17032 | 17032 | 1 | 1 | 1001 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 16838 | 1 | 1000 | 17033 | 17033 | 17033 | 17033 | 17033 |
| 1004 | 17032 | 128 | 0 | 30 | 0 | 17017 | 15801 | 1000 | 1000 | 1000 | 6000 | 0 | 49 | 13957 | 14859 | 17032 | 3 | 16890 | 1000 | 1000 | 17032 | 17032 | 1 | 1 | 1001 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 16838 | 0 | 1000 | 17033 | 17033 | 17033 | 17033 | 17033 |
| 1004 | 17032 | 127 | 0 | 0 | 0 | 17017 | 15801 | 1000 | 1000 | 1000 | 6000 | 1 | 49 | 13957 | 14859 | 17032 | 3 | 16890 | 1000 | 1000 | 17032 | 17032 | 1 | 1 | 1001 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 16838 | 0 | 1000 | 17033 | 17033 | 17033 | 17033 | 17033 |
| 1004 | 17032 | 127 | 0 | 270 | 0 | 17017 | 15801 | 1000 | 1000 | 1000 | 6000 | 0 | 49 | 13957 | 14859 | 17032 | 3 | 16890 | 1000 | 1000 | 17032 | 17032 | 1 | 1 | 1001 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 16838 | 0 | 1000 | 17033 | 17033 | 17033 | 17033 | 17033 |
| 1004 | 17032 | 128 | 0 | 0 | 0 | 17017 | 15801 | 1000 | 1000 | 1000 | 6000 | 1 | 49 | 13957 | 14859 | 17032 | 3 | 16890 | 1000 | 1000 | 17032 | 17032 | 1 | 1 | 1001 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 16838 | 0 | 1000 | 17033 | 17033 | 17033 | 17033 | 17033 |
| 1004 | 17032 | 128 | 0 | 0 | 0 | 17017 | 15801 | 1000 | 1000 | 1000 | 6000 | 0 | 49 | 13957 | 14859 | 17032 | 3 | 16890 | 1000 | 1000 | 17032 | 17032 | 1 | 1 | 1001 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 16838 | 0 | 1000 | 17033 | 17033 | 17033 | 17033 | 17033 |
| 1004 | 17032 | 127 | 0 | 264 | 0 | 17017 | 15801 | 1000 | 1000 | 1000 | 6000 | 0 | 49 | 13957 | 14863 | 17032 | 3 | 16890 | 1000 | 1000 | 17032 | 17032 | 1 | 1 | 1001 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 16838 | 0 | 1000 | 17033 | 17033 | 17033 | 17033 | 17033 |
| 1004 | 17032 | 127 | 0 | 0 | 0 | 17017 | 15801 | 1000 | 1000 | 1000 | 6000 | 1 | 49 | 13957 | 14859 | 17032 | 3 | 16890 | 1000 | 1000 | 17032 | 17032 | 1 | 1 | 1001 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 16838 | 0 | 1000 | 17033 | 17033 | 17033 | 17033 | 17033 |
| 1004 | 17032 | 128 | 0 | 51 | 0 | 17017 | 15801 | 1000 | 1000 | 1000 | 6000 | 0 | 49 | 13957 | 14866 | 17032 | 3 | 16890 | 1000 | 1000 | 17032 | 17032 | 1 | 1 | 1001 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 16838 | 0 | 1000 | 17033 | 17033 | 17033 | 17033 | 17033 |
Code:
dsb st
(fused SUBS/B.cc loop)
Result (median cycles for code): 17.0032
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3a | 3f | 4b | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst barrier (9c) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | c2 | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10204 | 170032 | 1273 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159700 | 10100 | 100 | 10000 | 111 | 10000 | 500 | 59800 | 0 | 49 | 166957 | 151036 | 170073 | 15 | 168910 | 10153 | 200 | 10000 | 200 | 170032 | 135919 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 169838 | 0 | 10000 | 100 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10204 | 170032 | 1274 | 0 | 0 | 0 | 0 | 327 | 364 | 0 | 170017 | 0 | 159700 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 166957 | 150935 | 170032 | 3 | 168740 | 10100 | 200 | 10000 | 200 | 170032 | 135919 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 806 | 1 | 16 | 1 | 1 | 169838 | 1 | 10000 | 100 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10204 | 170032 | 1274 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159700 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 166957 | 150935 | 170032 | 3 | 168740 | 10100 | 200 | 10000 | 200 | 170032 | 135919 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 2 | 1 | 169838 | 0 | 10000 | 100 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10204 | 170032 | 1274 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159700 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 166957 | 150935 | 170032 | 3 | 168740 | 10100 | 200 | 10000 | 200 | 170032 | 135919 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 169838 | 0 | 10000 | 100 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10204 | 170032 | 1274 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159700 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 166957 | 150935 | 170032 | 3 | 168740 | 10100 | 200 | 10000 | 200 | 170032 | 135919 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 169838 | 0 | 10000 | 100 | 170049 | 170033 | 170033 | 170033 | 170033 |
| 10204 | 170032 | 1274 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159700 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 166957 | 150935 | 170032 | 3 | 168740 | 10100 | 200 | 10000 | 200 | 170032 | 135919 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 169838 | 0 | 10000 | 100 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10204 | 170032 | 1273 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 170017 | 0 | 159700 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 166957 | 150935 | 170032 | 3 | 168740 | 10100 | 200 | 10000 | 200 | 170032 | 135919 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 169838 | 0 | 10000 | 100 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10204 | 170032 | 1273 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159700 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 166957 | 150996 | 170032 | 3 | 168740 | 10100 | 200 | 10000 | 200 | 170032 | 135919 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 169838 | 0 | 10000 | 100 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10204 | 170032 | 1274 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159700 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 166957 | 150935 | 170032 | 3 | 168740 | 10100 | 200 | 10015 | 200 | 170032 | 135919 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 0 | 0 | 3 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 169838 | 0 | 10000 | 100 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10204 | 170032 | 1273 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 170017 | 1 | 159700 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 59800 | 0 | 49 | 166957 | 150935 | 170032 | 3 | 168740 | 10100 | 200 | 10000 | 200 | 170032 | 135919 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 169838 | 0 | 10000 | 100 | 170033 | 170033 | 170033 | 170033 | 170033 |
Result (median cycles for code): 17.0032
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 3f | 4b | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst barrier (9c) | 9f | st unit uop (a7) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10024 | 170032 | 1274 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159786 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59980 | 0 | 49 | 166952 | 149957 | 170032 | 3 | 168762 | 10031 | 20 | 10000 | 20 | 170032 | 170032 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 0 | 0 | 640 | 4 | 16 | 2 | 2 | 169838 | 10000 | 10 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10024 | 170032 | 1274 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159786 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59980 | 0 | 49 | 166952 | 150038 | 170032 | 9 | 168762 | 10010 | 20 | 10000 | 20 | 170032 | 170032 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 169838 | 10000 | 10 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10024 | 170032 | 1274 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159786 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59980 | 0 | 49 | 166952 | 149957 | 170032 | 3 | 168762 | 10010 | 20 | 10000 | 20 | 170032 | 170032 | 2 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 169838 | 10000 | 10 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10024 | 170032 | 1273 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159786 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59980 | 0 | 49 | 166952 | 149957 | 170032 | 3 | 168762 | 10010 | 20 | 10000 | 20 | 170032 | 170032 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 169838 | 10000 | 10 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10024 | 170032 | 1274 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159786 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 60045 | 0 | 49 | 166952 | 150037 | 170032 | 3 | 168762 | 10010 | 20 | 10000 | 20 | 170032 | 170032 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 169838 | 10000 | 10 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10024 | 170032 | 1273 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159786 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59980 | 1 | 49 | 163900 | 149957 | 170032 | 3 | 168762 | 10010 | 20 | 10000 | 20 | 170032 | 170032 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 169838 | 10000 | 10 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10024 | 170032 | 1274 | 0 | 0 | 0 | 0 | 9 | 170017 | 0 | 159786 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59980 | 1 | 49 | 166952 | 149957 | 170032 | 3 | 168762 | 10010 | 20 | 10000 | 20 | 170032 | 170032 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 0 | 0 | 640 | 2 | 16 | 3 | 3 | 169838 | 10000 | 10 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10024 | 170032 | 1274 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159786 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59980 | 0 | 49 | 166952 | 150028 | 170032 | 3 | 168762 | 10010 | 20 | 10000 | 20 | 170032 | 170032 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 1 | 0 | 640 | 3 | 16 | 3 | 3 | 169838 | 10000 | 10 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10024 | 170032 | 1274 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159786 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59980 | 1 | 49 | 166952 | 149957 | 170032 | 3 | 168762 | 10010 | 20 | 10000 | 20 | 170032 | 170032 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 169838 | 10000 | 10 | 170033 | 170033 | 170033 | 170033 | 170033 |
| 10024 | 170032 | 1274 | 0 | 0 | 0 | 0 | 0 | 170017 | 0 | 159786 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 59980 | 1 | 49 | 166952 | 149957 | 170032 | 3 | 168762 | 10010 | 20 | 10000 | 20 | 170032 | 170032 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 10000 | 1 | 0 | 640 | 3 | 16 | 2 | 3 | 169838 | 10000 | 10 | 170033 | 170033 | 170033 | 170033 | 170033 |