Firestorm: CSET (64-bit) measurements

Code:

  cset x0, hi

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	369	2	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	1000	0	0	73	2	18	2	2	366	1000	1000	370	370	370	370	370
1004	369	2	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	1000	3	0	73	2	18	2	2	366	1000	1000	370	370	370	370	370
1004	369	2	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	1000	2	0	73	2	18	2	2	366	1000	1000	370	370	370	370	370
1004	369	3	0	89	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	1000	0	0	73	2	18	2	2	366	1000	1000	370	370	370	370	370
1004	369	2	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	1000	0	0	73	2	18	2	2	366	1000	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	1000	0	0	73	2	18	2	2	366	1000	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	1000	0	230	73	2	18	2	2	366	1000	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	1000	0	245	73	2	18	2	2	366	1000	1000	370	370	370	370	370
1004	369	2	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	1000	0	0	73	2	18	2	2	366	1000	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	1000	0	0	73	2	18	2	2	366	1000	1000	370	370	370	370	370

Test 2: Latency 1->2

Chain cycles: 1

Code:

  cset x0, hi
  tst x0, 1

Initialization

  mov x0, 1

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	327	61	19930	25	20200	20200	20212	1297733	0	49	16955	20035	20035	17425	7	17485	20212	20224	20224	20080	104	1	1	20201	100	99	20100	10000	0	0	1	1	1	1320	2	16	1	1	20011	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20200	20200	20212	1297733	1	49	16955	20035	20035	17425	7	17486	20212	20224	20224	20035	104	1	1	20201	100	99	20100	10000	0	0	1	1	1	1320	1	16	1	1	20011	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20200	20200	20212	1297733	0	49	16955	20035	20035	17425	7	17486	20212	20224	20224	20035	104	1	1	20201	100	99	20100	10000	0	0	1	1	1	1320	1	16	1	1	20011	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20200	20200	20212	1297733	0	49	16955	20035	20035	17425	7	17485	20212	20224	20224	20035	104	1	1	20201	100	99	20100	10000	1	0	1	1	1	1319	1	16	1	2	20011	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20200	20200	20212	1297733	0	49	16955	20035	20035	17425	8	17486	20212	20224	20224	20035	104	1	1	20201	100	99	20100	10000	0	0	1	1	1	1319	1	16	1	1	20011	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	3	61	19930	25	20200	20200	20212	1297733	0	49	16955	20035	20035	17432	7	17486	20212	20224	20224	20035	104	1	1	20201	100	99	20100	10000	0	0	1	1	1	1320	2	16	2	1	20011	20100	10100	20036	20081	20036	20036	20036
20204	20035	149	0	61	19930	25	20200	20200	20212	1297733	0	49	16955	20035	20035	17425	7	17486	20212	20224	20224	20035	104	1	1	20201	100	99	20100	10000	0	0	1	1	1	1319	1	16	1	1	20011	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20200	20200	20212	1297733	0	49	16955	20035	20035	17425	7	17486	20212	20224	20224	20035	104	1	1	20201	100	99	20100	10000	0	0	1	1	1	1320	1	16	1	1	20011	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20200	20200	20212	1297733	1	49	16955	20035	20035	17425	8	17485	20212	20224	20224	20035	104	1	1	20201	100	99	20100	10000	0	0	1	1	1	1319	1	16	1	2	20011	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20200	20200	20212	1297733	0	49	16955	20035	20035	17425	7	17486	20212	20224	20224	20035	104	1	1	20201	100	99	20100	10000	0	0	1	1	1	1319	1	16	1	1	20011	20100	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	87	61	19918	25	20020	20020	20020	1297297	1	49	16955	0	20035	20035	17428	3	17504	20020	20020	20020	20035	104	1	1	20021	10	9	20010	10000	0	1270	2	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	20020	20035	104	1	1	20021	10	9	20010	10000	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	0	20035	20035	17428	3	17504	20020	20020	20020	20035	104	1	1	20021	10	9	20010	10000	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	251	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	20020	20035	104	1	1	20021	10	9	20010	10000	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20116	20020	20035	104	1	1	20021	10	9	20010	10000	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	1	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	20020	20035	104	1	1	20021	10	9	20010	10000	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	30	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	20020	20035	104	1	1	20021	10	9	20010	10000	0	1270	1	27	1	1	19995	20010	10010	20067	20067	20036	20036	20036
20024	20035	150	0	0	21	935	19918	25	20020	20020	20020	1297297	1	49	16955	0	20035	20035	17428	3	17504	20020	20020	20020	20035	104	1	1	20021	10	9	20010	10000	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	383	19918	25	20020	20020	20020	1297297	1	49	16955	0	20035	20035	17428	3	17504	20020	20020	20020	20035	104	1	1	20021	10	9	20010	10000	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20304	20020	20035	104	1	1	20021	10	9	20010	10000	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036

Test 3: throughput

Count: 8

Code:

  cset x0, hi
  cset x1, hi
  cset x2, hi
  cset x3, hi
  cset x4, hi
  cset x5, hi
  cset x6, hi
  cset x7, hi

Initialization

  mov x0, 0
  cmp x0, x0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26797	200	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	80200	26736	66	1	1	80201	100	99	100	80100	80100	0	0	0	5110	2	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	207	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	80200	26736	66	1	1	80201	100	99	100	80100	80100	2	3	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	36	25	80100	80100	80100	479799	0	49	23656	26736	26736	16672	3	16691	80100	80200	80200	26736	66	1	1	80201	100	99	100	80100	80100	1	0	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	80200	26736	66	1	1	80201	100	99	100	80100	80100	2	6	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	80200	26736	66	1	1	80201	100	99	100	80100	80100	0	78	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	36	25	80100	80100	80100	479799	0	49	23656	26736	26736	16672	3	16691	80100	80200	80200	26736	66	1	1	80201	100	99	100	80100	80100	1	0	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	80200	26736	66	1	1	80201	100	99	100	80100	80100	2	0	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	80200	26736	66	1	1	80201	100	99	100	80100	80100	1	0	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	201	0	36	25	80100	80100	80100	479799	0	49	23656	26736	26736	16672	3	16691	80100	80200	80200	26736	66	1	1	80201	100	99	100	80100	80100	1	171	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	36	25	80100	80100	80100	479799	0	49	23656	26736	26736	16672	3	16691	80100	80200	80200	26736	66	1	1	80201	100	99	100	80100	80100	1	6	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26723	200	0	0	0	36	25	80010	80010	80010	472059	49	23626	26706	26706	16665	3	16684	80010	80020	80020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	5020	0	3	18	3	2	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	36	25	80010	80010	80010	472059	49	23626	26706	26706	16665	3	16684	80010	80020	80020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	5020	0	3	18	2	3	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	3	0	0	212	25	80010	80010	80077	472059	49	23626	26706	26706	16665	3	16684	80010	80020	80020	26706	66	2	1	80021	10	9	10	80010	80010	0	0	4	0	0	5020	0	3	18	3	3	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	78	25	80010	80010	80010	472059	49	23626	26706	26706	16665	3	16684	80010	80020	80020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	5020	0	2	18	3	3	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	36	25	80010	80010	80010	472059	49	23626	26706	26706	16665	3	16684	80010	80020	80020	26706	66	1	1	80021	10	9	10	80010	80010	2	1	0	3	2	5020	0	3	18	3	2	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	207	0	88	0	36	25	80010	80010	80010	472059	49	23963	26706	26706	16665	3	16684	80010	80020	80020	26706	66	1	1	80021	10	9	10	80010	80010	0	4	0	0	0	5020	0	2	18	3	2	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	36	25	80010	80010	80010	472059	49	23626	26706	26706	16665	3	16684	80010	80020	80020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	5020	0	2	18	3	3	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	36	25	80010	80010	80010	472059	49	23626	26706	26706	16665	3	16684	80010	80020	80020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	5020	0	3	18	2	3	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	199	0	0	0	36	25	80010	80010	80010	472059	49	23626	26706	26706	16665	3	16684	80010	80020	80020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	5020	0	3	18	3	2	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	36	25	80010	80010	80010	472059	49	23626	26706	26706	16665	3	16684	80010	80020	80020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	5020	0	3	18	3	3	26702	80000	80010	26707	26707	26707	26707	26707

CSET (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations