Firestorm: LDNP (32-bit) measurements

Code:

  ldnp w0, w1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	403	3	0	0	1	45	1	0	1	379	2	1	12	19	25	1000	1000	1000	15389	398	398	96	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1039	0	61	1038	6	1	39	44	73	1	16	1	1	395	1038	10	10	4	1000	1000	399	399	399	399	399
2004	403	3	0	0	0	44	1	0	1	383	2	1	1	19	25	1000	1000	1000	15105	398	394	96	3	131	1000	2000	1000	398	35	1	1	1001	1000	1000	0	1000	43	1039	0	39	1038	6	1	39	44	73	1	16	1	1	391	1038	14	14	7	1000	1000	399	395	395	395	399
2004	400	3	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15288	398	398	96	3	134	1000	2000	1000	398	35	1	1	1001	1000	1000	0	1000	43	1038	0	39	1039	6	1	39	44	73	1	16	1	1	395	1038	14	14	4	1000	1000	399	399	399	399	399
2004	398	3	0	0	0	44	1	0	1	383	2	1	1	19	25	1000	1000	1000	15780	398	398	96	3	127	1000	2000	1000	398	35	1	1	1001	1000	1000	0	1000	43	1038	0	39	1038	6	1	39	43	73	1	16	1	1	395	1038	14	14	7	1000	1000	399	399	399	399	399
2004	394	3	0	0	1	44	0	0	1	383	2	12	1	19	25	1000	1000	1000	15014	398	398	96	3	131	1000	2000	1000	398	35	1	1	1001	1000	1000	0	1000	43	1038	0	39	1039	6	1	39	43	73	1	16	1	1	391	1039	14	10	7	1000	1000	399	395	395	399	399
2004	394	3	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15288	398	398	96	3	134	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1038	0	38	1039	6	1	39	44	73	1	16	1	1	391	1038	14	14	7	1000	1000	399	399	404	399	399
2004	398	3	0	0	0	46	0	0	1	383	2	12	1	19	25	1000	1000	1000	15246	398	398	96	3	131	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1038	0	39	1039	6	1	39	44	73	1	16	1	1	395	1038	14	10	4	1000	1000	395	395	395	399	399
2004	402	3	0	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15288	407	398	96	3	131	1000	2000	1000	398	35	1	1	1001	1000	1000	0	1000	43	1038	0	39	1039	6	1	39	43	73	1	16	1	1	391	1039	10	10	4	1000	1000	395	395	395	395	395
2004	394	3	0	0	0	45	0	0	1	383	2	1	1	16	25	1004	1130	1000	15284	399	398	96	18	131	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1038	0	39	1038	6	1	39	44	73	1	25	1	1	391	1038	14	10	7	1000	1000	399	399	399	399	399
2004	419	3	0	1	0	201	1	0	1	383	2	12	1	19	25	1000	1000	1000	15284	394	398	96	3	127	1000	2000	1000	398	35	1	1	1001	1000	1000	0	1000	44	1038	0	39	1038	6	1	39	44	73	1	16	1	1	395	1038	14	10	7	1000	1000	399	399	399	399	399

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldnp w0, w1, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	70051	524	0	0	0	0	0	0	0	0	2	0	1	0	0	70039	69698	59703	25	40104	30103	10002	30100	10000	613888	3342250	49	66979	0	70035	70054	63407	3	63695	40100	30200	20000	60200	10000	70054	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	4	1	10002	0	40	1	1	10000	1	0	1	0	0	2610	2	78	1	1	69808	10001	30003	0	10	0	10000	40100	70058	70061	70061	70061	70058
50204	70060	524	1	1	1	0	0	0	0	0	6	0	0	0	0	70036	69698	59684	25	40108	30106	10002	30100	10000	613646	3342394	49	66971	0	70051	70054	63388	3	63695	40100	30200	20000	60200	10000	70051	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10001	0	5	3	121	10000	1	1	0	1	1	2610	1	64	1	1	69809	10001	30006	0	10	0	10000	40100	70042	70042	70061	70061	70061
50204	70060	525	1	0	1	0	0	0	0	0	2	0	0	0	0	70045	69725	59709	25	40104	30106	10002	30100	10000	613942	3341607	49	66974	0	70054	70054	63407	3	63695	40100	30200	20000	60200	10000	70054	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	34	0	3	10000	1	0	0	0	0	2610	1	64	1	1	69817	10000	30003	0	10	13	10000	40100	70036	70052	70055	70036	70060
50204	70035	524	0	0	0	0	0	0	0	0	0	0	0	0	0	70036	69719	59684	25	40104	30103	10001	30100	10000	613652	3341304	49	66971	0	70051	70054	63407	3	63711	40100	30200	20000	60200	10000	70054	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	53	0	0	10000	1	0	1	0	0	2610	1	64	1	1	69798	10000	30003	13	0	13	10000	40100	70055	70052	70055	70036	70076
50204	70100	525	0	0	0	0	0	0	0	0	0	0	0	0	0	70020	69719	59703	25	40104	30103	10001	30100	10000	613930	3342250	49	66974	0	70054	70035	63407	3	63714	40100	30200	20000	60200	10000	70054	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	1	0	0	10000	0	0	1	0	0	2610	1	64	1	1	69814	10000	30003	10	10	10	10000	40100	70055	70036	70036	70036	70094
50204	70035	524	0	0	0	0	0	0	0	0	1	0	0	0	0	70039	69719	59700	25	40100	30103	10001	30100	10000	613930	3342250	49	66971	0	70054	70035	63404	3	63714	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10001	0	59	1	1	10000	0	1	1	1	1	2610	1	78	1	1	69823	10001	30003	13	10	0	10000	40100	70061	70042	70061	70042	70123
50204	70060	524	1	0	1	1	0	0	0	0	2	0	0	0	0	70026	69725	59706	25	40108	30106	10002	30100	10000	613646	3342538	49	66961	3	70054	70054	63407	3	63695	40100	30200	20000	60200	10000	70054	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	7	0	3	10000	1	0	0	0	0	2610	1	64	1	1	69820	10000	30000	0	10	13	10000	40100	70055	70055	70036	70055	70060
50204	70051	525	0	0	0	0	0	0	0	0	6	0	1	0	0	70042	69711	59688	25	40108	30103	10002	30100	10000	613646	3341607	49	66980	0	70041	70060	63410	3	63687	40100	30200	20000	60200	10000	70060	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	0	10001	1	35	1	1	10000	0	1	1	1	1	2610	1	64	1	1	69823	10001	30006	13	13	13	10000	40100	70061	70061	70042	70042	70118
50204	70057	524	1	1	1	0	0	0	0	0	2	0	0	0	0	70026	69725	59709	25	40104	30106	10002	30100	10000	613942	3342538	49	66980	0	70057	70060	63410	3	63687	40100	30200	20000	60200	10000	70041	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10001	1	38	1	1	10000	1	1	1	1	1	2610	1	64	1	1	69798	10000	30000	10	13	13	10000	40100	70036	70055	70055	70055	70107
50204	70054	524	0	0	0	0	1	0	0	0	0	0	1	0	0	70020	69719	59684	25	40104	30100	10001	30100	10000	613888	3342250	49	66971	0	70054	70035	63407	3	63714	40100	30200	20000	60200	10000	70054	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	6	0	12	10000	0	0	0	0	0	2610	1	64	1	1	69814	10000	30000	0	0	13	10000	40100	70036	70052	70055	70055	70056

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	70047	525	0	0	0	0	0	0	0	0	1	0	0	0	0	70032	69719	59692	25	40010	30010	10001	30010	10000	614994	3341899	1	0	49	66970	70047	70050	63415	0	3	63718	40010	30020	20000	60020	10000	70035	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	2	0	0	10000	1	0	0	0	2521	0	2	78	2	2	69814	10000	30000	0	0	9	10000	40010	70036	70048	70048	70036	70067
50024	70050	524	0	0	0	0	0	0	0	0	1	0	0	0	0	70032	69718	59689	25	40010	30010	10001	30010	10000	615126	3341899	1	0	49	66955	70050	70035	63415	0	3	63715	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	30	0	0	10000	0	1	0	0	2521	0	2	78	2	2	69817	10000	30003	0	0	0	10000	40010	70051	70048	70051	70048	70101
50024	70050	524	0	0	0	0	0	0	0	0	0	0	0	0	0	70032	69714	59692	25	40014	30013	10001	30010	10000	615102	3341899	1	0	49	66967	70047	70035	63403	0	3	63718	40010	30020	20000	60020	10000	70047	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	1	0	3	10000	1	1	0	0	2521	0	2	78	2	2	69814	10000	30003	6	0	9	10000	40010	70051	70039	70051	70051	70113
50024	70047	524	0	1	0	0	0	0	0	0	1	0	0	0	0	70035	69718	59689	25	40014	30010	10001	30010	10000	615102	3341295	1	0	49	66970	70047	70035	63403	0	3	63682	40010	30020	20000	60020	10000	70047	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	1	0	0	10000	1	1	0	0	2521	0	2	99	2	2	69801	10000	30003	6	6	6	10000	40010	70048	70048	70048	70048	70073
50024	70047	525	0	0	0	0	0	0	0	0	0	0	1	0	0	70020	69718	59689	25	40010	30013	10001	30010	10000	614994	3341899	1	0	49	66955	70035	70035	63418	0	3	63717	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	5	0	0	10000	1	1	0	0	2521	0	2	78	2	2	69801	10000	30003	0	0	6	10000	40010	70036	70051	70051	70036	70049
50024	70047	524	0	0	0	0	0	0	0	0	1	0	1	0	0	70035	69719	59677	25	40010	30013	10001	30010	10000	615126	3342046	1	0	49	66970	70047	70035	63415	0	3	63682	40010	30020	20000	60020	10000	70047	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	59	0	0	10000	1	1	0	0	2521	0	2	78	2	4	69801	10000	30003	6	0	6	10000	40010	70051	70036	70048	70048	70037
50024	70047	524	0	0	0	0	0	0	0	0	1	0	0	0	0	70020	69719	59689	25	40010	30010	10001	30010	10000	615102	3342046	1	0	49	66955	70050	70050	63418	0	3	63682	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	52	0	0	10000	0	0	0	0	2521	0	2	99	2	2	69803	10000	30003	0	6	0	10000	40010	70036	70092	70099	70057	70089
50024	70050	525	0	0	0	0	0	1	0	0	1	0	0	0	0	70020	69714	59677	25	40010	30010	10001	30010	10000	615126	3342046	1	0	49	66970	70035	70050	63418	0	3	63682	40010	30215	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	2	0	9	10000	1	1	0	0	2521	0	2	99	2	2	69817	10000	30003	6	6	0	10000	40010	70036	70051	70051	70051	70083
50024	70035	525	0	0	0	0	0	0	0	0	1	0	0	0	0	70032	69714	59677	25	40014	30013	10001	30010	10000	615102	3342046	1	0	49	66970	70050	70047	63418	0	3	63715	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	39	0	0	10000	1	1	0	0	2521	0	2	99	2	2	69814	10000	30003	9	9	9	10000	40010	70051	70036	70048	70051	70094
50024	70047	525	0	0	0	0	0	0	0	0	1	0	0	0	0	70032	69714	59677	25	40010	30013	10000	30010	10000	615126	3341439	1	0	49	66967	70047	70035	63403	0	3	63721	40010	30020	20000	60020	10000	70047	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	40	0	24	10000	1	1	0	0	2521	0	2	79	2	2	69801	10000	30003	0	0	9	10000	40010	70036	70048	70036	70048	70056

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldnp w0, w1, [x6]
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	18	1e	1f	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	70051	524	0	1	1	0	1	0	1	0	70042	69698	59700	25	40104	30103	10001	30100	10000	613930	3341304	1	49	66955	0	70051	70051	63404	3	63711	40100	30200	20000	60200	10000	70051	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10003	3	0	10000	1	1	0	0	0	2610	3	64	1	1	69798	10000	30006	10	10	10	10000	40100	70052	70052	70052	70052	70052
50204	70051	525	0	0	0	0	1	0	0	0	70036	69715	59700	25	40117	30103	10000	30100	10000	613930	3345224	0	49	66971	0	70051	70051	63404	3	63695	40100	30200	20000	60200	10000	70051	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	0	0	0	0	2610	1	64	1	1	69814	10000	30003	10	10	10	10000	40100	70052	70052	70052	70052	70052
50204	70051	524	0	0	0	0	1	0	1	0	70036	69715	59684	25	40104	30103	10001	30100	10000	613652	3342104	1	49	66971	0	70051	70035	63404	3	63711	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	0	2610	1	64	1	1	69814	10000	30003	10	10	10	10000	40100	70052	70052	70052	70052	70055
50204	70051	524	0	0	0	0	0	0	1	0	70036	69715	59702	25	40104	30103	10001	30100	10000	613939	3341304	0	49	66971	0	70035	70051	63404	3	63711	40100	30200	20000	60200	10000	70051	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	4560	10000	0	1	0	0	0	2711	1	64	1	1	69814	10000	30003	10	10	10	10000	40100	70036	70052	70052	70052	70052
50204	70051	525	0	1	0	0	6	0	1	0	70119	69715	59700	25	40104	30103	10000	30100	10000	613930	3342104	0	49	66971	0	70051	70035	63404	3	63711	40100	30200	20000	60200	10067	70054	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	1	1	0	0	1	2610	1	64	1	1	69798	10000	30003	10	10	10	10000	40100	70052	70052	70052	70052	70052
50204	70051	525	0	0	0	0	1	0	1	0	70036	69698	59700	25	40100	30103	10001	30100	10000	613930	3342104	0	49	66955	0	70035	70051	63404	3	63711	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	10000	1	1	0	0	0	2610	1	64	1	1	69814	10000	30003	0	10	10	10000	40100	70052	70052	70036	70036	70036
50204	70035	525	0	0	0	0	1	0	1	0	70142	69715	59700	25	40104	30103	10001	30100	10000	613939	3342104	0	49	66971	3	70051	70051	63404	3	63711	40100	30200	20000	60200	10066	70107	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	0	1	0	0	0	2610	1	64	1	1	69798	10000	30003	10	0	10	10000	40100	70036	70036	70036	70052	70052
50204	70035	525	0	0	0	0	1	0	1	0	70123	69698	59700	25	40104	30103	10001	30100	10000	613652	3342104	0	49	66971	0	70051	70035	63388	3	63711	40100	30200	20000	60200	10000	70051	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	0	2610	1	64	1	1	69814	10000	30006	10	10	10	10000	40100	70052	70052	70052	70052	70052
50204	70051	525	0	0	0	0	1	0	1	0	70036	69715	59700	25	40104	30103	10001	30100	10000	613652	3342104	1	49	66971	0	70051	70051	63404	3	63695	40100	30200	20000	60200	10000	70051	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	0	2610	1	64	1	1	69814	10000	30003	10	10	10	10000	40100	70052	70036	70052	70036	70052
50204	70051	525	0	1	0	0	1	0	0	0	70036	69715	59700	25	40104	30103	10001	30100	10000	613930	3342104	0	49	66971	0	70035	70051	63404	3	63711	40100	30200	20000	60200	10000	70051	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	3	10000	1	0	0	0	0	2610	1	64	1	1	69814	10000	30003	10	10	10	10000	40100	70052	70052	70052	70052	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	70051	525	0	0	0	0	0	0	0	1	0	0	0	0	0	70141	69722	59710	25	40018	30016	10002	30010	10000	615163	3342398	0	49	66977	70057	70041	63409	3	63739	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	2	1	10002	0	0	0	1	10000	1	1	0	1	1	2520	1	64	1	3	69818	10000	30006	10	10	10	10000	40010	70036	70052	70052	70036	70052
50024	70054	525	0	0	0	0	0	0	0	1	0	1	0	0	0	70125	69715	59677	25	40014	30013	10001	30010	10000	615145	3341295	0	49	66971	70035	70051	63419	3	63719	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10003	0	0	0	0	10000	1	0	1	0	0	2520	1	78	1	3	69818	10000	30006	10	0	10	10000	40010	70052	70052	70052	70036	70052
50024	70051	525	0	0	0	0	0	0	0	0	0	1	0	0	0	70099	69715	59693	25	40010	30013	10001	30010	10000	614994	3342095	0	49	66971	70051	70051	63419	3	63719	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	0	0	1	0	0	2520	3	78	1	1	69801	10000	30006	10	10	10	10000	40010	70052	70052	70052	70052	70036
50024	70051	525	0	0	0	0	0	0	0	1	0	0	0	0	0	70154	69715	59677	25	40014	30010	10001	30010	10000	615145	3342095	1	49	66971	70051	70051	63403	3	63719	40010	30020	20000	60020	10000	70035	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	2520	1	78	1	1	69819	10000	30006	10	0	10	10000	40010	70036	70052	70036	70052	70036
50024	70051	524	0	0	0	0	0	0	0	1	0	1	0	0	0	70152	69715	59693	25	40014	30013	10001	30164	10000	615145	3342095	0	49	66971	70051	70051	63419	3	63719	40010	30020	20000	60020	10000	70051	37	2	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	3	10000	1	0	0	0	0	2520	3	64	1	1	69818	10000	30006	10	10	10	10000	40010	70062	70052	70052	70052	70052
50024	70051	525	0	0	0	1	0	0	0	1	0	1	0	0	0	70129	69719	59693	25	40010	30013	10001	30010	10000	615145	3342095	0	49	66971	70051	70051	63419	3	63719	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	0	0	1	0	0	2520	3	78	1	1	69818	10000	30006	10	10	10	10000	40010	70052	70054	70052	70036	70053
50024	70239	525	0	0	0	1	0	0	0	1	0	1	0	0	0	70042	69819	59693	76	40014	30013	10000	30010	10000	615145	3342095	0	49	66971	70051	70051	63419	3	63719	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	2520	1	78	1	1	69801	10000	30006	10	10	10	10000	40010	70052	70036	70052	70052	70052
50024	70051	524	0	0	0	0	0	0	0	1	0	1	0	0	0	70042	69719	59693	25	40010	30013	10001	30010	10000	615145	3342095	1	49	66971	70035	70051	63403	3	63719	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	0	0	0	0	0	2520	1	78	1	1	69818	10000	30006	10	10	10	10000	40010	70054	70052	70052	70054	70055
50024	70051	525	0	0	0	0	1	0	0	1	0	1	0	0	0	70042	69715	59693	25	40014	30010	10001	30010	10000	615145	3342095	0	49	66971	70051	70051	63421	3	63682	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	2	1	10000	0	0	0	4541	10000	1	0	1	0	0	2520	1	78	1	1	69818	10018	30003	10	10	10	10000	40010	70052	70052	70052	70052	70052
50024	70051	524	0	0	0	0	0	0	0	13	0	1	0	0	0	70042	69719	59695	25	40014	30010	10000	30010	10000	615145	3342095	0	49	66971	70035	70056	63424	3	63682	40010	30020	20000	60020	10000	70035	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	2	1	10001	0	0	2	1	10000	1	1	0	1	0	2520	1	64	1	3	69823	10001	30006	10	10	10	10000	40010	70052	70052	70052	70052	70052

Test 4: throughput

Count: 8

Code:

  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	26724	201	0	0	0	0	0	0	0	41	0	0	0	1	26714	2	18	18	0	25	80100	100	80000	100	80000	500	1170529	0	49	23652	26732	26714	6637	3	6690	80100	200	160000	200	80000	26732	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80035	0	0	0	38	80035	6	1	0	39	0	0	0	0	0	5110	2	16	2	2	26729	80057	9	9	2	80000	80100	26733	26733	26733	26733	26733
160204	26741	202	1	1	0	1	1	1	0	21	1	0	0	2	26799	2	0	0	12	25	80100	100	80000	100	80000	500	1170107	0	49	23627	26816	26722	6645	3	6680	80100	200	160000	200	80000	26731	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80035	0	0	0	38	80035	6	1	35	39	0	0	0	0	0	5110	2	16	2	2	26729	80057	9	9	2	80000	80100	26733	26715	26733	26733	26715
160204	26714	200	1	1	0	0	0	0	0	21	1	0	0	2	26789	2	18	18	12	25	80100	100	80000	100	80000	500	1170107	0	49	23642	26722	26722	6630	3	6680	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80035	0	0	0	35	80000	6	1	35	39	0	0	0	0	0	5110	2	16	2	2	26711	80057	9	9	2	80000	80100	26733	26733	26733	26733	26733
160204	26714	201	1	1	0	1	0	0	0	21	1	0	0	2	26699	2	18	18	14	25	80100	100	80000	100	80000	500	1168898	0	49	23642	26722	26722	6645	3	6680	80100	200	160000	200	80000	26707	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80035	0	0	0	0	80000	6	1	35	39	0	0	0	0	0	5110	2	16	2	2	26729	80057	9	9	2	80000	80100	26733	26733	26733	26733	26733
160204	26732	200	1	1	0	0	0	0	0	65	0	0	0	0	26713	2	18	18	12	25	80100	100	80000	100	80000	500	1170107	0	49	23642	26722	26722	6630	3	6680	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	39	80035	0	0	0	35	80035	6	1	35	39	0	0	0	0	0	5110	2	16	2	2	26729	80058	9	9	2	80000	80100	26715	26733	26715	26715	26715
160204	26732	200	1	0	0	1	0	0	0	65	1	0	0	2	26713	2	18	18	12	25	80100	100	80000	100	80000	500	1168880	0	49	23642	26722	26707	6645	3	6680	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80035	0	0	0	35	80035	6	1	0	39	0	0	0	0	0	5110	2	16	2	2	26729	80057	9	9	2	80000	80100	26715	26733	26715	26733	26733
160204	26714	200	1	1	0	0	0	0	0	21	1	0	0	2	26709	2	18	18	0	25	80100	100	80000	100	80000	500	1170107	0	49	23642	26722	26722	6645	3	6665	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80000	0	0	0	35	80000	0	1	35	39	0	0	0	0	0	5110	2	16	2	2	26729	80057	9	9	2	80000	80100	26733	26733	26733	26733	26733
160204	26732	200	1	0	0	0	0	0	0	65	0	0	0	2	26713	0	18	18	12	25	80100	100	80000	100	80000	500	1170107	0	49	23642	26722	26713	6630	3	6665	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80035	0	0	0	35	80035	6	1	38	39	0	0	0	0	0	5110	2	16	2	2	26729	80057	9	9	2	80000	80100	26745	26733	26734	26733	26734
160204	26732	215	1	1	0	0	0	0	0	65	0	1	0	2	26713	0	18	18	0	25	80100	100	80000	100	80000	500	1170107	0	98	23642	26722	26707	6645	3	6680	80100	200	160000	200	80000	26707	35	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	39	80035	0	0	0	35	80000	6	1	35	39	0	0	0	0	0	5110	2	16	2	2	26729	80057	9	9	2	80000	80100	26733	26715	26733	26733	26733
160204	26732	200	1	0	0	0	1	0	0	65	0	0	0	2	26713	2	18	0	12	25	80100	100	80000	100	80000	500	1170107	0	49	23627	26722	26722	6645	3	6680	80100	200	160000	200	80000	26707	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80000	0	0	0	35	80000	0	1	35	0	0	0	0	0	0	5110	2	16	2	2	26729	80057	9	9	0	80000	80100	26733	26715	26733	26733	26733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	19	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	26729	200	0	1	0	44	1	0	1	26740	2	12	1	19	25	80010	10	80000	10	80000	50	1168880	49	23651	0	26707	26731	6676	3	6711	80010	20	160000	20	80000	26731	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80038	0	38	80039	6	1	39	43	5020	5	16	5	5	26728	80038	14	10	7	80000	80010	26708	26708	26732	26708	26708
160024	26727	201	0	0	0	44	0	0	0	26692	2	1	1	16	25	80010	10	80000	10	80000	50	1168880	49	23627	0	26731	26707	6676	3	6707	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	0	80038	6	0	0	0	5020	3	16	5	4	26730	80039	14	10	7	80000	80010	26709	26732	26732	26728	26708
160024	27137	200	0	0	0	0	0	0	1	26716	0	1	1	19	25	80010	10	80000	10	80000	50	1174887	49	23651	0	26707	26731	6676	3	6687	80010	20	160000	20	80000	26727	35	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	80000	0	0	80000	6	1	38	44	5020	4	16	6	3	26704	80000	14	0	0	80000	80010	26732	26708	26732	26732	26729
160024	26707	201	0	0	0	0	1	0	1	26714	2	0	0	19	25	80010	10	80000	10	80000	50	1168880	49	23651	0	26727	26727	6653	3	6711	80010	20	160000	20	80000	26731	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	0	80038	6	1	39	44	5020	5	16	5	3	26707	80039	14	10	0	80000	80010	26735	26708	26708	26732	26708
160024	26731	200	0	0	0	45	0	0	1	26692	2	12	1	16	25	80010	10	80000	10	80000	50	1168627	49	23651	0	26731	26707	6676	3	6687	80010	20	160000	20	80000	26735	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	38	80038	6	1	39	0	5020	5	16	3	5	26728	80038	14	10	7	80000	80010	26728	26708	26708	26732	26732
160024	26731	200	0	0	0	0	1	0	1	26712	2	1	1	19	25	80010	10	80000	10	80000	50	1174887	49	23627	0	26707	26731	6676	3	6711	80010	20	160000	20	80000	26731	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	39	80039	6	1	0	0	5020	3	16	3	5	26728	80038	0	0	7	80000	80010	26728	26728	26708	26732	26708
160024	26727	200	0	0	0	44	0	0	0	26716	2	1	1	0	25	80010	10	80000	10	80000	50	1169085	49	23627	0	26731	26727	6653	3	6687	80010	20	160000	20	80000	26731	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	1	38	80039	6	1	39	0	5020	5	16	3	5	26724	80038	0	10	7	80000	80010	26708	26732	26732	26732	26708
160024	26731	200	0	0	0	0	1	0	1	26692	2	1	12	0	25	80010	10	80000	10	80000	50	1174628	49	23647	0	26731	26727	6653	3	6687	80010	20	160000	20	80000	26731	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	41	80038	6	0	39	44	5020	5	16	5	3	26704	80038	0	14	7	80000	80010	26708	26708	26732	26728	26732
160024	26731	200	0	0	0	44	1	0	0	26692	2	12	0	19	25	80010	10	80000	10	80000	50	1168880	49	23651	0	26707	26707	6676	3	6711	80010	20	160000	20	80000	26731	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	0	41	80038	6	1	0	0	5020	3	16	5	3	26728	80038	14	0	7	80000	80010	26708	26708	26728	26708	26708
160024	26731	200	0	0	0	0	0	0	0	26716	2	0	1	19	25	80010	10	80000	10	80000	50	1168880	49	23651	0	26707	26707	6676	3	6711	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	0	38	80038	6	0	0	44	5020	5	16	3	5	26704	80038	14	10	4	80000	80010	26732	26708	26708	26732	26728

LDNP (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations