Firestorm: SDIV (medium, 64-bit) measurements

Code:

  sdiv x0, x1, x2

Initialization

  mov x1, #0xffffffff80000000
  mov x2, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2039	15	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	3	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	16	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	6	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	16	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	2	3	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040

Test 2: Latency 1->2

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov x1, #0xffffffff80000000
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	100035	749	0	0	0	61	91261	25	30129	30100	30100	9493443	0	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	2	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	1	0	89	91261	25	30100	30100	30100	9493443	0	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	1	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	276	61	91261	25	30100	30100	30100	9493443	0	49	96955	100035	100035	95873	3	96306	30203	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	61	91261	25	30100	30100	30100	9493443	0	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	94	91261	25	30100	30100	30100	9493443	0	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	726	91261	25	30100	30100	30100	9493443	0	49	93915	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100076	749	0	0	0	61	91261	25	30100	30100	30100	9493443	0	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	61	91261	25	30100	30100	30100	9493443	0	49	96955	100035	100035	95873	20	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	1008	726	91261	25	30100	30100	30100	9493443	0	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	61	91261	25	30100	30100	30100	9493443	0	49	96955	100035	100035	95873	3	96242	30100	30200	60486	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	100035	749	0	984	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	16	16	7	16	99714	30007	30010	100036	100036	100036	100036	100036
30024	100035	750	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	4	0	0	0	1890	16	16	16	15	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60284	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	13	16	7	15	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	16	16	16	15	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	16	16	13	16	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	246	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	16	16	13	16	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30022	10	9	10	30010	10	0	0	0	0	1	1890	16	16	15	15	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	750	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	0	100035	100035	95885	9	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	13	16	16	13	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	0	100066	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	14	16	7	14	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	16	16	13	16	99714	30000	30010	100036	100036	100036	100036	100036

Test 3: Latency 1->3

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov x1, #0xffffffff80000000
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	100035	749	0	0	0	61	91145	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95867	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	2	17	1	2	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	61	91261	25	30100	30100	30201	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	61	91261	25	30100	30100	30100	9493443	0	49	96955	100035	100035	95873	3	96262	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	726	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	3	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	2	2	2098	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	82	91261	25	30100	30100	30100	9493443	0	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	2	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	726	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	93925	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	100035	750	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1890	5	16	3	5	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	1839	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1890	3	16	5	3	99714	30000	30010	100036	100036	100036	100067	100036
30024	100035	749	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1890	4	16	4	7	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1890	3	16	3	5	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	1249	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1890	7	16	7	4	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1890	3	16	3	5	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1890	3	16	7	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	726	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1890	5	16	5	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1	1890	5	16	3	5	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	3	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1890	7	16	3	5	99714	30000	30010	100036	100067	100036	100036	100036

Test 4: throughput

Count: 8

Code:

  sdiv x0, x8, x9
  sdiv x1, x8, x9
  sdiv x2, x8, x9
  sdiv x3, x8, x9
  sdiv x4, x8, x9
  sdiv x5, x8, x9
  sdiv x6, x8, x9
  sdiv x7, x8, x9

Initialization

  mov x8, #0xffffffff80000000
  mov x9, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	160039	1199	0	0	726	79950	25	80100	80100	80100	4399225	49	156959	160078	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	1	0	5113	0	2	16	1	1	3	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	1	67	79950	25	80100	80100	80100	4399225	49	156959	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5113	3	1	16	1	1	3	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	1	67	79950	25	80100	80100	80100	4399225	49	156959	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5113	3	1	16	1	1	3	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	1	2188	79950	25	80100	80100	80310	4399225	98	156959	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5113	3	1	16	1	1	3	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	1	2955	79950	25	80100	80100	80100	4399225	49	156959	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5113	3	1	16	1	1	3	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	1	1140	79950	25	80100	80100	80100	4399225	49	156959	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5113	3	1	16	1	1	3	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	1	2835	79950	25	80100	80100	80100	4399225	49	156959	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	1	0	0	0	0	5113	3	1	16	1	1	3	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	1	2407	79950	25	80100	80100	80100	4399225	49	156959	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5113	3	1	16	1	1	3	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	1	2374	79950	25	80100	80100	80100	4399440	49	156959	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5113	3	1	16	1	1	3	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	1	3041	79950	25	80100	80100	80100	4399225	49	156959	160080	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5113	3	1	16	1	1	3	159980	80000	80100	160040	160040	160040	160040	160040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0f	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	160039	1199	0	0	0	0	0	0	4	12	0	726	79950	25	80010	80010	80010	4398775	1	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160237	261	1	1	80021	10	9	10	80010	10	0	0	3	0	0	0	0	0	0	5020	0	9	16	6	3	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	3	0	0	0	0	5020	0	3	16	5	3	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1198	0	0	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156959	160039	160039	150003	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5042	0	5	16	5	3	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	1	0	4	0	0	0	61	79950	110	80010	80010	80010	4398775	0	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	3	0	3	0	0	0	0	0	0	5020	0	5	16	3	5	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	0	0	0	0	9	0	61	79950	25	80010	80010	80010	4398775	0	49	157156	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	0	3	16	3	5	159980	80000	80010	160237	160040	160040	160040	160040
80024	160039	1199	0	0	0	0	1	4	0	0	0	726	79950	111	80010	80010	80010	4398775	0	49	157008	160039	160039	149923	12	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	1	0	0	0	0	0	1	5020	0	3	16	5	5	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1198	0	1	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156959	160236	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	2	0	0	0	0	0	0	0	5020	0	3	16	4	5	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	0	0	0	0	0	0	726	79938	25	80062	80010	80010	4398775	0	49	156959	160039	160039	150000	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	0	5	16	5	3	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	0	0	0	0	57	352	61	79950	25	80010	80010	80010	4398775	0	49	156959	160039	160237	149923	3	150155	80010	80020	160020	160039	261	5	1	80021	10	9	10	80010	10	0	0	4	0	0	0	0	0	0	5020	0	5	16	3	5	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1198	0	1	0	0	0	0	0	0	0	557	79950	25	80010	80010	80010	4398775	0	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	5	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	0	3	48	3	5	159980	80000	80010	160040	160040	160040	160040	160040

SDIV (medium, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations