Firestorm: DMB (NSHLD) measurements

Code:

  dmb nshld

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst barrier (9c)	st unit uop (a7)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	3027	23	0	3020	2009	1000	1000	1000	6000	1	33	0	3027	3035	3	2885	1000	1000	3026	3035	1	1	1001	1000	1000	0	73	1	16	1	1	3022	1000	3036	3028	3036	3028	3036
1004	3035	22	0	3011	2001	1000	1000	1000	6000	1	42	0	3035	3025	3	2885	1000	1000	3025	3035	1	1	1001	1000	1000	0	73	1	16	1	1	3032	1000	3027	3036	3028	3036	3028
1004	3035	22	0	3012	2001	1000	1000	1000	6000	1	33	0	3027	3035	3	2893	1000	1000	3035	3027	1	1	1001	1000	1000	0	73	1	16	1	1	3032	1000	3026	3036	3027	3036	3028
1004	3026	23	0	3020	2009	1000	1000	1000	6000	0	42	0	3035	3026	3	2885	1000	1000	3026	3035	1	1	1001	1000	1000	0	73	1	16	1	1	3023	1000	3036	3027	3036	3028	3036
1004	3027	22	135	3020	2009	1000	1000	1000	6000	0	33	0	3035	3027	3	2884	1000	1000	3027	3035	1	1	1001	1000	1000	0	73	1	16	1	1	3032	1000	3028	3036	3028	3036	3027
1004	3035	23	0	3012	2001	1000	1000	1000	6000	0	34	0	3026	3035	3	2893	1000	1000	3035	3027	1	1	1001	1000	1000	0	73	1	16	1	1	3032	1000	3028	3036	3028	3036	3027
1004	3026	23	9	3011	2000	1000	1000	1000	6000	1	34	0	3027	3035	3	2893	1000	1000	3035	3025	1	1	1001	1000	1000	0	73	1	16	1	1	3024	1000	3036	3028	3036	3028	3036
1004	3027	23	0	3020	2009	1000	1000	1000	6000	1	34	0	3026	3035	3	2893	1000	1000	3035	3027	1	1	1001	1000	1000	0	73	1	16	1	1	3024	1000	3028	3036	3027	3036	3027
1004	3035	23	0	3011	2001	1000	1000	1000	6000	1	34	0	3035	3027	3	2884	1000	1000	3027	3035	1	1	1001	1000	1000	15	73	1	16	1	1	3023	1000	3036	3027	3036	3028	3036
1004	3025	22	0	3011	2001	1000	1000	1000	6000	1	42	0	3035	3025	3	2885	1000	1000	3025	3035	1	1	1001	1000	1000	0	73	1	16	1	1	3032	1000	3027	3036	3026	3036	3028

Code:

  dmb nshld

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.9043

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst barrier (9c)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	29036	217	0	0	0	0	0	0	29020	18906	10100	100	10000	100	10000	500	59800	0	49	25955	29135	29027	3	27843	10100	200	10000	200	29135	23207	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	791	0	1	73	2	2	29919	25	10000	100	29969	29884	29977	29992	29956
10204	29775	225	1	1	7	7	933	704	29925	19612	10185	118	10062	125	10056	611	62000	0	49	26767	30082	29940	26	28703	10188	200	10056	202	29907	29987	8	1	10201	100	99	100	100	10000	100	0	2	10032	0	4413	3	710	0	1	40	1	1	29040	0	10000	100	29136	29028	29136	29037	29136
10204	29273	218	0	0	0	0	6	0	29027	18900	10100	100	10000	100	10000	500	59800	0	49	25963	29135	29034	3	27735	10100	200	10000	200	29028	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	710	0	1	16	1	1	29024	0	10000	100	29136	29043	29136	29044	29136
10204	29036	218	0	0	0	0	0	0	29120	19008	10100	100	10008	100	10000	500	59800	0	49	26055	29034	29135	3	27744	10100	200	10000	200	29135	23214	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	710	0	1	16	1	1	29033	0	10000	100	29136	29044	29136	29196	29136
10204	29042	226	0	0	0	0	3	0	29120	19008	10100	100	10000	100	10000	500	60864	0	49	26055	29034	29135	3	27843	10100	200	10000	200	29135	23222	1	1	10201	100	99	100	100	10000	100	13	0	10000	1	0	0	710	0	1	16	1	1	29040	0	10000	100	29136	29028	29136	29037	29136
10204	29035	219	0	0	0	0	3	0	29028	18908	10100	100	10000	121	10000	500	59800	0	49	25955	29135	29027	3	27742	10100	200	10000	200	29035	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	710	465	1	16	1	1	29132	0	10000	100	29045	29136	29044	29136	29044
10204	29036	272	0	0	0	0	0	0	29027	18900	10100	100	10000	100	10000	500	59800	0	49	25955	29135	29044	3	27751	10100	200	10000	200	29043	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	126	0	710	0	1	16	1	1	29132	0	10000	100	29044	29136	29035	29136	29044
10204	29135	217	0	0	0	0	0	0	29028	18908	10100	100	10000	100	10000	500	59800	0	49	25963	29135	29043	3	27743	10100	200	10000	200	29035	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	135	0	710	0	1	16	1	1	29132	0	10000	100	29029	29136	29035	29136	29028
10204	29135	217	0	0	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	61261	0	49	26055	29027	29135	3	27843	10100	200	10000	200	29135	23221	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	710	0	1	16	1	1	29032	0	10000	100	29136	29037	29136	29043	29136
10204	29135	217	0	0	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	59800	0	49	25948	29135	29034	3	27752	10100	200	10000	200	29042	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	710	0	1	16	1	1	29031	0	10000	100	29136	29036	29136	29045	29136

1000 unrolls and 10 iterations

Result (median cycles for code): 2.9951

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst barrier (9c)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	29888	224	0	0	0	0	0	0	0	0	29851	19830	10025	10	10000	10	10000	50	59982	49	26871	29866	29951	3	28596	10010	20	10000	20	29866	29951	1	1	10021	10	9	10	10	10000	10	0	0	0	10000	0	6	0	0	0	640	5	16	5	5	29948	0	10000	10	29865	29952	29867	29952	29868
10024	29951	223	0	0	0	0	0	0	0	0	29850	19831	10010	10	10000	10	10000	50	59982	49	26787	29951	29865	3	28595	10010	20	10000	20	29867	29951	1	1	10021	10	9	10	10	10000	10	0	0	0	10000	0	93	0	0	0	640	6	16	6	6	29861	0	10000	10	29952	29868	29952	29867	29952
10024	29867	224	0	0	0	0	0	0	0	0	29852	19831	10010	10	10000	10	10000	50	59982	49	26871	29867	29951	3	28681	10010	20	10000	20	29951	29864	1	1	10021	10	9	10	10	10000	10	0	0	0	10000	0	3	0	0	0	640	6	16	6	5	29948	0	10000	10	29867	29952	29867	29952	29868
10024	29951	224	0	0	0	0	0	0	0	0	29936	19915	10010	10	10000	10	10000	50	59984	49	26871	29866	29951	3	28681	10010	20	10000	20	29951	29867	1	1	10021	10	9	10	10	10000	10	0	0	0	10000	0	153	0	0	0	640	6	16	6	6	29864	0	10000	10	29952	29865	29952	29867	29952
10024	29867	224	0	0	0	0	0	0	0	0	29852	19832	10010	10	10000	10	10000	50	61043	49	26786	29951	29866	3	28595	10010	20	10000	20	29865	29951	1	1	10021	10	9	10	10	10000	10	0	0	0	10000	0	0	0	0	0	640	6	16	6	5	29948	0	10000	10	29866	29952	29865	29952	29868
10024	29951	223	0	0	0	0	0	0	0	0	29852	19829	10010	10	10000	10	10000	50	59982	49	26871	29864	29951	3	28681	10010	20	10000	20	29951	29866	1	1	10021	10	9	10	10	10000	10	0	0	0	10000	0	6	0	0	0	640	4	16	6	6	29864	0	10000	10	29866	29952	29866	29952	29866
10024	29867	224	0	0	0	0	0	0	0	0	29936	19915	10010	10	10000	10	10000	50	59982	49	26785	29951	29864	3	28596	10010	20	10000	20	29867	29951	1	1	10021	10	9	10	10	10000	10	0	0	0	10000	0	0	0	0	0	640	6	16	6	6	29948	0	10000	10	29868	29952	29867	29952	29868
10024	29951	224	0	0	0	0	0	0	0	0	29936	19915	10010	10	10000	10	10000	50	59982	49	26871	29866	29951	3	28681	10010	20	10000	20	29951	29867	1	1	10021	10	9	10	10	10000	10	0	0	0	10000	0	6	0	0	0	640	6	16	5	5	29862	0	10000	10	29952	29867	29952	29868	29952
10024	29867	224	0	0	0	0	0	0	0	0	29936	19915	10010	10	10000	10	10000	50	59982	49	26785	29951	29865	3	28597	10010	20	10000	20	29866	29951	1	1	10021	10	9	10	10	10000	10	0	0	0	10000	0	6	0	0	0	640	5	16	6	6	29948	0	10000	10	29868	29952	29867	29952	29868
10024	29951	223	0	0	0	0	0	0	0	0	29851	19915	10010	10	10000	10	10000	50	60859	49	26871	29864	29951	3	28681	10010	20	10000	20	29951	29867	1	1	10021	10	9	10	10	10000	10	0	0	0	10000	0	0	0	0	0	640	6	16	5	5	29948	0	10000	10	29868	29952	29868	29952	29867

DMB (NSHLD)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations