Firestorm: MVN (register, asr, 64-bit) measurements

Code:

  mvn x0, x0, asr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	1	1	0	3	68	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	6	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	1	1	0	3	68	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	1	1	0	3	68	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	1	1	0	3	68	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	1	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	1	1	0	3	68	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	1	1	0	3	68	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	1	1	0	3	112	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	11	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	1	1	0	3	200	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	1	1	0	3	133	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	1	1	0	3	68	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  mvn x0, x0, asr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	0	0	0	0	126	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	2	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	103	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	82	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	149	0	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	296	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20081	20036	20036
10204	20035	150	0	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	124	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	75	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	661	4	63	6	4	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	0	0	126	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	5	63	5	6	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	0	0	189	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	6	63	6	5	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	0	0	189	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	6	63	6	5	19792	20000	10010	20036	20036	20069	20036	20036
10024	20035	150	0	0	0	0	0	0	0	0	0	82	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	5	63	5	6	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	1	0	0	0	0	234	10009	19743	25	20010	20010	10010	185310	49	17001	20081	20080	18455	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	2	3	0	0	0	0	2	662	5	63	6	5	19792	20022	10010	20082	20081	20080	20036	20036
10024	20035	150	0	0	0	0	0	0	0	0	0	126	10000	19743	25	20010	20010	10157	185310	49	16955	20079	20035	18451	8	18734	10155	10188	10188	20081	42	2	1	10021	10	9	10	10010	10	2	0	0	0	0	0	0	752	9	122	8	7	19905	20090	10010	20217	20264	20262	20264	20170
10024	20262	152	0	0	1	1	5	5	540	440	0	2604	10036	19789	125	20124	20121	10736	194000	49	17180	20262	20260	18459	21	18800	10596	10845	10851	20217	42	6	1	10021	10	9	10	10010	10	0	0	1	1	0	10040	2	726	8	99	8	10	19953	20022	10010	20218	20299	20081	20267	20218
10024	20263	151	1	1	1	0	5	5	660	440	0	2435	10036	19777	125	20101	20122	10623	194013	49	17182	20216	20292	18460	23	18799	10737	10855	10703	20263	42	6	1	10021	10	9	10	10010	10	0	0	0	0	2	9930	0	752	7	103	10	4	19998	20113	10010	20264	20175	20265	20306	20305
10024	20263	151	1	1	0	0	6	6	672	528	0	3088	10054	19795	151	20146	20146	10884	195757	49	17183	20306	20297	18462	30	18812	10010	11015	11021	20306	42	2	1	10021	10	9	10	10010	10	0	0	0	1	2	13955	0	769	7	103	8	6	19930	20135	10010	20353	20310	20310	20081	20309

Test 3: throughput

Count: 8

Code:

  mvn x0, x8, asr #17
  mvn x1, x8, asr #17
  mvn x2, x8, asr #17
  mvn x3, x8, asr #17
  mvn x4, x8, asr #17
  mvn x5, x8, asr #17
  mvn x6, x8, asr #17
  mvn x7, x8, asr #17

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26768	200	0	0	0	0	0	0	0	28	80031	26146	28	160182	160182	80262	161906	1	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	1	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	0	51	80031	26146	28	160182	160182	80262	161906	1	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	4	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26732	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	0	28	80031	26146	28	160182	160182	80262	161906	0	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	0	28	80031	26146	28	160182	160182	80262	161906	1	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5128	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26731	200	0	0	0	0	0	0	0	133	80031	26146	28	160182	160182	80262	161906	1	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	0	28	80031	26146	28	160182	160182	80262	161906	0	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	0	28	80031	26146	28	160182	160182	80262	161906	1	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	0	28	80031	26146	28	160182	160182	80262	161906	1	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26728	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	0	28	80031	26146	28	160182	160182	80262	161906	0	0	49	23652	26732	26732	16651	7	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	0	70	80031	26146	28	160182	160182	80262	161906	1	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	26734	200	0	0	145	80000	21280	25	160010	160010	80010	163142	1	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	4	22	4	2	3	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	22	4	3	2	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26769	16625	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	2	22	4	3	4	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	22	4	3	3	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	1	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	22	3	3	2	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	1	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	22	4	3	3	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	3	0	5020	2	22	3	3	2	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	1	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	22	3	3	3	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	22	3	3	2	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	1	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	22	4	3	3	26704	160000	0	80010	26712	26712	26712	26712	26712

MVN (register, asr, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations