Firestorm: SMSUBL measurements

Code:

  smsubl x0, w0, w1, x2

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	3033	22	0	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	0	73	0	3	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	0	73	0	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	0	73	0	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	0	61	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	0	73	0	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	6	61	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	0	73	0	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	29	0	0	292	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	0	73	0	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	24	0	0	61	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1051	3000	3033	380	1	1	1001	1000	0	0	0	0	73	0	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	327	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	0	73	0	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	0	73	0	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	0	73	0	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034

Test 2: Latency 1->2

Code:

  smsubl x0, w0, w1, x2

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	224	0	0	61	19922	25	10100	10100	10100	828940	49	26953	0	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	1	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	19922	25	10131	10100	10100	828940	49	26953	0	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	29939	10026	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	19922	25	10100	10100	10100	828940	49	26953	0	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	19922	25	10100	10100	10100	828940	49	26953	0	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	19922	25	10100	10100	10100	828940	49	26953	0	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	36	0	61	19922	25	10100	10100	10100	828940	49	26953	0	30064	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	21	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	19922	25	10100	10100	10100	828940	49	26953	0	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	19922	25	10100	10100	10100	828940	49	26953	0	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	1	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	19922	25	10100	10100	10100	828940	49	26953	0	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	19922	25	10100	10100	10100	828940	49	26953	0	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	180	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	591	61	19922	25	10010	10010	10010	828490	1	2	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	1	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	438	61	19922	25	10010	10010	10010	828490	1	1	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	1	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	276	61	19922	25	10010	10010	10010	828490	1	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	1	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	426	61	19922	25	10010	10010	10010	828490	1	1	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	1	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	414	61	19922	25	10010	10010	10010	828490	1	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	30200	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	1	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	450	61	19922	25	10010	10010	10010	828490	0	1	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	1	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	444	61	19922	25	10010	10010	10010	828490	0	1	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	1	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	489	61	19922	25	10010	10010	10010	828490	1	1	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	1	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	690	61	19922	25	10010	10010	10010	828490	1	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	1	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	447	61	19922	25	10010	10010	10010	828490	1	1	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	0	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034

Test 3: Latency 1->3

Code:

  smsubl x0, w1, w0, x2

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	2	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	3	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	0	0	61	19922	25	10100	10100	10100	828940	3	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	6	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	1	87	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	3	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	6	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	6	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	6	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	6	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	9	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30077	225	1	624	708	19910	47	10010	10033	10043	828490	1	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	12	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	666	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	588	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10043	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	0	462	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	420	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	402	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	216	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034

Test 4: Latency 1->4

Code:

  smsubl x0, w1, w2, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	51	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	15	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	3	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	9	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10037	75	0	0	117	48	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	48	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	1	0	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	48	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	48	25	10010	10010	10010	70048	1	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	69	25	10010	10010	10010	70048	1	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	69	48	25	10010	10010	10010	70048	1	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	69	25	10010	10010	10010	70048	1	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	48	25	10010	10010	10010	70048	1	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	231	48	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	216	48	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038

Test 5: throughput

Count: 8

Code:

  smsubl x0, w8, w9, x9
  smsubl x1, w8, w9, x9
  smsubl x2, w8, w9, x9
  smsubl x3, w8, w9, x9
  smsubl x4, w8, w9, x9
  smsubl x5, w8, w9, x9
  smsubl x6, w8, w9, x9
  smsubl x7, w8, w9, x9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80036	599	0	46	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	17	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	1	12	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	46	25	80100	80100	80100	400500	0	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	126	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	46	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	3	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	46	25	80145	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	3	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	46	25	80100	80142	80100	400500	1	49	76955	3	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	1271	0	5110	1	24	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	67	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	12	0	5110	1	17	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	46	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	1	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	46	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	1	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	46	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	2	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	67	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	2	3	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80075	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80035	600	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	5020	5	16	5	3	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	711	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	5020	5	16	3	5	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	46	25	80010	80010	80010	400050	1	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	16	3	5	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	46	25	80031	80073	80077	401655	0	49	77815	80716	80624	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	5020	5	16	3	5	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	711	25	80010	80010	80010	400050	1	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	16	5	5	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	5020	5	16	5	3	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	46	25	80010	80010	80010	400050	1	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	16	3	5	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	46	25	80010	80010	80010	400050	1	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	1	0	0	5020	3	16	3	5	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	9	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80076	164	1	1	80021	10	9	10	80010	10	0	0	0	5020	5	16	5	3	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	5020	5	16	3	5	80032	80000	80010	80036	80036	80036	80036	80036

SMSUBL

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations