Firestorm: LDRSB (pre-index, 64-bit) measurements

Code:

  ldrsb x0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	20	22	23	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1054	7	0	0	0	55	20	1	0	0	4	12	1025	19	0	12	1	14	25	2000	1000	1000	1000	1000	52848	45827	1041	1040	700	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1030	0	0	80	1047	10	1	38	6	19	1017	72	9	16	55	0	0	0	73	2	16	2	2	1028	1000	45	42	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	49	24	0	0	8	0	0	1025	0	0	1	6	16	25	2000	1000	1000	1000	1000	52844	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1010	6	0	50	1031	5	0	10	6	15	1019	30	5	11	31	0	0	0	73	2	16	2	2	1037	1000	43	29	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	61	16	1	0	0	0	12	1025	0	0	0	0	19	25	2000	1000	1000	1000	1000	52844	45824	1040	1057	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1000	0	0	55	1021	6	0	22	6	12	1019	30	6	11	39	0	0	0	73	2	16	2	2	1037	1000	54	54	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	64	12	1	0	0	0	0	1025	4	0	1	0	11	25	2000	1000	1000	1000	1000	52840	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1015	0	0	48	1046	4	0	30	12	7	1049	36	6	9	41	0	0	0	73	2	16	2	2	1037	1000	72	40	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	47	0	0	0	0	0	0	1025	6	0	6	4	18	25	2000	1000	1000	1000	1000	52836	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1036	0	0	39	1034	2	0	26	8	14	1038	48	6	7	31	0	0	0	73	2	16	2	2	1037	1000	36	38	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	1	63	14	0	0	0	0	0	1025	9	0	0	1	24	25	2000	1000	1000	1000	1000	52840	45824	1059	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1022	0	0	50	1028	3	0	20	12	12	1037	50	4	7	34	0	0	4	73	2	16	2	2	1037	1000	37	35	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	1	0	47	26	1	0	0	0	0	1025	27	0	2	0	14	25	2000	1000	1000	1000	1000	52828	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1020	12	0	64	1013	0	0	0	0	9	1011	24	7	16	31	0	0	0	73	2	16	2	2	1037	1000	43	42	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	0	39	14	1	0	0	0	0	1025	11	1	1	1	9	25	2000	1000	1000	1000	1000	52832	45824	1056	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1012	0	0	32	1028	4	0	26	6	15	1027	24	5	32	41	6	0	0	73	2	16	2	2	1037	1000	31	29	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	40	0	1	0	0	2	4	1025	0	2	3	3	19	25	2000	1000	1000	1000	1000	52840	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1012	0	0	33	1022	1	0	26	6	17	1030	30	5	17	63	0	0	0	73	2	16	2	2	1037	1000	32	31	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	57	34	1	0	0	2	0	1025	9	1	3	4	20	25	2000	1000	1000	1000	1000	52844	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	2	1020	12	0	39	1020	2	0	30	10	14	1031	35	4	10	55	0	0	0	73	2	16	2	2	1037	1000	39	36	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1919

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72077	540	2	0	0	0	0	1	0	0	446	0	827	1	720	2	128	71873	815	6	2	71792	25	50815	40616	10146	40100	10000	613366	2729766	49	68826	71996	71843	65368	3	65621	50100	40200	10000	70200	10000	72073	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10858	6	144	479	10646	264	10	886	44	28	10936	130	9	132	3	4	9	0	0	2610	2	58	1	1	71903	40548	1171	1123	1132	10000	40100	71983	71901	71760	71956	71832
50204	72032	538	2	0	0	0	0	0	0	0	436	0	832	1	712	2	120	71946	795	4	3	71885	25	50700	40608	10144	40100	10000	613957	2722095	49	69053	71794	71808	65459	3	65664	50100	40200	10000	70200	10000	71949	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10927	3	133	487	10655	278	12	923	42	33	10875	136	7	134	3	0	3	0	0	2610	1	63	1	1	71939	40496	1107	1094	1144	10000	40100	71741	71978	71926	71932	72092
50204	71974	538	3	3	0	0	0	0	0	0	416	0	826	1	720	3	88	71910	784	3	3	71726	25	50785	40568	10137	40100	10000	614663	2723213	49	68779	72122	72003	65406	3	65565	50100	40200	10000	70200	10000	71878	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10884	3	155	485	10635	241	12	876	46	35	10896	128	8	134	3	3	3	0	0	2610	1	63	1	1	71738	40512	1114	968	1056	10000	40100	72087	72013	72106	72054	71939
50204	72023	538	3	0	0	0	0	0	0	0	456	0	781	1	704	3	120	71885	804	5	4	71534	25	50850	40616	10134	40100	10000	615065	2731205	49	69040	71954	71910	65272	3	65674	50100	40200	10000	70200	10000	71910	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10868	6	150	493	10652	269	46	884	82	34	10904	124	8	121	3	0	3	0	0	2610	1	63	1	1	71731	40480	939	1039	1019	10000	40100	71901	71880	71864	71977	71953
50204	71824	539	2	0	0	0	0	0	0	0	459	0	802	1	704	2	116	71930	831	5	2	71732	25	50725	40572	10132	40100	10000	614874	2720767	49	68828	71687	71880	65202	3	65569	50100	40200	10000	70200	10000	71939	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10919	2	158	498	10608	274	13	883	134	25	10938	111	7	127	2	0	3	0	0	2610	1	63	1	1	71621	40492	1036	1141	1111	10000	40100	72049	71895	72005	72068	72031
50204	71916	539	2	2	0	0	0	0	0	0	381	0	827	1	704	2	108	71923	810	5	3	71722	25	50665	40672	10123	40100	10000	615538	2721136	49	68799	71893	71647	65411	3	65532	50100	40200	10000	70200	10000	71807	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10925	3	155	481	10631	259	8	862	44	18	10892	119	9	137	2	3	5	0	0	2610	1	63	1	1	71751	40532	1033	1087	888	10000	40100	71890	72053	71905	71992	72034
50204	71845	538	2	0	0	0	0	0	0	0	437	0	775	1	736	2	140	71825	802	6	2	71872	25	50835	40624	10135	40100	10000	614948	2725718	49	68788	72159	71954	65328	3	65643	50290	40200	10000	70200	10000	71991	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10878	3	153	482	10623	268	9	889	78	23	10899	131	8	117	2	3	4	0	0	2610	1	58	1	1	71793	40516	956	1082	1021	10000	40100	72120	72015	71960	72041	72067
50204	71955	540	2	1	1	0	0	0	0	0	464	0	826	1	736	2	108	71894	760	8	1	71751	25	50825	40616	10141	40100	10000	613512	2729633	49	68806	71790	72069	65570	3	65608	50100	40200	10000	70200	10000	71925	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10853	2	168	483	10641	263	12	921	72	28	10888	129	8	127	2	0	5	0	0	2610	1	64	1	1	71727	40504	1006	1140	1111	10000	40100	71839	72010	72019	72090	71995
50204	72036	539	2	1	2	0	0	0	0	0	449	0	807	1	704	2	96	71788	777	6	2	71573	25	50805	40652	10129	40100	10000	614398	2729724	49	68891	71798	72098	65316	3	65556	50100	40200	10000	70200	10000	71937	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10897	2	157	489	10624	262	11	931	112	40	10946	129	7	118	2	2	6	0	0	2610	1	58	1	0	71620	40496	952	1056	989	10000	40100	71850	71812	71958	72013	71918
50204	71881	538	2	1	0	0	0	0	0	0	430	0	826	1	760	2	96	71763	783	4	2	71561	25	50750	40664	10137	40100	10000	614662	2733070	49	68754	71971	71817	65435	3	65666	50100	40200	10000	70200	10000	71833	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10901	2	132	478	10642	252	10	883	48	33	10919	127	7	133	2	4	3	0	0	2610	1	57	1	1	71861	40588	1029	1071	1004	10000	40100	71900	71967	71814	71953	71972

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1955

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	20	22	24	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72483	539	0	0	0	0	0	0	0	455	814	1	0	736	0	100	71939	794	2	0	71491	48	50665	40550	10127	40010	10000	613816	2726004	1	49	68775	71703	71952	65342	3	65524	50010	40020	10000	70020	10000	71958	35	1	1	40021	10	9	10	10000	30010	10000	10	10908	0	155	490	10655	265	8	930	42	273	10892	123	2	119	0	0	5	2520	1	85	1	1	71797	40508	1009	1185	1050	10000	40010	71871	71916	71824	71948	71915
50024	71968	540	0	0	0	0	0	0	0	400	826	1	0	728	0	116	71828	792	4	0	71642	25	50630	40506	10132	40010	10000	614248	2731448	1	49	68637	71782	71932	65222	3	65700	50010	40020	10000	70020	10041	71882	35	1	1	40021	10	9	10	10000	30010	10000	10	10923	1	157	516	10644	270	7	940	48	46	10911	138	1	126	0	0	7	2520	1	85	2	1	71632	40568	1081	1032	1018	10000	40010	72021	71955	72015	72011	72179
50024	72038	539	0	0	0	0	0	0	0	423	826	1	0	744	0	132	71959	810	4	1	71701	25	50670	40570	10132	40010	10000	611261	2725208	1	49	68830	71995	72094	65333	3	65481	50010	40020	10000	70020	10000	71998	35	1	1	40021	10	9	10	10000	30010	10000	10	10930	0	146	504	10639	274	9	927	38	277	10875	132	4	126	0	0	5	2520	2	71	2	3	71733	40520	1059	1096	1002	10000	40010	71711	71939	71829	71697	71924
50024	72084	539	0	0	0	0	1	0	0	453	849	1	0	744	0	108	71767	809	3	0	71564	25	50630	40542	10122	40010	10000	612988	2729116	1	49	68943	71774	71801	65244	3	65394	50010	40020	10000	70020	10000	72024	35	1	1	40021	10	9	10	10000	30010	10000	10	10939	0	166	518	10614	259	10	909	48	57	10884	118	4	130	0	0	5	2520	3	71	1	2	71681	40480	964	1013	1051	10000	40010	71996	71822	72022	71899	71950
50024	72096	539	0	0	0	0	1	0	0	449	831	1	0	752	0	100	71735	783	3	0	71810	25	50650	40498	10125	40010	10000	613306	2719120	1	49	68807	71929	71853	65506	3	65570	50010	40020	10000	70020	10000	71711	35	1	1	40021	10	9	10	10000	30010	10000	10	10912	0	152	506	10663	255	9	916	48	73	10876	113	2	129	0	0	7	2520	1	71	2	3	71575	40480	1141	983	996	10000	40010	71812	71904	71947	71861	71889
50024	72125	538	0	0	0	0	0	0	0	427	819	1	0	624	0	96	71826	789	3	1	71582	25	50675	40522	10111	40010	10000	612395	2725150	1	49	68726	71958	72049	65510	3	65617	50010	40020	10000	70020	10000	71844	35	1	1	40021	10	9	10	10000	30010	10000	10	10874	0	147	521	10654	288	9	940	48	56	10890	124	3	118	0	0	5	2520	2	71	1	2	71713	40540	1043	1028	1089	10000	40010	72226	71808	71983	71779	72236
50024	72219	538	0	0	0	0	0	0	0	489	833	1	0	672	0	140	71828	796	3	0	71596	25	50708	40518	10127	40010	10000	612443	2729286	1	49	68823	71889	71916	65380	3	65507	50010	40020	10000	70020	10000	71718	35	1	1	40021	10	9	10	10000	30010	10000	10	10907	0	159	501	10651	272	8	880	46	110	10910	124	4	124	0	0	3	2520	2	71	2	1	71648	40496	1071	981	1062	10000	40010	71909	72038	71895	71744	71860
50024	71902	539	0	0	0	0	1	0	0	438	816	1	0	696	0	132	71729	789	3	0	71591	25	50665	40538	10127	40010	10000	613384	2717093	1	49	68859	71939	71777	65251	3	65649	50010	40020	10000	70020	10000	71892	35	1	1	40021	10	9	10	10000	30010	10000	10	10909	0	165	485	10634	250	8	893	44	59	10890	122	4	126	0	0	9	2520	1	85	1	1	71719	40544	1029	1095	1107	10000	40010	71935	72142	71934	72132	71958
50024	72004	539	0	0	0	0	0	0	0	453	819	1	0	720	0	96	71911	771	3	0	71646	25	50620	40510	10132	40010	10000	613618	2716150	1	49	68688	71849	72014	65223	3	65612	50010	40020	10000	70020	10000	71917	35	1	1	40021	10	9	10	10000	30010	10000	10	10896	0	150	518	10649	269	8	880	80	303	10929	125	3	125	1	0	3	2520	1	71	3	2	71903	40532	1009	1130	1053	10000	40010	72037	71849	71687	71971	71964
50024	72110	538	1	0	1	0	0	0	0	416	826	1	0	696	1	140	71710	805	2	1	71599	25	50620	40546	10137	40010	10000	612149	2722033	1	49	68760	71821	71892	65145	3	65302	50010	40020	10000	70020	10000	71870	35	1	1	40021	10	9	10	10000	30010	10000	10	10926	0	159	506	10653	246	11	906	80	53	10896	129	4	130	0	3	9	2520	3	71	1	3	71742	40544	914	1113	1067	10000	40010	71933	71761	71918	71843	71824

Test 3: throughput

Count: 8

Code:

  ldrsb x0, [x6, #8]!
  ldrsb x0, [x7, #8]!
  ldrsb x0, [x8, #8]!
  ldrsb x0, [x9, #8]!
  ldrsb x0, [x10, #8]!
  ldrsb x0, [x11, #8]!
  ldrsb x0, [x12, #8]!
  ldrsb x0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3641

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29856	220	1	0	0	0	1	0	7087	798	1	688	84	80	29086	765	411	2186	2098	1929	25	160163	80150	80000	80100	80000	400739	1280948	1	75	49	26019	29243	29388	8986	3	9293	160100	80200	80000	80200	80000	29153	35	1	1	80201	100	99	11	100	80000	100	80000	0	100	80886	18	406	5372	85572	725	19	918	44	5016	85732	808	131	5048	5374	14	0	3	5110	11	16	11	10	29330	30	80050	386	448	77	80000	80100	29037	29302	29180	29135	29259
160204	28988	220	1	0	0	1	0	0	6337	800	1	688	107	84	29205	788	426	2141	2092	1847	25	160150	80155	80000	80100	80000	400789	1292368	0	53	49	25934	28967	29296	9003	3	9236	160100	80200	80000	80200	80000	29136	35	1	1	80201	100	99	10	100	80000	100	80000	0	100	80901	18	373	5537	85697	722	15	891	162	5481	85960	746	133	5051	4697	16	0	4	5110	10	16	11	9	29175	33	80070	332	364	93	80000	80100	29379	29057	29133	29175	29251
160204	29582	218	1	0	0	0	1	0	7029	802	1	680	96	136	29316	795	386	2169	2152	1869	25	160146	80163	80000	80100	80000	400786	1287115	0	53	49	26320	29352	29203	9167	3	9367	160100	80200	80000	80200	80000	29084	35	1	1	80201	100	99	6	100	80000	100	80000	0	100	80876	18	382	5092	84610	689	14	866	36	5260	85467	726	129	5413	4859	17	0	11	5110	12	16	11	12	29334	23	80076	389	409	75	80000	80100	29208	29336	29384	29133	29405
160204	29036	217	1	0	0	0	0	0	6569	785	1	696	93	152	29173	783	416	2018	2357	1885	25	160154	80159	80000	80100	80000	400795	1278934	0	54	49	26003	29328	29086	9133	3	9168	160100	80200	80000	80200	80000	29036	35	1	1	80201	100	99	8	100	80000	100	80000	0	100	80923	18	375	5458	85466	725	15	893	26	4340	85415	772	122	4754	4532	18	0	3	5110	10	16	12	10	29366	34	80060	305	388	78	80000	80100	29113	29095	29256	29027	29273
160204	29077	218	1	0	0	1	0	0	6223	809	1	712	81	112	29195	760	390	2102	1991	1891	25	160139	80172	80000	80100	80000	400785	1288246	0	57	49	26198	29195	29066	9146	3	9172	160100	80200	80000	80200	80000	29044	35	1	1	80201	100	99	7	100	80000	100	80000	0	100	80929	19	443	5704	85291	730	17	948	24	5121	86116	789	132	4769	5598	17	0	0	5110	10	16	12	10	29230	42	80059	414	372	87	80000	80100	29132	29114	29247	29091	29141
160204	29348	217	1	0	0	0	0	0	6550	778	1	672	95	124	29318	771	359	2170	2149	1960	25	160156	80166	80000	80100	80000	400788	1289012	1	64	49	26383	29171	29394	9143	3	9273	160100	80200	80000	80200	80000	29243	35	1	1	80201	100	99	14	100	80000	100	80000	0	100	80916	16	362	5249	85304	714	16	868	82	5091	85895	764	117	5024	4663	19	0	3	5110	7	16	10	10	29186	24	80062	368	334	83	80000	80100	29326	29361	29185	29409	29291
160204	29067	219	1	0	0	0	1	0	6821	805	1	688	90	108	29171	809	397	2046	2213	1889	25	160159	80170	80000	80100	80000	400744	1279967	0	56	49	26171	29234	29067	9199	3	9303	160100	80200	80000	80200	80000	29183	35	1	1	80201	100	99	4	100	80000	100	80000	0	100	80883	14	380	5101	84932	715	17	898	34	4439	86309	779	115	5395	4769	19	0	4	5110	10	16	10	9	29055	23	80069	362	339	91	80000	80100	29117	29270	29092	29218	29148
160204	29116	219	1	0	0	0	0	0	6722	795	1	656	86	108	29095	774	427	2202	1960	2035	25	160454	80172	80130	80273	80000	400722	1288504	1	59	49	26140	29173	29216	9273	3	9270	160100	80369	80000	80200	80000	29215	35	1	1	80201	100	99	8	100	80000	100	80000	0	100	80972	8	385	5037	85309	749	19	900	78	5148	85792	818	140	4931	5020	17	0	3	5110	11	16	7	14	29073	26	80063	337	372	84	80000	80100	29077	29148	29304	29319	29110
160204	29339	220	1	0	0	0	0	0	6808	805	1	704	100	92	29120	773	362	2013	2172	1963	25	160149	80154	80000	80100	80000	400771	1281416	1	63	49	26106	29225	29190	9031	3	9203	160100	80200	80000	80200	80000	29036	35	1	1	80201	100	99	5	100	80000	100	80000	0	100	80920	17	374	5361	84711	728	16	854	32	4920	86251	845	128	5391	5128	18	3	4	5110	12	16	11	12	29199	38	80057	361	361	89	80000	80100	29514	29266	29221	29090	29210
160204	29318	219	1	0	0	0	0	0	6988	795	1	704	98	116	29041	798	371	2282	2069	1932	25	160146	80156	80000	80100	80000	400767	1278605	0	69	49	25860	29185	29054	9248	3	9048	160100	80200	80000	80200	80000	29223	35	1	1	80201	100	99	8	100	80000	100	80000	1	100	80981	17	419	6197	85156	662	16	892	22	4993	86596	703	127	4967	5114	0	0	5	5110	11	16	12	11	29157	27	80049	392	393	84	80000	80100	29137	29170	29111	29330	29346

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3683

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9e	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29637	219	2	0	0	0	0	0	0	6882	781	1	696	84	112	29450	759	448	2038	2210	1854	25	160080	80065	80000	80010	80000	400331	1299274	0	63	98	26444	29335	29237	9186	0	3	9059	160010	80020	80000	80020	80000	29175	35	1	1	80021	10	9	10	10	80000	10	80000	0	0	10	80907	32	431	5094	0	84825	703	13	900	42	5373	85969	742	131	5586	4934	55	0	3	2	5020	3	16	3	2	29429	25	80061	433	382	106	80000	80010	29167	29230	29276	28960	29280
160024	29571	221	2	0	0	2	0	0	0	7089	783	1	720	88	108	29324	777	438	1995	2076	2116	25	160073	80074	80000	80010	80000	400347	1289438	1	57	49	26182	29431	29410	9005	0	3	9015	160010	80020	80000	80020	80000	29195	35	1	1	80021	10	9	9	10	80000	10	80000	0	0	10	80894	33	417	4979	0	85068	663	10	935	84	5233	85722	795	127	5248	5344	34	0	3	0	5020	3	16	3	2	29074	30	80052	340	352	89	80000	80010	29099	29286	29138	29334	29183
160024	29634	219	3	1	0	0	0	1	0	7206	814	1	720	98	96	29322	760	435	1993	1802	1804	25	160068	80074	80000	80010	80000	400324	1291587	0	66	49	26072	29200	29107	9467	0	3	9274	160010	80020	80000	80020	80000	29163	35	1	1	80021	10	9	14	10	80000	10	80000	0	0	10	80933	52	405	5529	0	85069	669	9	891	44	5820	85688	658	137	4725	5643	33	0	10	0	5020	2	16	3	2	29070	36	80057	330	358	96	80000	80010	29324	29295	29323	28974	29333
160024	29464	219	2	0	0	0	0	0	0	6291	785	1	592	77	108	29073	752	362	1803	2112	1761	25	160053	80060	80000	80010	80000	400317	1287987	0	62	49	26057	29256	29310	9040	0	3	9051	160010	80020	80000	80020	80000	29094	35	1	1	80021	10	9	10	10	80000	10	80000	0	0	10	80935	35	399	5407	32	85512	692	13	906	32	5601	85438	833	132	5276	4876	16	0	3	0	5020	2	16	2	3	29339	44	80073	389	367	97	80000	80010	29417	29369	29112	29084	29358
160024	29463	219	2	0	1	0	0	0	0	6709	830	1	712	82	96	29103	762	378	2091	2253	2098	25	160082	80070	80000	80010	80000	400327	1300150	0	58	49	26111	29056	29174	8942	0	3	9139	160010	80020	80000	80020	80000	29215	35	1	1	80021	10	9	7	10	80000	10	80000	0	0	10	80950	34	411	5814	0	85573	725	11	938	48	4758	85959	698	129	4734	4744	33	0	3	0	5020	3	16	3	2	29021	29	80055	355	299	90	80000	80010	28995	29183	29406	28983	29109
160024	29595	218	2	0	0	0	1	0	0	6564	787	1	696	120	96	29111	783	400	2084	2215	1896	25	160067	80070	80000	80010	80000	400353	1295220	0	50	49	26173	29207	28953	9004	0	3	9003	160010	80020	80000	80020	80000	29228	35	1	1	80021	10	9	6	10	80000	10	80000	0	0	10	80897	35	392	5626	0	85050	670	16	873	56	5933	85769	819	122	4592	4764	47	0	4	0	5020	3	16	3	3	29277	33	80060	381	380	84	80000	80010	29530	29277	29255	29348	29133
160024	29409	218	3	1	0	3	0	0	0	7280	798	1	736	103	104	29353	796	453	1995	2130	1904	25	160062	80068	80000	80010	80000	400325	1289356	0	57	49	25965	28934	29167	9099	0	3	9091	160010	80020	80000	80020	80000	29087	35	1	1	80021	10	9	7	10	80000	10	80000	0	0	10	80934	54	385	5228	0	85233	710	12	881	90	4716	85794	872	129	4578	5079	37	0	3	0	5020	3	16	2	3	29250	20	80066	340	348	82	80000	80010	29194	29250	29425	29273	29297
160024	29549	219	1	1	0	0	1	0	0	6907	802	1	720	110	108	29300	807	521	2160	2109	1907	25	160058	80067	80000	80010	80000	400287	1278022	0	58	49	26380	29241	29030	9117	0	3	9129	160010	80020	80000	80020	80000	29247	35	1	1	80021	10	9	10	10	80000	10	80000	0	0	10	80913	33	415	5814	0	85190	670	7	901	26	5239	86387	750	117	5267	4669	53	0	3	0	5020	3	16	2	3	29275	25	80064	396	362	101	80000	80010	29192	29183	29076	29053	29143
160024	29276	218	3	0	0	0	1	0	0	7201	796	1	704	98	100	29257	764	457	1988	2067	1829	25	160073	80067	80000	80010	80000	400333	1290875	0	66	49	26167	29335	29142	9213	0	3	9057	160010	80020	80000	80020	80000	28848	35	1	1	80021	10	9	9	10	80000	10	80000	0	0	10	80878	33	388	5084	0	84973	709	14	867	50	5799	85314	641	118	4692	4498	36	3	4	0	5020	2	16	3	3	29296	32	80057	436	375	91	80000	80010	29260	29377	29083	29299	29098
160024	29462	220	2	0	0	0	0	0	0	6596	775	1	760	111	144	29366	768	424	2046	1809	1769	25	160068	80065	80000	80010	80000	400325	1294132	0	66	49	26082	29239	29149	8920	0	3	9326	160010	80020	80000	80020	80000	29162	35	1	1	80021	10	9	15	10	80000	10	80000	0	0	10	80931	53	406	5052	0	85078	705	11	847	38	5050	85976	750	112	4786	5154	54	0	0	0	5020	3	16	2	3	28973	37	80058	366	350	90	80000	80010	29340	29387	29240	28933	29278

LDRSB (pre-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations