Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (NSHLD)

Test 1: uops

Code:

  dsb nshld

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)033f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)60696a6b6d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)inst barrier (9c)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
100417032128170171580110001000100060000491395201485917032316890100010001703217032111001100010000073116111683810001703317033170381703817033
1004170321271701715801100010001000600004913952014859170323168901000100017032170321110011000100001273116111683810001703317033170381703817033
10041703212717017158011000100010006000049139520148651703231689010001000170321703211100110001000013573116111683810001703317033170381703817033
100417032127170171580110001000100060001491395201485917032316890100010001703217032111001100010000073116111683810001703317033170381703817033
100417032127170171580110001000100060001491395201485917032316890100010001703217032111001100010000073116111683810001703317033170381703817033
10041703212817017158011000100010006000149139520148591703231689010001000170321703211100110001000016873116111683810001703317033170381703817033
100417032127170171580110001000100060001491395201485917032316890100010001703217032111001100010000073116111683810001703317033170381703817033
100417032127170171580110001000100060001491395201491317032316890100010001703217032111001100010000373116111683810001703317033170381703817033
100417032128170171580110001000100060000491395201485917032316890100010001703217032111001100010000073116111683810001703317033170381703817033
10041703212717017158011000100010006000149139520148591703231689010001000170321703211100199910000373116111683810001703317033170381703817033

Test 2: throughput

Code:

  dsb nshld

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
10204170032127400001200170128159700101001001000010010000500598001491669521509351700323168740101002001000020017003213591911102011009910010010000100001000010300710116421698382310000100170100170076170233170038170281
102041700321273000000017001715970010100100100001001000050059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000100002000071011610169838010000100170033170033170033170038170033
102041700321274000000017001715970010100100100001001000050059848149166952150935170032316874010100200100002001700321359191110201100991001001000010000100000000071011611169838010000100170033170033170038170038170033
102041700321273000000017001715970010100100100001001000050059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000100000000071011611169838010000100170033170033170038170038170033
102041700321274000000017001715970010100100100001001000050059800149166952150935170032316874010123200100002001700321359191110201100991001001000010000100000000071011611169838010000100170033170033170038170038170033
1020417003212740000000170017159700101001001000010010000500598001491669521509351700323168740101002001000020017003213591911102011009910010010000100001000000180071011611169838010000100170033170033170038170038170033
1020417003212740000000170017159700101001001000010010000500598001491669521510091700323168740101002001000020017003213591911102011009910010010000100001000762000071011611169838010000100170033170033170038170038170033
102041700321273000000017001715970010100100100001001000050059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000100000000071011611169838010000100170033170033170038170038170033
102041700321273000000017001715976010100100100001001000050059800149166952150961170032316874010100200100002001700321359191110201100991001001000010000100000000071011611169838010000100170033170033170038170038170033
102041700481273000000017001715970010100100100001001000050059800198166952150935170032316874010100200100002001700321359191110201100991001001000010000100000000071011611169838010000100170033170033170038170038170033

1000 unrolls and 10 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f414b51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
10024170032127300017001700159786100101010000101000050599800491669520149957170032316876210010201000020170056170032111002110910101000010001000000006403162316983801000010170033170033170033170033170033
10024170032127300017001700159786100101010000101000050599800491669520150014170032316876210010201000020170032170032111002110910101000010001000000006403163316983801000010170076170033170033170033170033
10024170032127400017001700159786100101010000101000050599800491669520149957170032316876210010201000020170032170032111002110910101000010001000000006403163216983801000010170033170033170033170033170033
10024170032127300017001700159786100101010000101000050599800491669520149957170032316876210010201000020170032170032111002110910101000010001000000006403163316983801000010170033170033170033170033170033
100241700321274003017001700159786100101010000101000050599800491669520150043170032316876210010201000020170032170032111002110910101000010001000006016402163316983801000010170033170033170033170033170033
10024170032127300017001700159786100101010000101000050599800491669520149997170032316876210010201000020170032170032111002110910101000010001000000006402163316983801000010170033170033170033170033170033
10024170032127300017001700159786100101010000101000050599800491669520149957170032316877710010201000020170032170032111002110910101000010001000000006402163316983811000010170033170033170033170033170033
10024170032127400017001700159786100101010000101000050599800491669520149957170032316876210010201000020170032170032111002110910101000010001000020006403162316983801000010170033170033170033170033170033
10024170032127300017001700159786100101110000101000050599800491669520150029170032316876210010201000020170032170032111002110910101000010001000000006403163316983801000010170033170033170033170033170033
10024170032127400017001700159786100101010000101000050599800491669520149957170032316876210010201000020170032170032111002110910101000010001000000006402163316983801000010170033170033170033170033170033