Firestorm: STP (post-index, 64-bit) measurements

Code:

  stp x0, x1, [x6], #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	20	22	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	ldst x64 uop (b1)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1040	8	1	1	1	1	0	10	14	1	20	28	1025	0	0	7	5	25	2000	1000	1000	1000	1000	50738	45824	1	1040	1040	824	3	898	2000	1000	3000	1040	124	1	1	1001	1000	1000	1022	8	60	3	12	1008	1	1	12	8	7	1012	125	7	52	7	1	73	4	16	2	2	1037	1000	1000	1000	1041	1041	1041	1041	1092
1004	1040	8	0	0	0	0	0	6	8	1	8	12	1025	0	3	6	1	25	2000	1000	1000	1000	1000	50778	45824	1	1040	1040	824	3	898	2000	1000	3000	1040	124	1	1	1001	1000	1000	1000	0	61	2	16	1000	1	0	24	0	0	1000	125	0	77	0	0	73	2	16	2	2	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	1	0	0	0	4	18	0	13	0	1025	9	1	6	2	25	2000	1000	1000	1000	1000	50778	45824	1	1040	1040	824	3	898	2000	1000	3000	1040	124	1	1	1001	1000	1000	1000	0	68	0	14	1000	0	0	20	0	6	1020	125	0	35	0	0	73	2	16	2	2	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	1	1	1	0	11	14	1	11	12	1025	18	1	5	5	25	2000	1000	1000	1000	1000	50738	45824	1	1040	1040	824	3	898	2000	1000	3000	1040	124	1	1	1001	1000	1000	1027	8	44	1	14	1007	0	1	14	6	7	1010	125	7	44	7	1	73	2	16	2	2	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	1	0	11	22	1	15	0	1025	8	2	11	4	25	2000	1000	1000	1000	1000	50746	45824	1	1040	1040	824	3	898	2000	1000	3000	1040	124	1	1	1001	1000	1000	1023	8	43	0	9	1007	1	1	18	4	7	1010	125	7	44	7	1	73	2	16	2	2	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	1	0	0	10	9	1	14	4	1025	9	2	6	3	25	2000	1000	1000	1000	1000	50762	45824	1	1040	1040	824	3	898	2000	1000	3000	1040	124	1	1	1001	1000	1000	1008	7	43	0	1	1007	1	2	12	12	10	1016	125	7	43	7	2	73	2	16	2	2	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	0	1	0	10	14	1	16	0	1025	8	3	9	4	25	2000	1000	1000	1000	1000	50762	45824	1	1040	1040	824	3	898	2000	1000	3000	1040	124	1	1	1001	1000	1000	1008	8	70	0	0	1007	11	1	0	0	10	1000	125	7	52	7	0	73	2	16	2	2	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	1	0	0	10	0	0	9	0	1025	10	0	4	3	25	2000	1000	1000	1000	1000	50746	45824	1	1040	1040	824	3	898	2000	1000	3000	1040	124	1	1	1001	1000	1000	1018	8	52	3	15	1007	1	1	15	6	11	1012	125	7	44	7	1	73	2	16	2	2	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	1	1	1	0	9	18	1	10	0	1025	6	2	5	5	25	2000	1000	1000	1000	1000	50754	45824	1	1040	1040	824	3	898	2000	1000	3000	1040	124	1	1	1001	1000	1000	1008	7	35	0	2	1007	0	0	22	16	7	1000	125	7	44	7	0	73	2	16	2	2	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	0	0	11	14	1	14	0	1025	10	2	9	5	25	2000	1000	1000	1000	1000	50746	45824	1	1040	1040	824	3	898	2000	1000	3000	1040	124	1	1	1001	1000	1000	1023	8	43	1	14	1008	0	1	14	4	7	1016	125	7	51	7	1	73	2	16	2	2	1037	1000	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 3->3

Code:

  stp x0, x1, [x6], #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	18	19	1e	1f	20	22	29	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10209	10040	75	0	0	0	0	2121	76	799	1	736	74	0	92	10025	780	78	165	40	25	20100	10100	10000	10100	10000	522019	468824	0	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	30000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10928	0	1434	364	0	669	10251	289	0	902	40	877	10908	1250	4	15	1289	0	0	710	1	17	1	1	10037	10000	12	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	0	0	0	0	2259	79	821	1	744	74	0	120	10025	785	74	152	43	25	20100	10100	10000	10100	10000	522157	468824	0	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	30000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10946	0	1478	428	1	672	10243	277	0	916	40	857	10917	1250	4	23	1208	0	0	710	1	17	1	1	10037	10000	68	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	0	0	0	0	2265	73	800	1	736	70	0	100	10025	828	88	141	53	25	20100	10100	10000	10100	10000	522075	468824	0	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	30000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10870	0	1313	385	0	654	10257	271	0	900	32	972	10909	1250	4	21	1228	0	0	710	1	17	1	1	10037	10000	9	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	0	0	0	0	2220	71	807	1	760	82	0	152	10025	805	81	168	65	25	20100	10100	10000	10100	10000	522069	468824	0	0	49	6960	10344	10040	8708	11	8849	20718	206	10232	205	30696	10196	122	5	1	10201	100	99	100	10000	100	10000	100	11006	0	1393	351	0	683	10343	288	0	888	64	2932	11021	1263	4	20	1212	0	0	775	1	48	1	1	10076	10127	52	0	10000	10100	10231	10249	10193	10272	10245
10204	10246	76	0	1	0	4	2616	332	799	1	688	90	0	88	10232	834	95	124	222	86	20331	10242	10102	10419	10279	520919	475761	0	0	49	7165	10245	10272	8741	21	8747	20711	206	10312	204	30942	10192	122	4	1	10201	100	99	100	10000	100	10000	100	10969	0	1504	339	0	631	10329	270	0	894	38	3630	11031	1262	4	17	1289	0	0	778	2	49	1	2	10245	10136	72	1	10000	10100	10191	10296	10231	10243	10197
10204	10273	77	0	0	4	4	2430	510	812	1	776	77	0	124	10233	789	75	164	232	107	20398	10243	10000	10432	10307	520108	473169	0	0	49	7165	10245	10246	8759	16	8877	20711	200	10339	208	30954	10195	122	5	1	10201	100	99	100	10000	100	10000	100	10968	0	1403	394	0	653	10360	267	0	886	46	4527	10939	1264	4	16	1317	0	0	793	1	50	1	1	10242	10128	13	1	10000	10100	10246	10249	10248	10244	10303
10204	10247	77	0	0	4	5	2307	432	798	1	712	84	0	104	10232	792	91	114	222	135	20338	10235	10102	10354	10279	519423	473306	0	1	49	7280	10241	10271	8674	25	8927	20750	202	10234	208	30702	10246	122	6	1	10201	100	99	100	10000	100	10000	100	10923	0	1392	365	0	675	10311	286	0	884	38	2044	10946	1259	4	18	1213	0	0	760	1	43	2	1	10157	10051	81	1	10000	10100	10196	10245	10041	10244	10143
10204	10040	77	0	0	3	1	2616	337	785	1	768	79	0	140	10074	775	99	146	90	85	20285	10100	10076	10273	10210	520058	469903	0	2	49	7063	10040	10091	8707	12	8780	20100	204	10159	202	30468	10142	122	1	1	10201	100	99	100	10000	100	10000	100	10985	9	1297	380	1	679	10298	297	0	902	42	2281	10898	1255	4	21	1478	0	7	727	1	33	2	1	10037	10070	97	0	10000	10100	10041	10092	10142	10143	10146
10204	10143	76	0	0	2	0	2205	74	807	1	704	94	0	96	10025	789	80	129	40	25	20100	10100	10000	10100	10000	522187	468824	1	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	30000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10896	0	1395	396	0	685	10253	268	0	906	38	866	10936	1250	4	15	1236	0	0	710	1	17	1	1	10037	10000	63	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	0	0	0	0	2121	78	814	1	736	82	0	144	10025	763	74	128	43	25	20100	10100	10000	10100	10000	522147	468824	0	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	202	30000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10936	0	1333	397	0	655	10263	269	0	872	44	868	10924	1250	4	20	1296	0	0	710	1	17	1	1	10037	10000	83	0	10000	10100	10041	10041	10041	10041	10041

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10029	10040	75	2	2	0	1986	90	850	1	688	76	4	196	10025	792	113	165	47	25	20010	10010	10000	10010	10000	520969	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	30000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10944	24	1352	367	0	637	10283	253	0	864	34	742	10935	1250	4	41	1273	14	3	640	2	16	3	3	10037	10000	18	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	3	0	0	2232	70	776	1	712	79	0	116	10025	778	108	200	49	25	20010	10010	10000	10010	10000	521041	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	30000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10911	21	1280	366	0	629	10264	269	0	874	44	811	10910	1250	4	41	1120	21	0	640	2	16	3	3	10037	10000	93	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	3	3	0	2070	89	794	1	704	81	2	120	10025	793	124	165	46	25	20010	10010	10000	10010	10000	520977	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	30000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10953	21	1197	386	0	664	10284	255	3	884	48	841	10919	1250	4	40	1278	21	0	640	3	16	2	2	10037	10000	90	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	3	3	3	1767	84	787	1	696	72	1	156	10025	777	111	164	48	25	20010	10010	10000	10010	10000	521033	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	30000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10916	21	1368	324	0	666	10265	249	0	890	36	805	10875	1250	4	47	1267	21	0	640	3	16	2	2	10037	10000	11	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	76	3	0	3	1992	90	802	1	736	96	1	116	10025	791	135	198	39	25	20010	10010	10000	10010	10000	521049	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	30000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10899	21	1303	356	0	621	10271	263	0	834	40	765	10896	1250	4	52	1285	21	6	640	3	16	2	2	10037	10000	5	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	3	3	0	1881	95	761	1	712	68	1	152	10025	811	111	181	44	25	20010	10010	10000	10010	10000	521049	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	30000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10899	21	1333	345	0	637	10276	244	0	894	32	747	10868	1250	4	43	1225	21	0	640	2	16	2	2	10037	10000	10	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	3	3	3	2262	84	810	1	688	70	0	116	10025	804	102	180	49	25	20010	10010	10000	10010	10000	521025	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	30000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10888	14	1258	330	0	669	10271	245	0	898	32	689	10903	1250	4	29	1268	7	0	640	3	16	3	2	10037	10000	66	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	0	1944	82	821	1	720	59	0	160	10025	769	115	170	42	25	20010	10010	10000	10010	10000	521009	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	30000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10945	14	1357	377	0	687	10279	268	0	880	82	730	10941	1250	4	32	1155	14	4	640	3	16	3	2	10037	10000	63	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	2	2055	84	829	1	776	86	1	144	10025	774	130	186	43	25	20010	10010	10000	10010	10000	521049	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	30000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10889	27	1203	358	0	668	10277	222	0	890	42	811	10923	1250	4	41	1241	21	0	640	2	16	3	3	10037	10000	57	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	3	3	0	2109	82	774	1	712	86	2	156	10025	769	112	194	40	25	20010	10010	10000	10010	10000	521041	468824	49	6960	10040	10040	8696	3	8790	20010	20	10000	20	30000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10888	28	1280	371	0	660	10274	257	0	916	42	762	10913	1250	4	47	1091	7	8	640	2	16	3	3	10037	10000	64	1	10000	10010	10041	10041	10041	10041	10041

Test 3: throughput

Count: 8

Code:

  stp x0, x1, [x6], #8
  stp x0, x1, [x7], #8
  stp x0, x1, [x8], #8
  stp x0, x1, [x9], #8
  stp x0, x1, [x10], #8
  stp x0, x1, [x11], #8
  stp x0, x1, [x12], #8
  stp x0, x1, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5238

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80209	41803	312	2	1	2	0	1704	349	787	1	720	145	120	41713	810	1742	2924	1447	25	161614	83367	80011	80100	80000	402939	1916224	605	49	39071	0	41635	41720	31520	3	31676	160100	200	80000	200	240000	41734	75	1	1	80201	100	99	100	80000	100	80000	100	80996	15	5547	478	918	873	80310	238	0	901	80	1114	81195	10000	32	320	5925	27	0	0	5110	1	17	1	1	41654	80833	80000	80100	42132	41759	41672	41698	41684
80204	41733	312	1	1	1	0	1800	706	795	1	760	117	136	41676	788	2133	3364	1387	25	161137	80876	80015	80100	80000	402315	1918432	534	49	38630	0	41778	41687	31588	3	31641	160320	200	80000	200	240000	41683	75	1	1	80201	100	99	100	80000	100	80000	100	80952	13	5602	462	905	909	80607	270	0	907	38	1063	81203	10000	32	334	5762	13	0	0	5110	1	16	1	1	41687	82844	80000	80100	41658	41754	41648	41653	41672
80204	41645	312	1	0	0	0	1692	344	778	1	704	117	140	41650	778	1949	2884	1392	25	160845	81266	80007	80100	80000	401484	1920064	625	49	38580	0	41690	41684	31589	3	31584	160100	200	80136	200	240000	41638	82	1	1	80201	100	99	100	80000	100	80000	100	80943	13	5149	490	908	883	80348	267	0	866	44	1103	81221	10000	32	380	4456	14	0	0	5110	1	17	1	1	41923	80758	80000	80100	41898	41953	41905	41886	41938
80204	41888	396	1	0	1	0	1728	790	836	1	736	124	232	41897	729	2050	2593	1373	25	160814	81934	80015	80100	80000	402740	1931752	621	49	38759	0	41878	41862	31802	3	31826	160100	200	80000	200	240000	41880	75	1	1	80201	100	99	100	80000	100	80000	100	80961	15	4424	517	852	898	80588	224	0	835	44	1630	81486	10000	32	575	4522	13	0	0	5110	1	17	1	1	41931	82021	80000	80100	41930	41961	41871	41865	41829
80204	41918	314	1	0	1	0	1896	874	802	1	736	122	260	41994	784	1918	2732	1279	25	160869	80830	80000	80100	80000	403267	1930096	258	49	38884	0	42119	41953	31786	3	31930	160100	200	80000	200	240000	42091	75	1	1	80201	100	99	100	80000	100	80000	100	80911	13	5059	489	857	867	80637	240	0	889	38	1575	81453	10000	32	640	5004	13	0	0	5110	1	17	1	1	41811	80510	80000	80100	41771	41878	41894	41961	41894
80204	41892	314	1	0	0	0	1653	820	767	1	680	141	108	41924	754	1769	2404	1320	25	160773	81043	80000	80100	80432	411833	1929808	233	49	38851	0	41899	41979	31907	3	31879	160100	200	80000	200	240000	41935	82	1	1	80201	100	99	100	80000	100	80000	100	80937	15	5820	468	881	880	80619	240	1	863	42	1560	81470	10000	32	608	5488	14	0	0	5110	1	48	1	1	41874	82908	80000	80100	41882	41877	41919	41983	41957
80204	41831	314	1	1	0	0	1605	813	791	1	680	133	108	41856	776	1973	2395	1362	25	162794	80845	80000	80100	80000	407863	1932016	161	49	38798	0	42004	41929	31800	3	31878	160100	200	80000	200	240000	41953	81	1	1	80201	100	99	100	80000	100	80000	100	80966	17	5208	439	871	871	80590	264	1	886	44	1588	81517	10000	32	606	5178	13	1	0	5165	1	16	1	1	41845	80638	80000	80100	41939	41839	41954	42005	41939
80204	41792	313	1	1	0	0	2271	867	782	1	688	151	148	41923	784	2084	2106	1268	25	160605	83394	80000	80100	80000	408946	1930840	426	49	38815	0	41878	41974	31799	3	31906	160100	200	80000	200	240000	41879	75	1	1	80201	100	99	100	80000	100	80000	100	80951	14	5172	427	854	901	80614	239	0	883	44	1687	81508	10000	32	606	4942	14	1	256	5110	1	17	1	1	41893	80905	80000	80100	41960	41904	41963	42399	41991
80204	41902	314	1	1	1	0	1725	757	815	1	688	123	248	41921	771	1797	2316	1380	25	164464	80538	80000	80100	80000	403454	1935212	199	49	38994	0	42034	42148	31851	3	31840	160100	200	80000	200	240000	41920	81	1	1	80201	100	99	100	80000	100	80000	100	80957	13	5311	454	856	902	80662	250	0	921	80	1566	81552	10000	32	651	4728	14	1	0	5110	1	17	1	1	41895	82236	80000	80100	41940	41977	41921	41825	42351
80204	41923	313	1	1	0	0	1578	857	782	1	688	137	116	42401	754	1743	2416	1271	25	161055	82008	80000	80100	80000	403721	1926928	466	49	38786	0	41867	41827	32096	3	31820	160100	200	80000	200	240000	41825	75	5	1	80201	100	99	100	80000	100	80000	100	80949	13	4416	459	870	877	80616	251	1	872	44	1623	81459	10000	32	552	4704	13	0	0	5110	1	17	1	1	41992	80696	80000	80100	41870	42049	41937	41913	41928

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5246

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80029	41861	314	1	1	0	0	1752	383	865	1	688	131	156	41788	752	1951	2966	1595	25	161010	80088	80000	80010	80000	404091	1929328	1	155	49	38738	0	41915	41851	31771	3	31817	160010	20	80000	20	240000	41866	85	1	1	80021	10	9	10	80000	10	80000	10	80996	15	5399	474	956	868	80341	265	0	923	42	1043	81233	10000	32	329	6223	12	1	0	0	5020	0	0	1	17	1	1	41842	80143	0	80000	80010	41886	41866	41794	41797	41875
80024	41826	313	1	0	1	0	1854	426	783	1	688	135	224	41768	776	1787	2877	1587	25	160347	81335	80000	80010	80000	402622	1925320	1	80	49	38766	0	41777	41949	31758	3	31792	160010	20	80000	20	240000	41864	75	1	1	80021	10	9	10	80000	10	80000	10	80973	13	5793	467	996	938	80339	252	2	877	32	1186	81248	10000	32	315	5852	14	0	0	0	5038	0	0	1	17	1	1	41759	80651	0	80000	80010	41745	41777	41790	41761	41765
80024	41725	313	1	1	1	1	1845	363	825	2	744	146	184	41745	782	1809	2941	1574	25	160863	81474	80000	80010	80000	400360	1923160	0	322	49	38711	0	41819	41727	31684	3	31720	160010	20	80000	20	240000	41784	75	1	1	80021	10	9	10	80000	10	80000	10	80920	7	5278	438	971	892	80335	266	1	899	48	1024	81208	10000	32	329	5304	14	0	0	0	5020	0	0	1	17	1	1	41864	81276	0	80000	80010	41759	41841	41714	41784	41856
80024	41889	313	1	1	0	0	1641	339	798	1	720	137	232	41815	809	2016	2902	1577	25	160675	80784	80000	80010	80000	402287	1920856	0	412	49	38599	0	41815	41905	31768	3	31868	160010	20	80000	20	240000	41841	75	1	1	80021	10	9	10	80000	10	80000	10	80989	15	5850	522	983	947	80318	291	0	944	30	1127	81181	10000	32	308	5368	13	1	0	0	5020	0	0	1	17	1	1	41742	80591	0	80000	80010	41714	41857	41861	41827	41790
80024	41717	313	1	0	0	0	1821	364	797	1	680	113	144	41926	762	2227	2548	1547	25	160740	80346	80000	80010	80000	400641	1921912	0	137	49	38690	0	41799	41856	31794	3	31832	160010	20	80000	20	240000	41811	75	1	1	80021	10	9	10	80000	10	80000	10	80964	0	5880	491	986	856	80279	243	0	879	80	1100	81220	10000	32	313	5344	0	0	0	0	5020	0	0	1	17	1	1	41831	80575	0	80000	80010	41872	41782	41844	41739	41896
80024	41816	314	0	0	0	0	1764	326	801	1	712	103	112	41821	792	2095	2805	1538	25	160861	80632	80000	80010	80000	403905	1921240	0	354	49	38777	0	41784	41779	31743	3	31822	160010	20	80000	20	240000	41803	76	1	1	80021	10	9	10	80000	10	80000	10	80936	0	5882	444	985	853	80322	255	0	863	58	1130	81217	10000	32	324	5473	0	0	0	0	5020	0	0	1	17	1	1	41781	80943	0	80000	80010	41815	41887	41861	41811	41872
80024	41796	313	0	0	0	0	1707	339	785	1	728	137	92	41728	798	1887	2808	1520	25	160224	80268	80000	80010	80000	402352	1923784	0	385	49	38754	0	41868	41874	31843	3	31752	160010	20	80000	20	240000	41862	85	5	1	80021	10	9	10	80000	10	80000	10	80981	0	5782	478	1008	857	80278	249	0	893	42	1090	81171	10000	32	310	5885	0	0	0	0	5020	0	0	1	17	1	1	41783	80926	0	80000	80010	41781	41827	41788	41725	41711
80024	41878	312	0	0	0	0	1695	376	823	1	688	114	236	41790	746	1709	3063	1552	25	160299	81074	80000	80010	80000	401013	1926136	0	179	49	38754	0	41876	41819	31724	3	31822	160010	20	80000	20	240000	41950	76	1	1	80021	10	9	10	80000	10	80000	10	80924	0	5185	465	981	935	80335	238	0	900	62	1106	81172	10000	32	292	5259	0	0	0	0	5020	0	0	1	17	1	1	41814	80151	0	80000	80010	41881	41753	41940	41921	41817
80024	41788	313	0	0	0	0	1686	362	826	1	680	125	144	41719	820	1910	2908	1643	25	160671	80385	80000	80010	80000	402867	1926424	0	101	49	38609	0	41797	41836	31772	3	31792	160010	20	80000	20	240000	41847	75	1	1	80021	10	9	10	80000	10	80000	10	80938	0	5522	473	985	906	80296	264	0	883	74	1150	81178	10000	32	329	5797	0	0	0	0	5020	0	0	1	17	1	1	41816	80448	0	80000	80010	41776	41878	41981	41806	41828
80024	41753	314	0	0	0	0	1704	330	810	1	728	126	156	41873	795	1994	2869	1639	25	160828	80694	80000	80010	80000	401835	1923328	0	318	49	38813	0	41827	41879	31651	3	31699	160010	20	80000	20	240000	41838	75	1	1	80021	10	9	10	80000	10	80000	10	80970	0	5992	505	956	880	80297	217	0	911	34	1039	81228	10000	32	316	5703	0	0	0	0	5020	0	0	1	18	1	1	41827	80797	0	80000	80010	41890	41816	41925	41770	41746

STP (post-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations