Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMN (uxtx, 64-bit)

Test 1: uops

Code:

  cmn x0, x1, uxtx
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
10043692057251000100010005000369369206322510001000200036966111001100000073118113661000370370370370370
10043692036251000100010005000369369206322510001000200036966111001100000073118113661000370370370370370
10043693036251000100010005000369369206322510001000200036966111001100000073118113661000370370370370370
10043693036251000100010005000369369206322510001000200036966211001100000073118113661000370370370370370
10043692036251000100010005000369369206322510001000200036966111001100000073118113661000370370370370370
10043693036251000100010005000369369206322510001000200036966111001100000073118113661000370370370370370
10043693057251000100010005331369369206322510001000200036966111001100000073118113661000370370370370370
10043692036251000100010005000369369206322510001000200036966111001100000073118113661000370370370370370
10043692036251000100010005000369369206322510001000200036966111001100000073118113661000370370370370370
10043692036251000100010005000369369206322510001000200036966111001100000073118113661000370370370370370

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn x0, x1, uxtx
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020420035150000000168199262520100201002010012971500491695520035200351740631748120100202003020020035104112020110099100201001010000013101328221999220000101002003620036200362003620036
202042003515000000061199262520100201002010012971500491695520035200351740631748120100202003020020035104112020110099100201001010000013101228221999220000101002003620036200362003620036
2020420035150000000884199262520100201002010012971500491695520035200351740631748120100202003020020035104112020110099100201001010000013101228221999220000101002003620036200362003620036
202042003515000000061199262520100201002010012971500491695520035200351740631748120100202003020020035104112020110099100201001010000013101228221999220000101002003620036200362003620036
202042003515000000061199262520100201002010012971500491695520035200351740631748120100202003020020035104112020110099100201001010000013101228221999220000101002003620036200362003620036
202042003514900010061199262520100201002010012971500491695520035200351740631748120100202003020020035104112020110099100201001010000013101228221999220000101002003620036200362003620036
202042003514900000061199262520100201002010012971500491695520035200351740631748120100202003020020035104112020110099100201001010000013101228221999220000101002003620036200362003620036
202042003515000000061199262520100201002010012971500491695520035200351740631748120100202003020020035104112020110099100201001010000013101228221999220000101002003620036200362003620036
202042003515000000082199262520100201002010012971500491695520035200351740631748120100202003020020035104112020110099100201001010000013101228221999220000101002003620036200362003620036
202042003514900000061199262520100201002010012971500491695520035200351740631748120100202003020020035104112020110099100201001010000013101228221999220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002420035150006119918252001020010200101297247149169552003520035174283175042001020020300202003510411200211091020010100100001270627111999520000100102003620036200362003620036
2002420035150006619918252001020010200101297247049169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
20024200351500126119918252001020010200101297247049169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
20024200351500010319918252001020010200101297247049169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
2002420035150006119918252001020010200101297247049169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
2002420081150101241991725200102001020010129724704916955200352003517428317504200942002030155200351041120021109102001010010028131270127111999520000100102003620036200362003620036
2002420035149006119918252001020010200101297247149169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
20024200351500072619918252001020010200101297247049169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
20024200351500126119918252001020010200101297247149169552003520035174283175042001020020300202003510411200211091020010100101001270127111999520000100102003620036200362003620036
2002420035150006119918252001020079200101297247149169552003520035174283175042001020020300202003510411200211091020010100101061270127111999520000100102003620036200362003620036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn x0, x1, uxtx
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)191e3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020420035150110121726199302520100201002011212972330491695520035200351742521174872011220224302362003510411202011009910020100101000011113180216232001520000101002003620036200362003620036
2020420035150110016119930252010020100201121297233049169552003520035174256174872011220224302362003510411202011009910020100101000011113180216222001520000101002003620036200362003620036
2020420035150110316119930252010020100201121297233049169552003520035174256174872011220224302362003510411202011009910020100101000011113180216222001520000101002003620036200362003620036
2020420035150110016119930252010020100201121297233049169552003520035174256174872011220224302362003510411202011009910020100101000011113180216222001520000101002003620036200362003620036
2020420035150110016119930252010020100201121297150149169552003520035174063174812010020200302002003510411202011009910020100101000000013101228221999220000101002003620036200362003620036
20204200351500001506119926252010020100201001297150049169552003520035174063174812010020200302002003510411202011009910020100101000000013101328221999220000101002003620036200362003620036
202042003515000032106119926252010020100201001297150149169552003520035174063174812010020200302002003510411202011009910020100101000000013101228221999220000101002003620036200362003620036
20204200351500001206119926252010020100201001297150149169552003520035174063174812010020200302002003510411202011009910020100101000000013101228221999220000101002003620036200362003620036
2020420035150000006119926252010020100201001297150149169552003520035174063174812010020200302002003510411202011009910020100101000000013101228221999220000101002003620036200362003620036
2020420035150000006119926252010020100201001297150149169552003520035174063174812010020200302002003510411202011009910020100101000000013101228221999220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002420035150006119918252001020010200101297247149169552003520035174283175042001020020300202003510411200211091020010100100001270127121999520000100102003620036200362003620036
2002420035150006119918252001020010200101297247049169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
200242003515030006119918252001020010200101297247049169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
2002420035150006119918252001020010200101297247049169552003520035174283175042001020136300202003510411200211091020010100100001270127211999520000100102003620036200362003620036
2002420035150006119918252001020010200101297247149169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
20024200351501806119918252001020010200101297247049169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
2002420035150006119918252001020010200101297247149169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
2002420035150006119918252001020010200101297247049169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
2002420066150006119918252003320010200101297247149169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036
200242003515029406119918252001020010200101297247049169552003520035174283175042001020020300202003510411200211091020010100100001270127111999520000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204267702000035258010080100801004005000492365526735267351667231669080100802001602002673566118020110099100801001000000051103191126731800001002673626736267362673626736
80204267352010035258010080100801004005001492365526735267351667231669080100802001602002673566118020110099100801001000000051101191126731800001002673626736267362673626736
80204267352000035258010080100801004005000492365526735267351667231669080100802001602002673566118020110099100801001000000051101191126731800001002673626736267362673626736
80204267352000035258010080100801004005001492365526735267351667231669080100802001602002673566118020110099100801001000000051101191126731800001002673626736267362673626736
80204267352000035258010080100801004005001492365526735267351667231669080100802001602002673566118020110099100801001000000051101191126731800001002673626736267362673626736
80204267352000035258010080100801004005000492365526735267351667231669080100802001602002673566118020110099100801001000000051101191126731800001002673626736267362673626736
80204267352000035258010080100801004005000492365526735267351667231669080100802001602002673566118020110099100801001000000051101191126731800001002673626736267362673626736
80204267352000035258010080100801004005001492365526735267351667231669080100802001602002673566118020110099100801001000000051101191126731800001002673626736267362673626736
80204267352010035258010080100801004005001492365526735267351667231669080100802001602002673566118020110099100801001000000051101191126731800001002673626736267362673626736
802042673520000700258010080100801004005001492365526735267351667231669080100802001602002673566118020110099100801001000000051101191126731800001002673626736267362673626736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? int retires (ef)f5f6f7f8fd
80024267202000352580010800108001040005014923625267052670516665316683800108002016002026705661180021109108001010000502000015180002717267018000000102670626706267062670626706
80024267052000402580010800108009140005014923625267052670516665316683800108002016002026705661180021109108001010000502000028180001428267018000000102670626706267062670626706
80024267052000352580010800108001040005004923625267052670516665316683800108002016002026705661180021109108001010000502000028180112225267018000000102670626706267062670626706
800242670520003525800108001080010400050049236252670526705166653166838001080020160020267056611800211091080010109426502231021180112713267018000000102670626706267062670626706
80024267052000402580010800108001040005014923625267052670516665316683800108002016002026705661180021109108001010000502231018182112416267018000000102670626706267062670626706
800252670520003525800108001080010400050149236252670526705166653166838001080020160020267056611800211091080010100005020301221811022262670180000160102670626706267062670626706
80024267052000352580010800108001040005014923625267052670516665316683800108002016002026705661180021109108001010000502000014180002717267018000000102670626706267062670626706
800242670520003525800108001080010400050049236252670526705166653166838001080020160020267056611800211091080010100005020000281800016272670180000169102670626706267062670626706
800242670520003525800108001080010400050149236252670526705166653166838001080020160020267056611800211091080010100100502000017180002717267018000000102670626706267062670626706
800242670520002712580010800108001040005014923625267052670516665316683800108002016002026705661180021109108001010000502000028180001728267018000000102670626706267062670626706