Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ORN (register, lsr, 32-bit)

Test 1: uops

Code:

  orn w0, w0, w1, lsr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004203516061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203515061100017352520002000100032570020352035157531842100010002000203542111001100010731671117812000100020362036203620362036
100420351645611000173525200020001000325700203520351575318421000100020002035421110011000150731671117812000100020362036203620362036
1004203516061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203515061100017352520002000100032570020352035157531842100010002000203542111001100003731671117812000100020362036203620362036
1004203516061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351532961000173525200020001000325700203520351575318421000100020002035421110011000150731671117812000100020362036203620362036
1004203515061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203516061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035160103100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  orn w0, w0, w1, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204200351550001206110000198032520100201001010018534204916955200352003518429318700101001020020200200354231102011009910010100100000600710159111979120000101002003620036200362003620036
1020420035155000606110000198032520100201001010018534204916955200352003518429718748101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
10204200351560003306110000198032520100201001010018534204917000200352003518429618700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
102042003515500024015610000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
10204200351550004806110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
102042003515500012025710000198032520100201001010018534214916955200352003518429318757101001020020200200354211102011009910010100100000030710159111979120000101002003620036200362003620036
1020420035156000006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
10204200351560001506110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
10204200351550002406110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
10204200351550004206110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? int retires (ef)f5f6f7f8fd
100242003515500611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010106403632219792200000100102003620036200362003620036
10024200351551201851000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010406402632219792200000100102008120036200702003620036
100242003515500611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010036402632219792200000100102003620036200362003620036
100242003515600611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010006402632219792200000100102003620036200362003620036
100242003515600611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010006402632219792200000100102003620036200362003620036
100242003515500611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010106402632219792200000100102003620036200362003620036
100242003515500611000019743252005820010100101853101491695520035200351845131871810010100202002020035421110021109101001010036402632219792200000100102003620036200362003620036
1002420035155120611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010006402632219792200000100102003620036200362003620036
10024200351555970611000019743252001020010100101853101491392720035200351845131871810010100202002020035421110021109101001010206402632219792200000100102003620036200362003620036
100242003515500611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010406402632219792200000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  orn w0, w1, w0, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035156000000611000019803252010020100101001853421491695502003520035184293187001010010200202002003542111020110099100101001000000000710159111979120000101002003620036200362003620036
10204200351550000004521000019803252010020100101001853421491695502003520035184293187001010010200202002003588111020110099100101001000000000710159111979120000101002003620036200362003620036
1020420035155000000611000019803252010020100101001853421491695502003520035184293187001010010200202002003542111020110099100101001000000000710159111979120087101002003620036200362003620036
1020420035155000000611000019803252010020100101001853421491695502003520035184293187001010010200202002003542111020110099100101001000000000710159111979120000101002003620036200362003620036
1020420035155000000611000019803252010020100101001853421491695502003520035184293187001010010200202002003542111020110099100101001000000000710159111979120000101002003620036200362003620036
10204200351550000001711000019803252010020100101001853421491695502003520125184293187001010010200202002003542111020110099100101001000000000710159111979120000101002003620036200362003620036
1020420035155000000611000019803252010020100101001853421491695502003520035184293187001027110200202002003542111020110099100101001000001000710159111979120000101002003620036200362003620036
1020420035155000000611000019803252010020100101001853421491695502003520035184293187001010010200202002003542111020110099100101001000000000710159111979120000101002003620036200362003620036
1020420035156000000611000019803252010020100101001853421491695502003520035184293187001010010200202002003542111020110099100101001000000000710159111979120000101002003620036200362003620036
1020420035155000000611000019803252010020100101001853421491695502003520035184293187001010010200202002003542111020110099100101001000000000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? int retires (ef)f5f6f7f8fd
10024200351550126110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100306403633319792200000100102003620036200362003620036
1002420035155006110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100006403633319792200000100102003620036200362003620036
1002420035155006110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100006403633319792200000100102003620036200362003620036
1002420035156006110000197432520010200101001018531004916955200352003518451318718100101002020020200354211100211091010010100006403633319792200000100102003620036200362003620036
10024200351550126110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100006403633319792200000100102003620036200362003620036
10024200351550010310000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100306403633319792200000100102003620036200362003620036
1002420035155006110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100006403633319792200000100102003620036200362003620036
10024200351560126110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100006403633319792200000100102003620036200362003620036
1002420035155008910000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100006403633319792200000100102003620036200362003620036
10024200351550126110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100006403633319792200000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  orn w0, w8, w9, lsr #17
  orn w1, w8, w9, lsr #17
  orn w2, w8, w9, lsr #17
  orn w3, w8, w9, lsr #17
  orn w4, w8, w9, lsr #17
  orn w5, w8, w9, lsr #17
  orn w6, w8, w9, lsr #17
  orn w7, w8, w9, lsr #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204267672070006180000260942516010016010080100164318492364526725267251661531667780100802001602002672539118020110099100801001000051106221126717160000801002672626726267262672626726
80204267312070006180000239562516010016010080100163758492364526725267881661531667780100802001602002672539118020110099100801001000051101221126717160000801002672626726267262672626726
80204267252070006180000260942516012516012580125164318492364526725267251661531667780100802001602002673140118020110099100801001000051101221126717160000801002672626726267262672626726
80204267252070006180000260942516010016010080100164318492365126731267311662031668280100802001602002672539118020110099100801001000051102232126717160025801002673226726267262696226726
802042672520700014580000260942516010016010080100164318492376626725267251661531667780100802001602002672539118020110099100801001000051101221126717160000801002672626726267262672626726
80204267252070006180000260942516010016010080100164318492364526725267251661531667780100802001602002672539118020110099100801001000051101221126717160000801002672626726267262672626726
80204267252080006180000239562516012516012580125163758492364526725267251661531667780100802001602002672539118020110099100801001000051121221126717160000801002672626726267322672626726
80204267252070006180000260942516010016010080100164318492364526725267251661531667780100802001602002672539118020110099100801001000051101231126717160000801002672626726267262672626726
80204267252070006180000239562516010016010080100164318492364526725267251661531667780100802001602002672539118020110099100801001001051101221126717160000801002672626726269042672626726
80204267252070006180000239562516010016010080100164318492364526725267251661531667780100802001602002672539118020110099100801001000051101221126717160000801002672626732267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfl1i tlb miss demand (d4)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002426734207061800002128025160010160010800101631421492363126711267111662331668580010800201600202671139118002110910800101000502011522141526704160000800102671226712267122671226712
80024267112070618000021280251600101600108001016314214923631267112671116623316685800108002016002026711391180021109108001010005020092291126704160000800102671226712267122671226712
8002426711207061800002128025160010160010800101631421492363126711267111662331668580010800201600202671139118002110910800101000502001722151526704160000800102671226712267122671226712
80024267112071261800002128025160010160010800101631420492363126711267111662331668580010800201600202671139118002110910800101000502001622171826708160000800102671226712267122671226712
8002426711207061800002128025160010160010800101631420492363126711267111662331668580010800201600202671139118002110910800101000502001622151126748160000800102671226712267122671226712
80024267112070103800802128525160010160010800101631421492363126711267111662331668580010800201600202671139118002110910800101000502011222111526704160000800102671226712267122671226712
8002426711206061800002128025160010160010800101631420492363126711267111662331668580010800201600202671139118002110910800101000502011822161326704160000800102671226712267122671226712
800242671120706180000212802516001016001080010163142149236312671126711166233166858001080020160020267113911800211091080010100050200922111526704160000800102671226712267122671226712
8002426711207061800002128025160010160010800101631420492363126711267111662331668580010800201600202671139118002110910800101000502001722141826704160000800102671226712267122671226712
8002426711207053680000212802516001016001080010163142049236312671126711166233166858001080020160020267113911800211091080010100050200922111126704160000800102671226712267122671226712