Firestorm: LDR (literal, 64-bit) measurements

Code:

  ldr x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	1e	20	22	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	393	3	0	0	0	0	18	0	0	0	0	365	0	0	1	1	3	25	1000	1000	1000	14704	1	382	381	204	3	248	1000	1000	380	63	1	1	1001	1000	1000	0	1006	0	0	50	1023	7	0	7	0	23	1038	62	12	3	22	33	73	3	16	1	1	385	0	7	0	0	1000	388	394	394	395	389
1004	387	3	1	0	1	0	54	0	0	1	0	372	0	0	0	1	9	25	1000	1000	1000	15420	1	387	387	210	3	246	1000	1000	387	70	1	1	1001	1000	1000	0	1000	0	0	46	1012	7	0	0	6	11	1035	62	6	1	12	33	73	1	16	1	1	384	0	0	0	0	1000	383	389	388	388	389
1004	381	3	0	0	0	0	34	12	0	0	0	372	4	0	0	1	10	25	1000	1000	1000	14776	1	382	381	210	3	245	1000	1000	387	70	1	1	1001	1000	1000	0	1000	0	0	33	1012	0	0	8	0	12	1022	62	6	2	22	17	73	1	16	1	1	384	0	0	0	0	1000	388	388	389	382	383
1004	387	3	1	0	1	0	34	0	0	0	0	366	0	0	1	0	10	25	1000	1000	1000	15207	1	387	388	210	3	240	1000	1000	381	62	1	1	1001	1000	1000	0	1000	0	0	18	1012	7	0	7	0	25	1030	62	6	1	12	33	73	1	16	1	1	378	0	7	0	0	1000	382	389	388	383	388
1004	381	2	0	0	0	0	34	10	0	0	0	378	0	0	1	1	10	25	1000	1000	1000	15374	1	382	388	210	3	240	1000	1000	388	70	1	1	1001	1000	1000	0	1000	0	0	18	1012	0	0	0	0	12	1035	62	6	2	12	17	73	1	16	1	1	381	0	0	0	0	1000	388	389	388	383	382
1004	381	3	0	0	0	0	43	0	0	0	0	366	5	0	1	1	4	25	1000	1000	1000	14940	0	380	387	210	3	239	1000	1000	380	62	1	1	1001	1000	1000	1	1024	0	0	18	1012	0	0	12	0	12	1031	62	12	2	22	33	73	1	16	1	1	379	0	0	0	2	1000	382	388	381	401	383
1004	381	3	0	0	0	0	18	5	1	1	0	372	0	0	1	0	4	25	1000	1000	1000	14955	0	381	382	204	3	251	1000	1000	381	62	1	1	1001	1000	1000	0	1000	0	0	18	1022	0	0	0	0	13	1032	62	12	1	22	17	73	1	16	1	1	378	0	7	6	0	1000	388	388	394	390	381
1004	387	3	0	0	1	0	40	8	1	0	0	373	0	0	0	0	10	25	1000	1000	1000	14847	0	387	382	204	3	239	1000	1000	388	62	1	1	1001	1000	1000	0	1000	0	0	18	1013	7	1	0	0	12	1031	62	6	1	12	17	73	1	16	1	1	379	0	0	0	0	1000	382	382	383	383	383
1004	382	3	0	0	0	0	18	0	0	0	0	373	0	0	1	1	6	25	1000	1000	1000	14341	0	380	380	209	3	238	1000	1000	388	63	1	1	1001	1000	1000	0	1000	0	0	33	1012	0	0	0	0	22	1012	62	18	3	22	17	73	1	16	1	1	386	0	0	0	0	1000	383	395	389	388	383
1004	387	3	1	0	0	0	18	0	0	0	0	367	0	0	1	1	10	25	1000	1000	1000	14362	1	387	382	204	3	239	1000	1000	401	70	1	1	1001	1000	1000	0	1000	0	0	35	1022	0	0	0	0	12	1032	62	6	1	12	17	73	1	16	1	1	390	0	0	0	0	1000	382	383	382	381	383

Count: 8

Code:

  ldr x0, .+4
  ldr x0, .+4
  ldr x0, .+4
  ldr x0, .+4
  ldr x0, .+4
  ldr x0, .+4
  ldr x0, .+4
  ldr x0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	20	22	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26736	200	29	1	0	0	41	4	0	183	0	26703	6	1	0	0	6	25	80100	100	80260	100	80000	500	1167263	49	23635	26721	26715	16636	3	16674	80100	200	80000	200	26714	62	1	1	80201	100	99	100	80000	100	80000	0	100	80152	43	0	34	0	80024	436	0	538	0	22	80092	5000	6	2	22	17	272	332	5110	3	16	3	3	26710	1	6	6	2	80000	100	26721	26717	26717	26722	26715
80204	26720	200	23	59	0	0	22	0	0	72	16	26707	0	0	0	0	5	25	80100	100	80000	100	80000	500	1167108	49	23641	26714	26721	16637	3	16672	80100	200	80000	200	26715	56	1	1	80201	100	99	100	80000	100	80000	0	100	80387	128	0	34	0	80023	142	0	568	0	13	80184	5000	6	2	13	33	84	377	5110	3	16	3	3	26713	0	6	0	2	80000	100	26715	26723	26715	26715	26722
80204	26720	200	83	46	0	0	24	16	0	42	0	26700	0	0	0	0	6	25	80100	100	80000	100	80000	500	1165514	49	23635	26715	26716	16643	3	16674	80100	200	80000	200	26714	56	1	1	80201	100	99	100	80000	100	80000	1	100	80455	1	1	50	0	80023	222	1	479	0	23	80274	5000	6	1	12	33	160	366	5110	3	16	3	3	26704	1	6	6	0	80000	100	26716	26721	26716	26716	26722
80204	26714	200	67	58	0	0	19	0	1	23	12	26706	0	1	0	0	5	25	80100	100	80390	100	80000	500	1167326	49	23636	26715	26715	16637	3	16674	80100	200	80000	200	26715	56	1	1	80201	100	99	100	80000	100	80000	0	100	80466	110	3	36	0	80023	381	1	321	0	16	80295	5000	6	1	11	0	409	332	5110	3	16	3	3	26723	0	7	0	2	80000	100	26723	26722	26722	26721	26728
80204	26721	200	0	0	0	0	20	5	0	141	16	26699	0	0	0	0	4	25	80100	100	80000	100	80000	500	1166715	49	23642	26714	26714	16643	3	16672	80100	200	80000	200	26714	63	1	1	80201	100	99	100	80000	100	80000	0	100	80006	105	4	51	0	80024	162	0	585	0	16	80273	5000	6	1	13	17	479	345	5110	3	16	3	3	26713	0	7	0	2	80000	100	26734	26715	26716	26716	26715
80204	26721	200	77	63	0	0	41	6	0	199	16	26699	0	0	1	0	9	25	80100	100	80000	100	80000	500	1171515	49	23642	26720	26721	16647	3	16681	80100	200	80000	200	26708	56	1	1	80201	100	99	100	80000	100	80000	0	100	80329	209	1	50	0	80035	283	0	77	0	24	80279	5000	6	2	23	17	276	245	5110	3	16	3	3	26719	0	7	6	2	80000	100	26721	26722	26722	26722	26721
80204	26713	200	74	29	0	0	34	0	0	18	0	26773	10	1	0	0	4	25	80100	100	80000	100	80000	500	1166840	49	23640	26724	26716	16646	3	16673	80100	200	80000	200	26726	62	1	1	80201	100	99	100	80000	100	80000	0	100	80571	0	0	36	0	80025	104	1	352	0	24	80104	5000	6	2	22	33	392	115	5110	3	16	3	3	26722	0	7	0	2	80000	100	26721	27179	26731	26728	26722
80204	26720	200	68	0	0	0	34	0	0	7	0	26714	6	0	1	0	4	25	80100	100	80000	100	80000	500	1167881	49	23656	26730	26723	16640	3	16680	80100	200	80000	200	26714	70	1	1	80201	100	99	100	80000	100	80000	0	100	80110	0	1	17	0	80034	509	0	87	0	35	80160	5000	12	1	12	33	482	501	5110	3	16	3	3	26717	0	7	6	2	80000	100	26732	26716	27313	26715	26715
80204	26721	200	79	6	0	0	50	0	0	0	0	26706	5	2	1	0	3	25	80100	100	80000	100	80000	500	1166632	49	23646	26715	26757	17059	3	16672	80100	200	80000	200	26721	56	1	1	80201	100	99	100	80000	100	80000	0	100	80337	64	1	0	0	80025	482	0	115	10	21	80021	5000	12	1	11	33	396	450	5110	3	16	3	3	26718	1	7	6	2	80000	100	26728	26729	26724	26722	26721
80204	26723	200	14	72	0	0	36	0	0	114	0	26753	0	0	2	2	50	25	80100	100	80000	100	80000	500	1166936	49	23640	26714	26722	16640	21	16672	80100	200	80000	200	26713	62	1	1	80201	100	99	100	80000	100	80000	0	100	80302	9	1	51	0	80027	134	0	428	0	17	80277	5000	18	1	23	17	102	307	5110	3	16	3	3	26724	0	6	6	2	80000	100	26722	26723	26717	26716	26723

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3437

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	1e	20	22	29	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	b6	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80024	27697	206	0	0	0	3	1	1616	103	1	0	0	26	152	27495	133	1089	63	92	470	25	80010	10	80130	10	80000	50	1204160	1	49	24422	27478	27464	17470	3	17441	80010	20	80000	20	27596	70	1	1	80021	10	9	0	10	80000	10	80000	10	80129	0	13	497	190	81409	166	4	171	16	1386	81633	5000	10	167	29	1467	10	331	0	35	55	0	5020	17	16	9	10	27572	14	30	16	11	80000	10	27492	27470	27523	27481	27400
80024	27461	206	0	0	0	0	0	1547	103	1	0	9	12	88	27418	114	961	35	155	533	25	80010	10	80000	10	80000	50	1203395	0	49	24383	27480	27491	17403	3	17482	80010	20	80000	20	27553	75	1	1	80021	10	9	0	10	80000	10	80000	10	80209	0	17	395	191	81506	125	2	97	72	1370	81535	5000	10	84	16	1455	10	252	0	10	226	0	5020	6	16	10	10	27440	16	24	22	6	80000	10	27496	27493	27485	27490	27501
80024	27428	205	0	0	1	0	0	1533	127	1	0	1	30	40	27544	115	1202	62	107	534	25	80010	10	80000	10	80000	50	1203138	0	49	24415	27470	27509	17457	3	17442	80010	20	80000	20	27625	75	1	1	80021	10	9	0	10	80000	10	80000	10	80220	0	14	479	183	81266	74	1	127	40	1465	81698	5000	10	106	24	1372	10	327	0	46	5	0	5052	12	16	6	12	27475	22	34	16	19	80000	10	27455	27462	27465	27500	27442
80024	27492	206	0	0	0	0	0	1629	21	1	0	0	15	80	27445	84	1158	57	106	508	25	80010	10	80000	10	80000	50	1204021	0	49	24399	27476	27444	17402	3	17414	80010	20	80000	20	27609	75	1	1	80021	10	9	1	10	80000	10	80000	10	80156	0	16	689	192	81478	143	3	125	24	1450	81547	5000	10	77	22	1457	10	365	0	40	0	0	5020	11	16	13	12	27427	16	13	10	7	80000	10	27496	27457	27458	27514	27446
80024	27440	206	0	0	0	0	0	1500	128	1	0	1	12	44	27491	54	1025	140	153	525	25	80010	10	80000	10	80000	50	1203521	0	49	24365	27409	27445	17389	3	17409	80010	20	80000	20	27571	78	1	1	80021	10	9	0	10	80000	10	80000	10	80150	0	13	473	189	81493	115	2	38	0	1433	81711	5000	10	91	19	1465	10	406	0	9	99	1	5020	12	16	7	13	27448	17	27	13	9	80000	10	27520	27550	27476	27501	27544
80024	27460	205	0	0	2	0	0	1465	85	1	0	0	25	64	27471	125	1105	99	53	521	25	80010	10	80000	10	80000	50	1205307	0	49	24340	27437	27468	17362	3	17363	80010	20	80000	20	27648	75	1	1	80021	10	9	0	10	80000	10	80000	10	80188	0	16	490	183	81523	118	4	132	44	1567	81409	5000	10	78	15	1418	10	274	0	33	53	0	5020	11	16	11	11	27531	16	22	16	13	80000	10	27447	27537	27515	27492	27562
80024	27463	206	0	0	0	0	0	1629	56	0	0	0	29	0	27453	123	1128	50	115	528	25	80010	10	80000	10	80000	50	1207039	0	49	24445	27459	27571	17389	3	17473	80010	20	80000	20	27612	75	1	1	80021	10	9	0	10	80000	10	80000	10	80162	0	16	372	182	81464	128	1	140	18	1415	81523	5000	10	94	16	1491	10	436	0	30	22	0	5020	10	16	11	9	27513	18	13	16	4	80000	10	27439	27443	27452	27480	27501
80024	27504	206	0	1	0	0	0	1645	150	1	0	0	20	64	27456	97	916	66	150	511	25	80010	10	80000	10	80000	50	1202882	0	49	24535	27491	27478	17437	3	17466	80010	20	80000	20	27621	70	1	1	80021	10	9	0	10	80000	10	80000	10	80244	0	9	489	192	81376	125	2	213	90	1497	81476	5000	10	79	18	1442	10	326	0	23	119	0	5020	12	16	10	10	27451	17	26	29	3	80000	10	27493	27490	27482	27480	27473
80024	27507	206	0	0	1	0	0	1696	148	1	0	0	27	52	27463	89	1061	64	144	494	25	80010	10	80000	10	80000	50	1206026	1	49	24402	27459	27498	17377	3	17447	80010	20	80000	20	27630	75	1	1	80021	10	9	0	10	80000	10	80000	10	80131	0	10	492	189	81496	144	3	183	12	1466	81448	5000	10	98	23	1432	10	412	0	23	166	0	5020	7	16	11	10	27455	15	23	25	8	80000	10	27532	27463	27531	27616	27499
80024	27493	205	0	1	0	0	0	1623	92	1	0	0	22	48	27459	63	1108	67	101	486	25	80010	10	80000	10	80000	50	1204610	1	49	24458	27521	27490	17400	3	17465	80010	20	80000	20	27537	82	1	1	80021	10	9	0	10	80000	10	80000	10	80164	2	14	400	182	81397	169	3	134	60	1404	81494	5000	10	91	20	1634	10	273	0	38	65	0	5020	12	16	11	10	27521	16	14	33	13	80000	10	27448	27503	27529	27457	27468

LDR (literal, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations