Firestorm: UDIV (fast, 32-bit) measurements

Code:

  udiv w0, w1, w2

Initialization

  mov w1, #0
  mov w2, #0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2038	15	0	61	950	25	1000	1000	1000	53725	0	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	0	61	950	25	1000	1000	1000	53725	0	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	0	178	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	21	61	950	25	1000	1000	1000	53725	0	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	0	0	0	73	1	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	0	82	950	25	1000	1000	1000	53725	0	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	0	0	0	87	1	16	1	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	16	0	61	950	25	1000	1000	1000	53725	0	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	0	0	0	73	1	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	16	0	61	950	25	1000	1000	1000	53725	0	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	16	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	0	0	0	73	1	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	0	61	950	25	1000	1000	1000	53725	0	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	0	0	0	73	1	16	1	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	0	61	950	25	1000	1000	1000	53725	0	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039

Test 2: Latency 1->2

Chain cycles: 2

Code:

  udiv w0, w1, w2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov w1, #0
  mov w2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	90035	674	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1910	2	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	30	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	726	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1910	1	16	1	1	89836	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90066	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	726	81145	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	3	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	90035	675	0	0	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	6	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	2	89751	30008	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	726	81210	25	30010	30010	30010	8522901	1	49	86955	0	90035	90035	85922	3	86265	30113	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	6	0	1890	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	61	81210	25	30010	30016	30010	8522901	1	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	2	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30022	10	9	10	30010	10	0	0	0	0	1890	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	105	81210	25	30010	30010	30010	8522901	1	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	3	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	9	0	103	81210	25	30010	30010	30010	8522901	1	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	0	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	726	81210	25	30010	30010	30010	8522901	1	49	86955	0	90035	90035	85922	12	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	2	0	0	1890	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036

Test 3: Latency 1->3

Chain cycles: 2

Code:

  udiv w0, w1, w2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov w1, #0
  mov w2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	90035	674	0	0	0	0	0	0	103	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1	0	2076	0	0	0	1910	2	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30202	100	99	100	30100	100	0	0	0	0	0	0	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	0	0	0	1910	0	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	231	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	1	8	0	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	4	0	0	0	536	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	3	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90214	90036
30204	90035	674	0	0	0	0	573	0	251	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85928	3	86243	30100	30200	60200	90035	176	5	1	30201	100	99	100	30100	100	0	0	0	0	0	0	3	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	3	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90068	90036
30204	90035	674	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	3	4	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	90074	674	0	1361	81210	25	30010	30010	30010	8520582	1	49	86998	0	90035	90035	85922	7	86265	30416	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	5	16	0	3	5	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	61	81210	25	30010	30010	30010	8522901	0	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	3	0	0	0	1890	5	16	0	3	5	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	3	16	0	3	5	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	60	0	0	0	1890	5	16	0	5	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	61	81210	25	30010	30010	30010	8522901	0	49	86955	0	90076	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	3	16	0	5	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	61	81210	25	30010	30010	30010	8522901	0	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	5	16	0	5	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	251	81210	25	30010	30010	30010	8522901	0	49	86955	3	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	1	0	0	0	1890	3	16	0	3	5	89821	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	61	81210	25	30010	30010	30010	8522901	0	49	86955	0	90035	90066	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	3	16	0	5	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	3	16	0	3	5	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	61	81210	25	30010	30010	30010	8522901	0	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	9	0	0	1890	3	16	0	5	7	89751	30000	30010	90036	90036	90036	90036	90036

Test 4: throughput

Count: 8

Code:

  udiv w0, w8, w9
  udiv w1, w8, w9
  udiv w2, w8, w9
  udiv w3, w8, w9
  udiv w4, w8, w9
  udiv w5, w8, w9
  udiv w6, w8, w9
  udiv w7, w8, w9

Initialization

  mov w8, #0
  mov w9, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80204	160080	1198	0	0	0	726	79950	25	80100	80100	80100	4399225	1	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	2	16	1	1	159980	80000	2	80100	160039	160039	160039	160039	160039
80204	160038	1198	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	6	0	5110	1	17	1	1	159980	80000	0	80100	160039	160039	160039	160039	160039
80204	160038	1198	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	153929	0	160038	160038	149901	3	149996	80100	80200	160200	160229	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	2	16	1	1	159980	80000	0	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	48	61	79950	25	80100	80100	80100	4399225	0	49	156958	0	160038	160038	149901	18	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	0	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	2	129	1	2	160943	80425	0	80100	161347	161393	161103	160961	161486
80204	161731	1210	1	1	0	61	79950	25	80100	80100	80100	4399225	1	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	0	80100	160039	160039	160039	160039	160039
80204	160038	1198	0	0	0	61	79950	25	80100	80112	80100	4399225	0	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5123	1	16	1	1	159980	80000	0	80100	160039	160039	160039	160039	160039
80204	160038	1198	0	0	0	1135	79950	25	80100	80100	80100	4399225	1	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	0	80100	160039	160039	160039	160039	160039
80204	160038	1198	0	0	0	726	79950	25	80100	80100	80100	4399225	0	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	8	0	0	5110	1	16	1	1	160032	80000	0	80100	160039	160039	160039	160039	160039
80204	160038	1198	0	0	0	6538	79950	25	80100	80100	80100	4399225	0	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	0	80100	160039	160039	160039	160078	160039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	eb	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	160038	1199	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160078	149923	3	150018	80010	80080	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	12	0	8	16	0	0	4	2	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	0	6940	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	2	0	0	0	0	5020	3	0	2	16	0	0	2	4	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	0	428	79950	25	80010	80010	80048	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	2	16	0	0	4	2	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80218	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	3	0	4	16	0	0	2	5	159980	80000	0	0	80010	160039	160039	160081	160039	160039
80024	160038	1199	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	4	16	0	0	2	4	159980	80000	0	0	80010	160039	160039	160039	160077	160039
80024	160038	1199	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	4	16	0	0	4	2	159980	80000	18	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150036	80049	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	4	16	0	0	4	2	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	3	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	4	17	0	0	4	2	159980	80000	0	0	80010	160039	160077	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80167	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	2	16	0	0	3	4	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	530	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	4	16	0	0	4	4	159980	80000	0	0	80010	160039	160039	160039	160039	160039

UDIV (fast, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations