Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ldrh w0, [x6, #8]
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | 92 | inst int load (95) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | f5 | f6 | f7 | f8 | fd |
| 1005 | 403 | 3 | 1 | 1 | 0 | 1 | 1 | 1 | 21 | 1 | 0 | 1 | 359 | 0 | 0 | 1 | 0 | 25 | 1000 | 1000 | 1000 | 15208 | 398 | 398 | 197 | 3 | 256 | 1000 | 1000 | 1000 | 374 | 77 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1020 | 20 | 43 | 1019 | 1 | 0 | 1 | 21 | 1000 | 6 | 1 | 19 | 0 | 19 | 1 | 73 | 1 | 16 | 1 | 1 | 399 | 14 | 0 | 7 | 1000 | 375 | 375 | 399 | 399 | 375 |
| 1004 | 398 | 3 | 0 | 0 | 0 | 0 | 0 | 1 | 44 | 1 | 0 | 1 | 389 | 0 | 7 | 7 | 20 | 25 | 1000 | 1000 | 1000 | 15559 | 381 | 403 | 204 | 3 | 261 | 1000 | 1000 | 1000 | 403 | 85 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 0 | 43 | 1039 | 0 | 0 | 0 | 39 | 1000 | 0 | 1 | 0 | 44 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 395 | 13 | 13 | 0 | 1000 | 404 | 404 | 387 | 382 | 404 |
| 1004 | 403 | 3 | 1 | 1 | 1 | 1 | 1 | 1 | 69 | 0 | 0 | 1 | 389 | 2 | 1 | 1 | 0 | 25 | 1000 | 1000 | 1000 | 15267 | 398 | 374 | 197 | 3 | 232 | 1000 | 1000 | 1000 | 394 | 56 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 1 | 1018 | 19 | 0 | 1059 | 1 | 0 | 1 | 61 | 1039 | 6 | 1 | 59 | 0 | 19 | 0 | 73 | 1 | 16 | 1 | 1 | 378 | 10 | 10 | 4 | 1000 | 375 | 375 | 395 | 375 | 395 |
| 1004 | 394 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 1 | 388 | 3 | 7 | 7 | 20 | 25 | 1000 | 1000 | 1000 | 15957 | 403 | 403 | 204 | 3 | 239 | 1000 | 1000 | 1000 | 403 | 85 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 0 | 43 | 1000 | 0 | 0 | 0 | 42 | 1039 | 6 | 1 | 0 | 43 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 391 | 13 | 0 | 5 | 1000 | 404 | 404 | 382 | 404 | 403 |
| 1004 | 402 | 3 | 1 | 1 | 1 | 0 | 0 | 0 | 67 | 1 | 0 | 3 | 379 | 0 | 12 | 6 | 0 | 25 | 1000 | 1000 | 1000 | 15037 | 394 | 394 | 216 | 3 | 256 | 1000 | 1000 | 1000 | 398 | 77 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1019 | 19 | 43 | 1019 | 1 | 0 | 0 | 21 | 1040 | 0 | 1 | 58 | 0 | 19 | 1 | 73 | 1 | 16 | 1 | 1 | 379 | 10 | 10 | 7 | 1000 | 399 | 399 | 399 | 375 | 399 |
| 1004 | 398 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 366 | 2 | 0 | 7 | 0 | 25 | 1000 | 1000 | 1000 | 15555 | 381 | 403 | 225 | 3 | 261 | 1000 | 1000 | 1000 | 403 | 85 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 1 | 1000 | 0 | 43 | 1038 | 0 | 0 | 0 | 0 | 1000 | 0 | 1 | 38 | 44 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 395 | 13 | 0 | 0 | 1000 | 382 | 385 | 404 | 382 | 404 |
| 1004 | 403 | 3 | 1 | 0 | 1 | 1 | 0 | 0 | 21 | 0 | 0 | 2 | 359 | 2 | 1 | 0 | 19 | 25 | 1000 | 1000 | 1000 | 15304 | 398 | 398 | 221 | 3 | 256 | 1000 | 1000 | 1000 | 398 | 77 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1019 | 20 | 0 | 1058 | 1 | 0 | 0 | 61 | 1040 | 6 | 0 | 58 | 0 | 19 | 0 | 73 | 1 | 16 | 1 | 1 | 378 | 14 | 10 | 0 | 1000 | 399 | 399 | 375 | 399 | 375 |
| 1004 | 398 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 359 | 2 | 0 | 1 | 19 | 25 | 1000 | 1000 | 1000 | 15274 | 398 | 398 | 197 | 3 | 232 | 1000 | 1000 | 1000 | 398 | 77 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1019 | 19 | 43 | 1059 | 1 | 0 | 0 | 63 | 1040 | 6 | 0 | 59 | 0 | 19 | 1 | 73 | 1 | 16 | 1 | 1 | 379 | 10 | 10 | 0 | 1000 | 399 | 399 | 375 | 399 | 399 |
| 1004 | 399 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 366 | 0 | 0 | 0 | 19 | 25 | 1000 | 1000 | 1000 | 15526 | 403 | 381 | 204 | 3 | 261 | 1000 | 1000 | 1000 | 402 | 64 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 0 | 0 | 1038 | 0 | 0 | 0 | 50 | 1038 | 6 | 1 | 39 | 44 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 391 | 13 | 0 | 5 | 1000 | 404 | 403 | 382 | 404 | 383 |
| 1004 | 403 | 3 | 1 | 0 | 1 | 1 | 0 | 0 | 67 | 0 | 0 | 0 | 388 | 3 | 7 | 7 | 20 | 25 | 1000 | 1000 | 1000 | 15509 | 382 | 403 | 204 | 3 | 239 | 1000 | 1000 | 1000 | 403 | 86 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 1 | 1020 | 20 | 0 | 1058 | 1 | 0 | 0 | 21 | 1000 | 0 | 1 | 58 | 43 | 19 | 0 | 73 | 1 | 16 | 1 | 1 | 400 | 10 | 0 | 7 | 1000 | 399 | 399 | 399 | 399 | 375 |
Chain cycles: 3
Code:
ldrh w0, [x6, #8] eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 4.0050
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 23 | 3a | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6b | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 40205 | 70051 | 525 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 70041 | 69787 | 59715 | 25 | 40104 | 30103 | 10002 | 30100 | 10000 | 616059 | 3342494 | 0 | 49 | 66961 | 0 | 70056 | 70041 | 64637 | 0 | 3 | 64959 | 40100 | 30200 | 10000 | 60200 | 10000 | 70051 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2610 | 5 | 71 | 1 | 1 | 69798 | 30003 | 0 | 0 | 9 | 10000 | 30100 | 70051 | 70048 | 70051 | 70051 | 70051 |
| 40204 | 70050 | 524 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 70026 | 69787 | 59715 | 25 | 40104 | 30106 | 10002 | 30100 | 10000 | 616059 | 3342494 | 0 | 49 | 66961 | 0 | 70053 | 70056 | 64661 | 0 | 3 | 64959 | 40100 | 30200 | 10000 | 60200 | 10000 | 70074 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2610 | 1 | 71 | 1 | 1 | 69813 | 30003 | 9 | 6 | 6 | 10000 | 30100 | 70036 | 70051 | 70051 | 70051 | 70051 |
| 40204 | 70035 | 524 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 70026 | 69787 | 59715 | 25 | 40104 | 30106 | 10001 | 30100 | 10000 | 616078 | 3342494 | 1 | 49 | 66976 | 0 | 70041 | 70056 | 64652 | 0 | 3 | 64944 | 40100 | 30200 | 10000 | 60200 | 10000 | 70077 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 2610 | 1 | 71 | 1 | 1 | 69798 | 30003 | 9 | 6 | 9 | 10000 | 30100 | 70051 | 70036 | 70051 | 70048 | 70036 |
| 40204 | 70035 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 70032 | 69764 | 59709 | 25 | 40104 | 30103 | 10000 | 30100 | 10000 | 616005 | 3342206 | 0 | 49 | 66955 | 0 | 70050 | 70050 | 64646 | 0 | 3 | 64953 | 40100 | 30200 | 10000 | 60200 | 10000 | 70053 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10001 | 3 | 0 | 10001 | 0 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 2610 | 1 | 71 | 1 | 1 | 69813 | 30000 | 9 | 0 | 9 | 10000 | 30100 | 70036 | 70036 | 70048 | 70051 | 70048 |
| 40204 | 70035 | 525 | 0 | 0 | 0 | 0 | 0 | 25 | 0 | 0 | 0 | 70035 | 69764 | 59709 | 25 | 40100 | 30103 | 10001 | 30100 | 10000 | 616005 | 3342206 | 0 | 49 | 66970 | 0 | 70050 | 70035 | 64646 | 0 | 3 | 64938 | 40100 | 30200 | 10000 | 60200 | 10000 | 70116 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2610 | 1 | 71 | 1 | 1 | 69804 | 30006 | 9 | 6 | 9 | 10000 | 30100 | 70057 | 70057 | 70057 | 70042 | 70042 |
| 40204 | 70041 | 525 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 70032 | 69781 | 59706 | 25 | 40104 | 30100 | 10001 | 30100 | 10000 | 616005 | 3342206 | 0 | 49 | 66955 | 0 | 70050 | 70052 | 64649 | 0 | 3 | 64953 | 40100 | 30200 | 10000 | 60200 | 10000 | 70073 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 2610 | 1 | 71 | 1 | 1 | 69819 | 30003 | 9 | 0 | 9 | 10000 | 30100 | 70057 | 70057 | 70057 | 70054 | 70058 |
| 40204 | 70043 | 524 | 1 | 1 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 70026 | 69767 | 59695 | 25 | 40104 | 30103 | 10001 | 30100 | 10051 | 616059 | 3342206 | 0 | 49 | 66970 | 0 | 70314 | 70050 | 64695 | 0 | 3 | 64991 | 40294 | 30200 | 10000 | 60200 | 10000 | 70050 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2610 | 1 | 71 | 1 | 1 | 69819 | 30006 | 9 | 6 | 9 | 10000 | 30100 | 70059 | 70057 | 70057 | 70057 | 70042 |
| 40204 | 70056 | 524 | 1 | 0 | 1 | 0 | 0 | 2 | 1 | 0 | 0 | 70032 | 69781 | 59709 | 25 | 40100 | 30103 | 10000 | 30100 | 10000 | 616032 | 3342350 | 0 | 49 | 66955 | 0 | 70050 | 70050 | 64631 | 0 | 3 | 64939 | 40100 | 30200 | 10000 | 60200 | 10000 | 70084 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2610 | 1 | 107 | 1 | 1 | 69813 | 30000 | 9 | 6 | 9 | 10000 | 30100 | 70051 | 70053 | 70039 | 70050 | 70052 |
| 40204 | 70047 | 524 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 70026 | 69787 | 59715 | 25 | 40108 | 30103 | 10002 | 30100 | 10000 | 616078 | 3342350 | 0 | 49 | 66961 | 0 | 70041 | 70041 | 64652 | 0 | 3 | 64959 | 40100 | 30200 | 10000 | 60200 | 10000 | 70420 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2610 | 2 | 71 | 1 | 1 | 69804 | 30006 | 9 | 6 | 9 | 10000 | 30100 | 70054 | 70042 | 70042 | 70042 | 70042 |
| 40204 | 70041 | 524 | 1 | 1 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 70020 | 69781 | 59695 | 25 | 40104 | 30103 | 10000 | 30100 | 10000 | 616005 | 3341470 | 1 | 49 | 66970 | 0 | 70050 | 70035 | 64646 | 0 | 3 | 64953 | 40100 | 30200 | 10000 | 60200 | 10000 | 70064 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10002 | 2 | 1 | 10002 | 0 | 0 | 1 | 1 | 10000 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 2610 | 1 | 71 | 1 | 1 | 69813 | 30000 | 0 | 0 | 9 | 10000 | 30100 | 70051 | 70051 | 70036 | 70051 | 70036 |
Result (median cycles for code, minus 3 chain cycles): 4.0051
| retire uop (01) | cycle (02) | 03 | 09 | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 3a | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 40025 | 70051 | 525 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 70036 | 69743 | 59710 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 617018 | 3342398 | 0 | 49 | 66971 | 70054 | 70036 | 64672 | 3 | 64976 | 40010 | 30020 | 10000 | 60020 | 10000 | 70054 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 2521 | 7 | 71 | 9 | 10 | 69798 | 30000 | 0 | 10 | 13 | 10000 | 30010 | 70052 | 70052 | 70036 | 70036 | 70052 |
| 40024 | 70035 | 525 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70039 | 69743 | 59710 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 617068 | 3341470 | 0 | 49 | 66971 | 70051 | 70051 | 64672 | 3 | 64960 | 40010 | 30020 | 10000 | 60020 | 10000 | 70035 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2521 | 7 | 71 | 7 | 8 | 69814 | 30003 | 13 | 10 | 10 | 10000 | 30010 | 70036 | 70055 | 70055 | 70052 | 70036 |
| 40024 | 70035 | 525 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70020 | 69778 | 59695 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 621254 | 3345470 | 0 | 49 | 66974 | 70054 | 70035 | 64672 | 3 | 64960 | 40010 | 30020 | 10000 | 60020 | 10000 | 70054 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 2521 | 8 | 71 | 8 | 9 | 69817 | 30003 | 13 | 10 | 0 | 10000 | 30010 | 70058 | 70036 | 70055 | 70055 | 70052 |
| 40024 | 70035 | 525 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70039 | 69775 | 59710 | 25 | 40010 | 30010 | 10001 | 30010 | 10000 | 617068 | 3342254 | 0 | 49 | 66971 | 70054 | 70051 | 64672 | 3 | 64979 | 40010 | 30020 | 10000 | 60020 | 10000 | 70051 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 2521 | 8 | 71 | 9 | 8 | 69814 | 30003 | 13 | 10 | 10 | 10000 | 30010 | 70036 | 70093 | 70052 | 70055 | 70055 |
| 40024 | 70051 | 525 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 70039 | 69778 | 59713 | 25 | 40014 | 30010 | 10000 | 30010 | 10000 | 617018 | 3341470 | 0 | 49 | 66974 | 70035 | 70035 | 64672 | 3 | 64960 | 40010 | 30020 | 10000 | 60020 | 10000 | 70054 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 1 | 0 | 10000 | 1 | 0 | 0 | 2521 | 10 | 71 | 8 | 8 | 69798 | 30000 | 13 | 13 | 10 | 10000 | 30010 | 70055 | 70055 | 70055 | 70055 | 70055 |
| 40024 | 70054 | 525 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70039 | 69778 | 59695 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 617018 | 3342423 | 0 | 49 | 66955 | 70035 | 70051 | 64653 | 3 | 64960 | 40010 | 30020 | 10000 | 60020 | 10000 | 70051 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 2521 | 8 | 71 | 9 | 10 | 69817 | 30003 | 0 | 10 | 10 | 10000 | 30010 | 70055 | 70055 | 70055 | 70036 | 70036 |
| 40024 | 70054 | 524 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 70036 | 69780 | 59695 | 25 | 40010 | 30013 | 10001 | 30010 | 10000 | 616991 | 3342398 | 0 | 49 | 66955 | 70054 | 70035 | 64672 | 3 | 64960 | 40010 | 30020 | 10000 | 60020 | 10000 | 70051 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 0 | 1 | 0 | 2521 | 8 | 71 | 10 | 8 | 69817 | 30000 | 13 | 0 | 13 | 10000 | 30010 | 70055 | 70055 | 70052 | 70036 | 70036 |
| 40024 | 70054 | 525 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 70020 | 69743 | 59695 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 617068 | 3341470 | 0 | 49 | 66974 | 70054 | 70054 | 64655 | 3 | 64979 | 40010 | 30020 | 10000 | 60020 | 10000 | 70054 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 2521 | 7 | 71 | 8 | 8 | 69814 | 30003 | 13 | 10 | 13 | 10000 | 30010 | 70055 | 70055 | 70036 | 70052 | 70036 |
| 40024 | 70054 | 524 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 70039 | 69778 | 59714 | 25 | 40014 | 30013 | 10000 | 30010 | 10000 | 617068 | 3341470 | 0 | 49 | 66974 | 70054 | 70051 | 64672 | 3 | 64979 | 40010 | 30020 | 10000 | 60020 | 10000 | 70035 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 2521 | 9 | 71 | 10 | 9 | 69798 | 30003 | 13 | 13 | 13 | 10000 | 30010 | 70055 | 70036 | 70055 | 70055 | 70055 |
| 40024 | 70035 | 525 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70039 | 69778 | 59713 | 25 | 40014 | 30013 | 10000 | 30010 | 10000 | 617000 | 3341470 | 0 | 49 | 66955 | 70054 | 70054 | 64672 | 3 | 64979 | 40010 | 30020 | 10000 | 60020 | 10000 | 70054 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2521 | 9 | 71 | 8 | 9 | 69798 | 30003 | 13 | 10 | 10 | 10000 | 30010 | 70052 | 70055 | 70036 | 70055 | 70052 |
Count: 8
Code:
ldrh w0, [x6, #8] ldrh w0, [x6, #8] ldrh w0, [x6, #8] ldrh w0, [x6, #8] ldrh w0, [x6, #8] ldrh w0, [x6, #8] ldrh w0, [x6, #8] ldrh w0, [x6, #8]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3342
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | 92 | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | a5 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80205 | 26736 | 200 | 1 | 1 | 1 | 1 | 1 | 66 | 1 | 3 | 26722 | 3 | 7 | 7 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1169949 | 0 | 49 | 23634 | 26737 | 26736 | 16642 | 6 | 16666 | 80115 | 200 | 80024 | 200 | 80024 | 26740 | 85 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 80000 | 100 | 80000 | 1 | 100 | 80020 | 20 | 0 | 0 | 80059 | 1 | 0 | 1 | 61 | 80039 | 6 | 0 | 58 | 43 | 19 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 26734 | 13 | 13 | 5 | 80000 | 100 | 26737 | 26737 | 26737 | 26737 | 26738 |
| 80204 | 26737 | 200 | 1 | 0 | 1 | 0 | 0 | 67 | 0 | 3 | 26722 | 3 | 7 | 7 | 18 | 25 | 80100 | 100 | 80000 | 100 | 80013 | 500 | 1167460 | 0 | 49 | 23634 | 26736 | 26737 | 16659 | 3 | 16694 | 80100 | 200 | 80000 | 200 | 80000 | 26743 | 64 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 21 | 0 | 0 | 80058 | 0 | 1 | 2 | 60 | 80039 | 6 | 1 | 59 | 43 | 19 | 0 | 1 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26733 | 13 | 13 | 5 | 80000 | 100 | 26715 | 26737 | 26738 | 26715 | 26737 |
| 80204 | 26736 | 200 | 1 | 1 | 0 | 0 | 0 | 66 | 1 | 2 | 26722 | 3 | 7 | 7 | 20 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167316 | 0 | 49 | 23657 | 26736 | 26736 | 16659 | 3 | 16694 | 80100 | 200 | 80000 | 200 | 80000 | 26929 | 85 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 19 | 43 | 0 | 80061 | 0 | 0 | 0 | 61 | 80040 | 0 | 1 | 59 | 43 | 19 | 0 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 27012 | 13 | 13 | 5 | 80000 | 100 | 26737 | 26741 | 26737 | 26737 | 26750 |
| 80204 | 26737 | 201 | 1 | 0 | 0 | 0 | 0 | 67 | 0 | 3 | 26721 | 3 | 7 | 7 | 20 | 35 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1169868 | 1 | 49 | 23656 | 26737 | 26736 | 16659 | 3 | 16694 | 80100 | 200 | 80000 | 200 | 80000 | 26736 | 85 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 21 | 43 | 0 | 80059 | 1 | 0 | 0 | 61 | 80040 | 6 | 0 | 59 | 43 | 19 | 1 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26734 | 13 | 13 | 5 | 80000 | 100 | 26737 | 26737 | 26715 | 26715 | 26737 |
| 80204 | 26736 | 200 | 1 | 1 | 1 | 0 | 0 | 70 | 0 | 3 | 26721 | 3 | 7 | 7 | 19 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167681 | 1 | 49 | 23656 | 26737 | 26736 | 16659 | 3 | 16694 | 80100 | 200 | 80000 | 200 | 80000 | 26739 | 85 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80019 | 19 | 43 | 0 | 80019 | 0 | 0 | 0 | 60 | 80000 | 6 | 1 | 59 | 43 | 19 | 1 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26733 | 13 | 13 | 5 | 80000 | 100 | 26741 | 26739 | 26737 | 26737 | 26738 |
| 80204 | 26714 | 201 | 1 | 0 | 0 | 0 | 0 | 66 | 1 | 3 | 26721 | 3 | 7 | 0 | 19 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1168432 | 0 | 49 | 23634 | 26737 | 26714 | 16659 | 3 | 16694 | 80100 | 200 | 80000 | 200 | 80000 | 26736 | 86 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 20 | 43 | 0 | 80060 | 0 | 0 | 0 | 60 | 80040 | 0 | 0 | 58 | 43 | 19 | 0 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26733 | 13 | 0 | 5 | 80000 | 100 | 26737 | 26737 | 26715 | 26737 | 26737 |
| 80204 | 26736 | 200 | 1 | 1 | 1 | 0 | 0 | 67 | 0 | 3 | 26721 | 0 | 7 | 0 | 18 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167460 | 1 | 49 | 23634 | 26736 | 26736 | 16658 | 3 | 16672 | 80100 | 200 | 80000 | 200 | 80000 | 26745 | 85 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 20 | 43 | 0 | 80059 | 0 | 0 | 0 | 21 | 80039 | 6 | 1 | 59 | 43 | 19 | 0 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26733 | 13 | 13 | 5 | 80000 | 100 | 26738 | 26715 | 26715 | 26737 | 26737 |
| 80204 | 26736 | 201 | 1 | 0 | 1 | 0 | 0 | 67 | 0 | 3 | 26721 | 3 | 7 | 7 | 19 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167555 | 0 | 49 | 23656 | 26736 | 26736 | 16642 | 3 | 16695 | 80100 | 200 | 80000 | 200 | 80000 | 26892 | 90 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80019 | 19 | 43 | 0 | 80019 | 0 | 1 | 1 | 61 | 80040 | 6 | 1 | 59 | 43 | 19 | 0 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26733 | 13 | 13 | 0 | 80000 | 100 | 26715 | 26738 | 26737 | 26715 | 26715 |
| 80204 | 26736 | 200 | 1 | 0 | 0 | 0 | 0 | 67 | 0 | 2 | 26721 | 0 | 9 | 7 | 19 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167474 | 0 | 49 | 23656 | 26742 | 26736 | 16658 | 3 | 16672 | 80100 | 200 | 80000 | 200 | 80000 | 26736 | 85 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 20 | 43 | 0 | 80058 | 1 | 0 | 1 | 61 | 80039 | 6 | 1 | 59 | 43 | 19 | 1 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26734 | 13 | 13 | 5 | 80000 | 100 | 26715 | 26737 | 26737 | 26715 | 26737 |
| 80204 | 26736 | 201 | 1 | 0 | 0 | 0 | 0 | 67 | 0 | 3 | 26721 | 3 | 0 | 7 | 19 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167555 | 0 | 49 | 23656 | 26736 | 26715 | 16659 | 3 | 16694 | 80100 | 200 | 80000 | 200 | 80193 | 26740 | 85 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80019 | 19 | 43 | 0 | 80058 | 1 | 0 | 0 | 61 | 80040 | 6 | 0 | 59 | 43 | 19 | 0 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26733 | 13 | 13 | 0 | 80000 | 100 | 26737 | 26737 | 26737 | 26738 | 26737 |
Result (median cycles for code divided by count): 0.3342
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80025 | 26736 | 200 | 1 | 1 | 1 | 1 | 67 | 1 | 0 | 3 | 26721 | 3 | 7 | 7 | 20 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1165304 | 1 | 49 | 23656 | 26715 | 26736 | 16681 | 3 | 16717 | 80010 | 20 | 80000 | 20 | 80000 | 26782 | 64 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80019 | 20 | 45 | 80059 | 0 | 0 | 1 | 61 | 80041 | 6 | 0 | 59 | 0 | 19 | 1 | 5020 | 4 | 3 | 16 | 1 | 1 | 26733 | 13 | 13 | 0 | 80000 | 10 | 26738 | 26716 | 26737 | 26740 | 26737 |
| 80024 | 26715 | 201 | 1 | 0 | 0 | 0 | 67 | 1 | 0 | 3 | 26721 | 3 | 0 | 9 | 20 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1167106 | 1 | 49 | 23634 | 26736 | 26737 | 16681 | 3 | 16716 | 80010 | 20 | 80000 | 20 | 80000 | 26740 | 85 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80019 | 20 | 43 | 80019 | 0 | 0 | 0 | 60 | 80000 | 6 | 0 | 59 | 44 | 19 | 1 | 5020 | 4 | 1 | 16 | 1 | 1 | 26733 | 0 | 0 | 5 | 80000 | 10 | 26737 | 26737 | 26737 | 26737 | 26737 |
| 80024 | 26736 | 200 | 1 | 0 | 0 | 1 | 67 | 0 | 0 | 3 | 26722 | 0 | 0 | 7 | 19 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1167109 | 1 | 49 | 23656 | 26736 | 26736 | 16681 | 3 | 16717 | 80010 | 20 | 80000 | 20 | 80000 | 26741 | 85 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80019 | 19 | 43 | 80019 | 0 | 0 | 0 | 21 | 80000 | 0 | 1 | 59 | 43 | 19 | 1 | 5020 | 4 | 2 | 16 | 1 | 1 | 26734 | 0 | 0 | 0 | 80000 | 10 | 26737 | 26738 | 26738 | 26738 | 26716 |
| 80024 | 26714 | 200 | 1 | 0 | 1 | 1 | 67 | 0 | 0 | 3 | 26722 | 2 | 0 | 0 | 22 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1167219 | 0 | 49 | 23657 | 26736 | 26736 | 16682 | 3 | 16717 | 80010 | 20 | 80000 | 20 | 80000 | 26727 | 85 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80020 | 21 | 43 | 80058 | 1 | 0 | 1 | 60 | 80040 | 6 | 1 | 59 | 43 | 19 | 1 | 5020 | 4 | 1 | 16 | 1 | 1 | 26733 | 13 | 13 | 5 | 80000 | 10 | 26738 | 26737 | 26738 | 26737 | 26737 |
| 80024 | 26736 | 200 | 1 | 1 | 0 | 1 | 21 | 0 | 0 | 0 | 26700 | 0 | 0 | 7 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1173975 | 0 | 49 | 23634 | 26715 | 26736 | 16659 | 3 | 16695 | 80010 | 20 | 80000 | 20 | 80000 | 26741 | 85 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80019 | 19 | 43 | 80059 | 0 | 0 | 2 | 21 | 80039 | 6 | 0 | 19 | 0 | 19 | 0 | 5020 | 4 | 1 | 16 | 1 | 1 | 26792 | 13 | 0 | 0 | 80000 | 10 | 26737 | 26737 | 26738 | 26738 | 26737 |
| 80024 | 26714 | 200 | 1 | 0 | 1 | 0 | 66 | 1 | 0 | 2 | 26722 | 2 | 7 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1167298 | 0 | 49 | 23656 | 26737 | 26736 | 16682 | 3 | 16717 | 80010 | 20 | 80000 | 20 | 80000 | 26741 | 85 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80021 | 20 | 0 | 80019 | 1 | 0 | 2 | 21 | 80000 | 6 | 0 | 58 | 43 | 18 | 1 | 5020 | 4 | 2 | 16 | 1 | 1 | 26736 | 13 | 13 | 0 | 80000 | 10 | 26716 | 26737 | 26737 | 26737 | 26716 |
| 80024 | 26736 | 200 | 1 | 0 | 0 | 0 | 67 | 0 | 0 | 2 | 26721 | 3 | 0 | 7 | 19 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1173975 | 0 | 49 | 23656 | 26737 | 26736 | 16681 | 3 | 16716 | 80010 | 20 | 80000 | 20 | 80000 | 26717 | 85 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80019 | 19 | 0 | 80019 | 1 | 1 | 1 | 60 | 80000 | 0 | 1 | 59 | 44 | 19 | 0 | 5020 | 4 | 2 | 16 | 1 | 1 | 26733 | 13 | 13 | 5 | 80000 | 10 | 26737 | 26737 | 26737 | 26737 | 26737 |
| 80024 | 26714 | 200 | 1 | 1 | 0 | 0 | 67 | 0 | 0 | 2 | 26721 | 3 | 7 | 7 | 1 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1165304 | 1 | 49 | 23635 | 26714 | 26736 | 16681 | 3 | 16717 | 80010 | 20 | 80000 | 20 | 80000 | 26722 | 85 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80019 | 19 | 0 | 80019 | 1 | 0 | 1 | 64 | 80000 | 6 | 1 | 58 | 43 | 19 | 0 | 5020 | 4 | 2 | 16 | 1 | 1 | 26733 | 13 | 0 | 5 | 80000 | 10 | 26737 | 26737 | 26737 | 26737 | 26738 |
| 80024 | 26715 | 201 | 1 | 0 | 1 | 0 | 66 | 0 | 0 | 0 | 26722 | 2 | 0 | 7 | 19 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1167791 | 0 | 49 | 23656 | 26736 | 26737 | 16681 | 3 | 16716 | 80010 | 20 | 80000 | 20 | 80000 | 26716 | 85 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80019 | 20 | 43 | 80058 | 1 | 0 | 0 | 60 | 80000 | 6 | 0 | 19 | 43 | 19 | 1 | 5020 | 4 | 1 | 16 | 1 | 1 | 26733 | 13 | 13 | 0 | 80000 | 10 | 26737 | 26716 | 26738 | 26738 | 26737 |
| 80024 | 26736 | 200 | 1 | 0 | 1 | 0 | 67 | 1 | 0 | 0 | 26721 | 0 | 7 | 0 | 19 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1170622 | 0 | 49 | 23656 | 26736 | 26737 | 16681 | 3 | 16694 | 80010 | 20 | 80000 | 20 | 80000 | 26741 | 85 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80020 | 19 | 43 | 80019 | 0 | 0 | 0 | 21 | 80040 | 6 | 1 | 58 | 43 | 19 | 0 | 5020 | 4 | 1 | 16 | 1 | 1 | 26733 | 0 | 0 | 5 | 80000 | 10 | 26715 | 26737 | 26737 | 26737 | 26738 |