Firestorm: AUTIA measurements

Code:

  autia x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	70	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	1	12	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	132	0	26	0	0	5972	1001	1000	6030	6030	6030	6030	6030
1004	6029	76	0	0	55	4950	22	1001	1001	1000	52725	0	0	0	6029	6029	5670	3	5751	1000	0	0	6029	2203	1	1	1001	1000	0	0	132	0	26	0	0	5972	1001	1000	6030	6030	6030	6030	6030
1004	6029	76	0	0	55	4950	22	1001	1001	1000	52725	0	0	0	6029	6029	5670	3	5751	1000	0	0	6029	2203	1	1	1001	1000	2	0	132	0	26	0	0	5972	1001	1000	6030	6030	6030	6030	6030
1004	6029	75	0	0	55	4950	22	1001	1001	1000	52725	0	0	0	6029	6029	5670	3	5751	1000	0	0	6029	2203	1	1	1001	1000	0	0	132	0	26	0	0	5972	1001	1000	6030	6030	6030	6030	6030
1004	6029	76	0	0	99	4950	22	1001	1001	1000	52725	0	0	0	6029	6029	5684	3	5751	1000	0	0	6029	2203	1	1	1001	1000	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	61	0	0	103	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	64	0	12	103	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	12	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	19	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  autia x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	618	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	2	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	3	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	24	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	0	1248	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	623	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	3	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	0	61	59824	25	10205	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	623	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	0	726	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	621	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	616	0	0	0	0	0	0	0	0	0	209	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	0	12	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	1	0	0	0	640	2	79	2	3	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	0	0	0	82	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70054	614	0	0	0	0	0	0	0	0	0	2110	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	623	0	0	0	0	0	0	0	3	0	156	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	0	0	0	103	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	621	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	0	0	0	103	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70054	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  autia x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	ec	? int retires (ef)	f5	f6	f7	f8	fd
30204	80029	697	0	0	0	0	0	0	89	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	5	80	3	3	79794	20100	0	0	30100	80030	80030	80030	80030	80030
30204	80029	750	0	0	0	0	3	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	3	72	3	3	79794	20100	0	0	30100	80030	80030	80030	80030	80030
30204	80029	700	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	3	72	3	3	79794	20100	0	0	30100	80030	80030	80030	80030	80030
30204	80029	700	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	3	72	3	3	79794	20100	0	0	30100	80030	80030	80030	80030	80030
30204	80029	700	0	0	0	0	12	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	1	0	1910	3	72	3	3	79794	20100	0	0	30100	80030	80030	80030	80030	80030
30204	80029	748	0	0	0	0	0	0	76	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1929	3	72	3	3	79794	20100	0	0	30100	80030	80030	80030	80030	80030
30204	80029	750	0	0	0	0	0	0	61	69799	45	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	2	0	0	0	0	0	0	0	0	1910	3	72	3	3	79794	20100	0	0	30100	80030	80030	80030	80030	80030
30204	80029	699	1	0	0	0	0	0	726	69799	25	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	3	72	3	3	79794	20100	0	0	30100	80030	80030	80030	80030	80030
30204	80029	701	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	3	72	3	3	79794	20100	0	0	30100	80030	80030	80030	80030	80030
30204	80029	700	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	6	0	0	0	1910	3	72	3	3	79794	20100	0	0	30100	80030	80030	80030	80030	80030

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	80060	745	0	0	0	0	0	0	61	69799	0	25	20020	20020	20020	4952048	1	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	3	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	743	0	0	0	0	0	0	61	69799	0	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	2	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	783	0	0	0	0	0	0	89	69799	0	25	20020	20020	20086	4952048	0	49	76949	0	80029	80029	75961	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	2	72	0	2	2	79803	20015	30010	80030	80030	80030	80030	80030
30024	80029	697	0	0	0	0	0	0	251	69799	0	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	3	0	0	1890	2	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	701	0	0	0	0	12	0	61	69799	0	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	1	0	0	0	0	1890	2	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	1	0	0	12	0	61	69799	0	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	3	0	0	1890	2	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	700	0	0	0	0	0	0	61	69799	0	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	2	72	0	2	2	79856	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	726	69799	0	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	1	0	0	0	0	1890	2	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	61	69799	0	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40182	80029	144	2	1	30021	10	9	30010	0	1	0	3	0	0	1890	2	72	0	3	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	701	0	1	0	0	0	0	61	69799	0	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	2	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030

Test 4: throughput

Count: 8

Code:

  autia x0, x8
  autia x1, x8
  autia x2, x8
  autia x3, x8
  autia x4, x8
  autia x5, x8
  autia x6, x8
  autia x7, x8

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80041	699	0	0	0	0	0	0	0	0	77	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	3	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	747	0	0	0	0	0	0	0	0	329	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	698	0	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	714	0	0	0	0	0	0	0	0	678	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80288	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	699	0	0	0	0	0	0	0	0	225	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80126	80081	80217
80204	80035	702	0	0	0	0	0	3	0	0	35	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	701	0	0	0	0	0	0	0	0	63	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	12	0	0	133	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	0	0	175	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	12	0	0	35	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	33	2	2	80025	80100	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	80052	697	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80080	164	2	1	80021	10	9	80010	0	0	0	0	0	0	0	1	5020	5	25	4	4	80024	80010	0	0	0	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	3	0	1827	25	80020	80076	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	15	0	0	5020	4	25	4	2	80024	80010	0	0	0	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	1	0	0	12	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	3	0	0	5033	2	25	2	4	80024	80010	0	0	0	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	30	0	1660	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	2	0	0	0	0	0	5020	2	25	2	4	80024	80010	0	0	0	80010	80036	80036	80036	80036	80036
80024	80035	750	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80049	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	2	25	2	4	80024	80010	0	0	0	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	0	0	175	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	2	25	2	4	80024	80010	0	0	0	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	77000	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	4	25	4	2	80024	80010	0	0	0	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	2	1	80021	10	9	80010	0	0	0	1	0	0	0	0	5020	4	25	4	2	80024	80010	0	0	0	80010	80036	80036	80036	80036	80036
80024	80035	701	0	0	0	0	0	60	0	77	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	4	25	4	2	80024	80010	0	0	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	77	25	80041	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80042	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	4	25	4	2	80024	80010	0	0	0	80010	80036	80036	80036	80036	80036

AUTIA

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations