Firestorm: SUBS (sxtw, 32-bit) measurements

Code:

  subs w0, w0, w1, sxtw

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	7	0	82	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	6	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  subs w0, w0, w1, sxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	354	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	327	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	82	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	107	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	3	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	9	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	8	6	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	54	348	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  subs w0, w1, w0, sxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	61	9927	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	0	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	0	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	126	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	0	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	84	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	0	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	147	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	0	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	3	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	84	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	0	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	0	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	0	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	0	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	9	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	14	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	648500	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	13	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8809	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	10	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs w0, w1, w2, sxtw
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	3	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	82	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	82	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	82	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1320	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	149	0	0	0	0	0	0	0	82	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20298	152	0	1	5	0	540	440	0	1340	19923	126	20010	20120	20420	1299759	49	17137	20260	20172	17469	23	17635	20420	20488	30734	20264	64	6	1	20021	10	9	10	20010	10010	2	2	0	0	2	3848	0	0	1353	1	59	2	2	20164	20110	20010	20262	20262	20264	20220	20036
20024	20307	152	0	1	4	5	672	440	1	1311	19916	126	20120	20032	20502	1300387	49	17226	20263	20264	17477	28	17632	20420	20490	30734	20264	64	6	1	20021	10	9	10	20010	10010	0	0	3	1	0	4063	2	0	1353	1	60	3	2	19995	20110	20010	20266	20263	20263	20263	20263
20024	20309	152	0	1	5	1	804	352	0	1316	19914	46	20120	20120	20421	1301015	49	17182	20216	20264	17483	25	17658	20420	20489	30742	20307	64	6	1	20021	10	9	10	20010	10010	0	0	0	0	0	4065	4	0	1372	1	68	1	1	20200	20000	20010	20264	20264	20172	20262	20263
20024	20264	152	1	0	6	6	795	528	0	1325	19917	129	20142	20122	20420	1301011	49	17184	20307	20267	17491	23	17661	20420	20599	30020	20172	64	5	1	20021	10	9	10	20010	10010	0	0	2	1	0	2415	2	0	1336	1	59	3	2	20029	20088	20010	20265	20265	20127	20261	20081
20024	20264	152	1	0	5	5	534	440	0	840	19917	132	20032	20120	20422	1299758	49	17092	20218	20126	17472	26	17610	20420	20432	30733	20263	64	6	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	17	0	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	6	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	138	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	251	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	1	27	2	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs w0, w1, w2, sxtw
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	187	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	0	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	82	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	0	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	0	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	354	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	149	0	0	0	0	21	0	0	84	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	2	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	1	16	0	20012	20000	20100	20036	20081	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	9	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	3	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	149	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30194	20035	64	1	1	20021	10	9	10	20010	10010	1	3	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	251	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	4	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	4	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	3	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	42	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	1	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	5	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	100	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	5	0	0	1270	2	27	3	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	23	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	30	0	1270	2	27	2	3	19995	20000	20010	20036	20036	20036	20036	20036

Test 6: throughput

Count: 8

Code:

  subs w0, w8, w9, sxtw
  subs w1, w8, w9, sxtw
  subs w2, w8, w9, sxtw
  subs w3, w8, w9, sxtw
  subs w4, w8, w9, sxtw
  subs w5, w8, w9, sxtw
  subs w6, w8, w9, sxtw
  subs w7, w8, w9, sxtw

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26761	200	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	35	25	80100	80100	80178	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	176	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	201	0	0	0	0	0	0	0	35	25	80190	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	201	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	1	0	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	201	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26720	200	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	3	18	0	3	3	26702	80063	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	16	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	1	0	5020	0	3	18	0	3	2	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	3	0	5020	0	3	18	3	3	3	26702	80000	80010	26706	26706	26706	26706	26892
80024	26705	200	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23677	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	1	0	5020	0	3	18	0	3	2	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	3	18	0	3	3	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	199	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	1	0	5020	0	3	18	0	2	3	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	3	18	0	3	3	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	3	18	0	3	3	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	2	18	0	3	3	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	1	0	5020	0	2	18	0	3	3	26702	80000	80010	26706	26706	26706	26706	26706

SUBS (sxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations