Firestorm: BL measurements

Code:

  bl .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch call (8e)	inst branch taken (90)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	1818	16	0	35	25	1000	1000	1000	5000	0	36	2022	1954	3	16	1000	1000	1896	280	1	1	1001	1000	1000	1000	0	0	0	1946	0	0	465	1054	400	437	1997	1941	1973	1893	1895	1945
1004	1786	14	0	35	25	1000	1000	1000	5000	58	0	1966	1844	3	18	1000	1000	1872	312	1	1	1001	1000	1000	1000	0	0	0	1930	0	0	434	984	474	450	1921	2051	1907	1821	1955	1993
1004	2014	15	0	35	25	1000	1000	1000	5000	154	0	1954	1934	3	18	1000	1000	1794	268	1	1	1001	1000	1000	1000	0	0	0	1890	58	24	355	920	461	463	1791	1959	1897	1905	1931	1951
1004	1950	14	0	35	25	1000	1000	1000	5000	0	41	1980	1904	3	18	1000	1000	1844	302	1	1	1001	1000	1000	1000	0	0	0	1880	0	0	434	894	444	385	1909	1951	1779	2009	1953	1967
1004	2008	15	0	35	25	1000	1000	1000	5000	0	58	1972	1860	3	18	1000	1000	1952	268	1	1	1001	1000	1000	1000	0	0	0	1892	0	0	486	914	434	464	1927	1911	1839	1949	1959	1949
1004	1936	14	0	33	25	1000	1000	1000	5000	154	0	1994	1950	3	18	1000	1000	1948	262	1	1	1001	1000	1000	1000	0	0	0	1934	0	0	446	970	405	449	1885	1955	1973	1985	1835	1933
1004	1930	15	0	35	25	1000	1000	1000	5000	56	0	1872	1814	3	18	1000	1000	1944	266	1	1	1001	1000	1000	1000	0	1	0	1960	41	8	449	850	390	457	1805	2051	1947	1785	1935	1949
1004	2014	14	0	35	25	1000	1000	1000	5000	0	58	1984	1912	3	16	1000	1000	1920	264	1	1	1001	1000	1000	1000	0	0	0	1938	58	18	438	836	440	452	1917	1939	1983	1907	1987	2031
1004	1960	15	0	35	25	1000	1000	1000	5000	0	58	1916	1950	3	18	1000	1000	1932	304	1	1	1001	1000	1000	1000	0	0	0	1832	58	18	461	826	411	453	1829	1797	1943	1971	1967	1977
1004	2012	15	0	35	25	1000	1000	1000	5000	0	58	1934	1938	3	18	1000	1000	1930	318	1	1	1001	1000	1000	1000	0	0	0	1882	63	0	467	836	412	442	1821	2071	1931	1817	1965	1943

Count: 8

Code:

  bl .+4
  bl .+4
  bl .+4
  bl .+4
  bl .+4
  bl .+4
  bl .+4
  bl .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0091

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch call (8e)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80204	81152	606	0	0	0	28	28	80105	80105	80107	400530	0	21	49	77651	0	80738	80744	6	10	80107	80207	200	80730	232	1	1	80201	80100	80000	80099	100	100	100	0	0	0	1	1	1	80737	21	6	397	689	323	297	80724	100	80722	80713	80734	80731	80756
80204	80732	605	0	0	0	28	27	80105	80105	80107	400530	54	11	49	77631	0	80731	80749	7	10	80107	80207	200	80857	230	1	1	80201	80100	80000	80099	100	100	100	0	0	0	1	1	1	80721	11	6	286	637	326	297	80722	100	80747	80754	80762	80770	80713
80204	80728	605	0	0	0	28	27	80105	80105	80107	400530	149	0	49	77658	0	80732	80748	6	10	80107	80207	200	80757	228	1	1	80201	80100	80000	80099	100	100	100	0	0	0	1	1	1	80728	0	6	294	589	288	297	80723	100	80753	80769	80720	80715	80713
80204	80714	604	0	0	0	28	27	80105	80105	80107	400530	54	11	49	77657	0	80732	80745	6	10	80107	80207	200	80718	222	2	1	80201	80100	80000	80099	100	100	100	0	0	0	1	1	1	80705	21	6	299	615	314	324	80728	100	80733	80721	80759	80725	80761
80204	80744	605	0	0	0	28	27	80105	80105	80107	400530	54	11	49	77700	0	80762	80784	6	10	80107	80207	200	80757	224	1	1	80201	80100	80000	80099	100	100	100	0	0	0	1	1	1	80711	0	7	315	593	294	306	80707	100	80724	80719	80750	80779	80743
80204	80740	604	0	0	0	28	27	80105	80105	80107	400530	149	0	49	77627	0	80734	80756	6	10	80107	80207	200	80748	226	1	1	80201	80100	80000	80099	100	100	100	0	0	0	1	1	1	80697	16	7	336	617	283	315	81295	100	80715	80759	80761	80735	80733
80204	80717	605	0	0	9	28	27	80105	80105	80107	400530	142	0	49	77640	0	80710	80696	6	10	80107	80207	200	80717	224	1	1	80201	80100	80000	80099	100	100	100	3	0	0	1	1	1	80703	6	8	321	673	292	313	80705	100	80759	80780	80791	80724	80753
80204	80748	604	0	0	0	28	27	80105	80105	80107	400530	0	16	49	77628	0	80774	80738	6	10	80107	80207	200	80776	232	1	1	80201	80100	80000	80099	100	100	100	0	0	0	1	1	1	80767	0	10	307	611	301	276	80719	100	80731	80725	80731	80701	80754
80204	80736	605	0	0	0	132	28	80105	80105	80107	400530	149	0	49	77664	0	80734	80724	6	10	80107	80207	200	80758	232	1	1	80201	80100	80000	80099	100	100	100	0	0	0	1	1	1	80700	0	6	304	615	298	306	80735	100	80745	80753	80717	80748	80768
80204	80779	605	0	0	0	28	28	80105	80105	80107	400530	52	6	49	77674	3	80762	80781	6	10	80107	80207	200	80762	226	1	1	80201	80100	80000	80099	100	100	100	0	0	0	1	1	1	80741	0	6	317	675	311	290	80765	100	80722	80735	80699	80726	80741

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.9750

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch call (8e)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80024	238548	1786	0	0	0	0	28	28	80011	80011	80012	400058	0	7	49	235270	0	238338	238320	6	19	80012	80022	20	238326	474	1	1	80021	80010	80000	80009	10	10	10	0	0	0	0	1	1	1	238239	7	2	79017	158302	79085	79106	238284	10	238239	238149	238179	238106	238219
80024	238182	1784	0	0	0	0	28	28	80011	80011	80012	400058	0	7	49	235238	0	238312	238264	6	10	80012	80022	20	238164	470	1	1	80021	80010	80000	80009	10	10	10	0	0	0	0	1	1	1	238114	0	0	79048	158258	79011	79046	238105	10	238215	238145	238189	238115	238139
80024	238030	1784	0	0	0	0	34	28	80011	80011	80012	400058	0	7	49	235066	0	237892	238202	6	10	80012	80022	20	238126	468	1	1	80021	80010	80000	80009	10	10	10	0	0	0	0	1	1	1	238186	7	2	78880	158152	79028	79017	238081	10	238115	238199	238105	238155	238233
80024	238001	1783	0	0	0	1	34	28	80016	80011	80012	400058	0	7	49	235074	0	238092	238176	6	10	80012	80022	20	238022	468	2	1	80021	80010	80000	80009	10	10	10	0	0	1	0	1	1	1	237968	7	2	79037	158070	79005	79011	238061	10	238087	238117	238043	238091	238151
80024	238066	1783	0	0	0	1	699	28	80011	80011	80012	400058	157	0	49	235008	0	238053	238132	6	10	80012	80022	20	238166	466	1	1	80021	80010	80000	80009	10	10	10	0	0	0	0	1	1	1	238044	7	2	79033	158032	79048	78954	238115	10	237955	238077	238039	238027	238055
80024	238093	1784	0	0	0	1	34	28	80011	80011	80012	400058	0	7	49	234955	0	237980	238090	6	10	80012	80022	20	237952	470	1	1	80021	80010	80000	80009	10	10	10	0	0	0	0	1	1	1	238076	7	2	78978	157928	78970	78970	238009	10	238061	238041	238015	237965	238035
80024	238110	1782	0	0	0	0	699	28	80011	80011	80012	400058	157	0	49	234974	0	238120	237992	6	10	80012	80022	20	238018	464	1	1	80022	80010	80000	80009	10	10	10	0	0	0	0	1	1	1	238004	0	0	79027	158018	79022	79032	238067	10	238057	238131	237981	238061	238029
80024	238018	1783	0	0	0	1	34	39	80011	80011	80012	400058	0	7	49	234957	0	238087	238080	6	10	80012	80022	20	238008	470	1	1	80021	80010	80000	80009	10	10	10	0	0	0	0	1	1	1	238000	0	0	79025	158048	78974	78994	237955	10	237975	238059	238017	238063	238089
80024	238076	1783	0	0	0	1	888	28	80011	80011	80012	400058	157	0	49	235040	3	238034	238084	6	10	80012	80022	20	238114	464	1	1	80021	80010	80000	80009	10	10	10	0	0	0	0	1	1	1	238108	0	0	79013	158008	79012	79026	238151	10	238037	238113	238051	238015	238011
80024	238000	1784	0	30	0	0	28	28	80011	80011	80012	400058	0	12	49	235024	0	238080	238080	6	10	80012	80022	20	238070	468	1	1	80021	80010	80000	80009	10	10	10	0	0	0	0	1	1	1	238100	12	2	79006	157982	79012	79035	238037	10	237987	238021	237973	238043	238029

BL

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations