Firestorm: STLRB measurements

Code:

  stlrb w0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	1084	8	6	1	0	1069	20	25	1000	1000	1000	45344	0	1032	1084	815	3	905	1000	1000	2000	1047	1084	1	1	1001	1000	1000	1000	60	14	1000	0	0	1000	60	73	1	16	1	1	1081	0	19	15	1000	1085	1085	1085	1085	1085
1004	1084	8	0	0	0	1032	20	25	1000	1000	1000	45344	1	1032	1084	815	3	942	1000	1000	2000	1084	1084	1	1	1001	1000	1000	1000	60	14	1000	0	0	1000	60	73	1	16	1	1	1044	19	19	15	1000	1085	1085	1085	1085	1048
1004	1084	8	0	1	1	1069	20	25	1000	1000	1000	45344	1	1032	1047	815	3	942	1000	1000	2000	1084	1084	1	1	1001	1000	1000	1000	60	14	1000	0	0	1000	60	73	1	16	1	1	1081	19	19	15	1000	1085	1085	1085	1085	1085
1004	1084	8	0	0	1	1069	20	25	1000	1000	1000	45344	0	1032	1084	815	3	942	1000	1000	2000	1084	1084	1	1	1001	1000	1000	1000	60	14	1000	0	0	1000	60	73	1	16	1	1	1081	19	0	15	1000	1085	1085	1085	1085	1085
1004	1084	8	0	1	0	1069	0	25	1000	1000	1000	45344	1	1032	1084	815	3	942	1000	1000	2000	1047	1084	1	1	1001	1000	1000	1000	60	14	1000	0	0	1000	60	73	1	16	1	1	1081	19	19	15	1000	1085	1085	1085	1085	1085
1004	1047	8	0	1	0	1069	20	25	1000	1000	1000	43568	1	1032	1084	815	3	942	1000	1000	2000	1084	1084	1	1	1001	1000	1000	1000	60	14	1000	21	0	1000	60	73	1	16	1	1	1081	0	0	0	1000	1085	1085	1085	1085	1085
1004	1084	8	0	1	0	1069	20	25	1000	1000	1000	45344	1	1032	1084	815	3	942	1000	1000	2000	1084	1084	1	1	1001	1000	1000	1000	60	14	1000	0	0	1000	0	73	1	16	1	1	1081	19	19	15	1000	1085	1085	1085	1048	1085
1004	1084	8	0	0	1	1069	20	25	1000	1000	1000	45344	1	1032	1047	815	3	905	1000	1000	2000	1084	1084	1	1	1001	1000	1000	1000	60	0	1000	0	0	1000	60	73	1	16	1	1	1081	19	19	15	1000	1085	1085	1085	1085	1085
1004	1084	8	0	1	1	1069	20	25	1000	1000	1000	45344	1	1032	1084	815	3	942	1000	1000	2000	1084	1084	1	1	1001	1000	1000	1000	60	14	1000	0	0	1000	60	73	1	16	1	1	1081	19	0	15	1000	1085	1085	1085	1085	1085
1004	1047	8	0	1	1	1069	20	25	1000	1000	1000	43568	1	1032	1047	815	3	942	1000	1000	2000	1084	1084	1	1	1001	1000	1000	1000	60	14	1000	0	0	1000	60	73	1	16	1	1	1081	0	19	15	1000	1085	1085	1085	1085	1085

Count: 8

Code:

  stlrb w0, [x6]
  stlrb w0, [x6]
  stlrb w0, [x6]
  stlrb w0, [x6]
  stlrb w0, [x6]
  stlrb w0, [x6]
  stlrb w0, [x6]
  stlrb w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0011

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	80088	600	1	1	1	0	0	0	119	1	0	80073	16	25	80100	100	80000	100	80000	500	3758588	49	77008	80036	80088	69920	3	70047	80100	200	80000	200	160000	80089	63926	1	1	80201	100	99	100	80000	100	80000	100	80015	14	60	7	1	80015	0	0	15	80000	14	60	14	0	0	5110	1	16	1	1	80086	0	15	0	6	80000	100	80090	80089	80056	80089	80090
80204	80089	600	1	1	0	0	0	0	18	1	0	80043	12	25	80100	100	80000	100	80000	500	3758540	49	77009	80037	80089	69919	3	70047	80100	200	80000	200	160000	80055	63960	1	1	80201	100	99	100	80000	100	80000	100	80016	15	60	12	0	80014	1	0	14	80000	14	60	14	1	0	5110	1	16	1	1	80085	0	16	16	12	80000	100	80089	80089	80090	80056	80090
80204	80055	600	1	0	1	0	0	0	15	1	0	80073	0	25	80100	100	80000	100	80000	500	3758540	49	77009	80036	80089	69919	3	70047	80100	200	80000	200	160000	80055	63959	1	1	80201	100	99	100	80000	100	80000	100	80015	14	60	5	0	80014	0	2	14	80000	14	60	14	0	0	5110	1	16	1	1	80085	0	15	16	5	80000	100	80090	80090	80089	80089	80090
80204	80089	600	1	1	1	0	0	0	15	0	0	80074	0	25	80100	100	80000	100	80000	500	3758588	49	77009	80036	80089	69920	3	70046	80100	200	80000	200	160000	80088	63959	1	1	80201	100	99	100	80000	100	80000	100	80015	16	0	9	2	80014	1	2	14	80000	14	60	14	0	1	5110	1	16	1	1	80086	0	16	16	10	80000	100	80056	80090	80090	80090	80090
80204	80088	600	1	1	0	0	0	0	19	0	0	80074	12	25	80100	100	80000	100	80000	500	3758588	49	77009	80036	80088	69886	3	70047	80100	200	80000	200	160000	80088	63959	1	1	80201	100	99	100	80000	100	80000	100	80015	15	0	5	1	80015	0	2	17	80000	14	60	14	0	0	5110	1	16	1	1	80086	0	15	16	7	80000	100	80090	80089	80089	80090	80089
80204	80089	600	1	1	0	0	0	0	21	0	0	80074	16	25	80100	100	80000	100	80000	500	3758588	49	76975	80037	80055	69920	3	70047	80100	200	80000	200	160000	80089	63960	1	1	80201	100	99	100	80000	100	80000	100	80015	14	60	7	1	80014	0	2	14	80000	14	60	14	2	0	5110	1	16	1	1	80085	0	16	16	7	80000	100	80090	80090	80090	80090	80089
80204	80089	600	1	1	1	0	0	0	15	0	0	80073	12	25	80100	100	80000	100	80000	515	3758591	49	77008	80003	80088	69919	3	70013	80100	200	80000	200	160000	80089	63959	1	1	80201	100	99	100	80000	100	80000	100	80015	15	0	0	1	80074	0	0	15	80000	15	60	14	1	0	5110	1	16	1	1	80085	0	16	16	10	80000	100	80090	80090	80090	80089	80090
80204	80088	600	1	1	1	0	0	0	16	0	0	80074	12	25	80100	100	80000	100	80000	500	3758542	49	76975	80036	80089	69886	3	70047	80100	200	80000	200	160000	80088	63959	1	1	80201	100	99	100	80000	100	80000	100	80014	15	60	5	0	80014	0	0	14	80000	14	0	14	0	0	5110	1	16	1	1	80086	0	0	16	8	80000	100	80089	80056	80056	80089	80089
80204	80089	599	1	1	0	0	0	0	15	0	1	80073	11	25	80100	100	80000	100	80000	500	3758541	49	77008	80037	80089	69920	3	70013	80100	200	80000	200	160000	80089	63960	1	1	80201	100	99	100	80000	100	80000	100	80014	15	60	6	1	80014	0	0	14	80000	14	60	14	0	0	5110	1	16	1	1	80086	0	15	16	7	80000	100	80089	80089	80090	80056	80090
80204	80088	600	1	1	1	0	0	0	15	0	0	80073	12	25	80100	100	80000	100	80000	500	3758540	49	77009	80036	80089	69920	3	70047	80100	200	80000	200	160000	80089	75214	1	1	80201	100	99	100	80000	100	80000	100	80015	14	0	6	0	80015	0	0	14	80000	14	0	14	0	0	5110	1	16	1	1	80052	0	15	15	11	80000	100	80090	80090	80090	80090	80059

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0010

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	80089	600	1	1	1	1	0	0	69	15	0	0	80065	16	25	80010	10	80000	10	80000	50	3758152	0	49	76967	0	80028	80080	69933	3	70027	80010	20	80000	20	160000	80047	80080	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	0	0	0	80000	60	5020	0	7	16	0	4	6	80077	121	0	0	80000	10	80081	80081	80048	80081	80081
80024	80080	599	0	0	0	0	0	0	162	0	0	0	80032	0	25	80010	10	80000	10	80000	50	3758152	0	49	73980	0	80028	80047	70013	3	70110	80010	20	80605	20	160242	80185	80212	1	1	80021	10	9	10	80000	10	80000	10	80000	60	10	80000	0	0	3	80000	60	5020	0	4	16	0	4	6	80077	102	15	11	80000	10	80081	80081	80081	80081	80081
80024	80080	600	0	0	0	0	0	0	12	1	0	0	80032	16	25	80010	10	80000	10	80000	50	3758152	0	49	77000	0	80028	80080	69933	3	70060	80010	20	80000	20	160000	80047	80080	1	1	80021	10	9	10	80000	10	80000	10	80000	60	10	80000	0	0	0	80000	60	5020	0	4	16	0	6	7	80077	82	15	11	80000	10	80048	80081	80081	80081	80081
80024	80047	600	0	0	0	0	0	0	12	1	0	0	80065	0	25	80010	10	80000	10	80000	50	3758152	0	49	77000	0	80028	80080	69933	29	70146	80010	20	80242	20	160000	80080	80146	1	1	80021	10	9	10	80000	10	80000	10	80120	60	27	80120	0	2	0	80000	60	5020	0	4	16	0	4	6	80077	67	15	11	80000	10	80081	80048	80081	80081	80081
80024	80080	600	0	0	0	0	0	0	12	1	0	0	80065	16	25	80010	10	80000	10	80000	50	3756568	0	49	76967	0	80028	80080	69933	3	70060	80010	20	80000	20	160000	80080	80080	1	1	80021	10	9	10	80000	10	80000	10	80000	60	10	80000	1	0	0	80000	60	5020	0	6	16	0	4	6	80077	82	15	11	80000	10	80081	80147	80081	80081	80081
80024	80080	599	0	0	0	0	0	2	12	1	0	0	80032	0	25	80010	10	80000	10	80000	50	3756568	0	49	77000	0	79995	80047	69900	3	70027	80010	20	80000	20	160000	80047	80080	1	1	80021	10	9	10	80000	10	80000	10	80000	60	10	80000	0	0	0	80000	0	5020	0	6	16	0	6	4	80077	82	15	11	80000	10	80081	80081	80048	80048	80081
80024	80080	600	0	0	0	0	0	0	0	1	1	0	80065	16	25	80010	10	80000	10	80000	50	3758152	0	49	77000	0	80028	80080	69933	3	70027	80010	20	80000	20	160000	80047	80047	1	1	80021	10	9	10	80000	10	80000	10	80000	60	10	80000	0	0	0	80000	0	5020	0	6	16	0	6	4	80077	102	15	0	80000	10	80081	80081	80081	80048	80081
80024	80080	600	0	0	0	0	1	0	6	1	0	0	80065	16	25	80010	10	80000	10	80000	50	3758152	0	49	77000	0	80028	80080	69933	16	70060	80010	20	80000	20	160000	80080	80080	1	1	80021	10	9	10	80000	10	80000	10	80000	60	0	80000	0	0	0	80000	60	5020	0	6	16	0	4	6	80077	82	0	11	80000	10	80081	80081	80081	80081	80081
80024	80080	620	0	0	0	0	0	0	0	1	0	1	80069	20	25	80010	10	80000	10	80000	50	3758344	0	49	77004	0	80032	80047	69900	3	70064	80010	20	80000	20	160000	80047	80084	1	1	80021	10	9	10	80000	10	80000	10	80000	60	0	80000	0	0	0	80000	60	5020	0	5	16	0	6	6	80044	19	19	15	80000	10	80085	80048	80048	80048	80085
80024	80084	599	0	0	0	0	0	0	0	1	0	0	80069	20	25	80010	10	80000	10	80000	50	3758344	0	49	77004	0	80032	80084	69937	3	70064	80010	20	80000	20	160000	80084	80084	1	1	80021	10	9	10	80000	10	80000	10	80000	0	14	80000	0	0	0	80000	60	5020	0	6	16	0	6	4	80081	19	0	15	80000	10	80048	80085	80085	80085	80048

STLRB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations