Firestorm: LDR (pre-index, 32-bit) measurements

Code:

  ldr w0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	23	24	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1040	29	0	0	0	0	55	18	0	0	0	4	0	1025	9	5	5	7	11	25	2000	1000	1000	1000	1000	52848	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1013	0	0	71	1047	6	0	20	26	29	1057	47	2	25	31	0	73	1	16	1	1	1037	1000	35	31	1000	1000	1041	1041	1041	1041	1041
2004	1040	41	0	0	0	0	57	20	1	0	0	3	4	1025	10	5	13	9	14	25	2000	1000	1000	1000	1000	52844	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1012	0	1	46	1039	6	0	28	0	32	1059	32	3	32	39	0	73	1	16	1	1	1037	1000	31	28	1000	1000	1044	1041	1044	1041	1041
2004	1040	9	0	0	0	0	59	0	0	0	0	5	4	1025	11	5	9	9	8	25	2000	1000	1000	1000	1000	52860	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1013	0	0	51	1021	0	0	0	0	15	1015	28	3	15	63	0	73	1	16	1	1	1037	1000	26	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	9	0	0	0	0	64	14	1	0	0	3	0	1025	11	3	9	9	14	25	2000	1000	1000	1000	1000	52852	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1014	0	0	33	1033	4	1	12	12	21	1026	36	1	10	63	0	73	1	16	1	1	1037	1000	28	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	9	0	0	0	1	43	11	0	0	0	2	0	1025	9	3	6	4	10	25	2000	1000	1000	1000	1000	52840	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1012	0	0	39	1020	1	0	20	8	17	1041	33	2	9	47	3	73	1	16	1	1	1037	1000	23	18	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	60	14	1	0	0	3	20	1025	10	5	6	5	13	25	2000	1000	1000	1000	1000	52856	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1016	0	0	33	1020	6	0	12	10	11	1014	28	2	19	55	0	73	1	16	1	1	1037	1000	28	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	0	0	53	0	0	0	0	7	0	1025	0	4	8	11	12	25	2000	1000	1000	1000	1000	52848	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1010	6	1	31	1035	1	0	14	12	9	1031	34	3	22	55	0	73	1	16	1	1	1037	1000	21	27	1000	1000	1041	1041	1041	1041	1041
2004	1040	9	0	0	0	0	62	12	0	0	0	4	0	1025	0	5	5	8	20	25	2000	1000	1000	1000	1000	52848	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1000	0	0	31	1033	3	0	12	14	15	1032	39	2	11	47	0	73	1	16	1	1	1037	1000	24	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	40	22	1	0	0	2	0	1025	10	6	8	10	17	25	2000	1000	1000	1000	1000	52848	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1010	0	0	32	1030	5	0	12	0	17	1033	24	5	16	39	0	73	1	16	1	1	1037	1000	26	26	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	0	0	44	15	0	0	1	3	0	1025	9	5	6	6	14	25	2000	1000	1000	1000	1000	52844	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	2	1018	0	1	57	1023	2	1	12	6	13	1034	24	3	10	63	5	73	1	16	1	1	1037	1000	36	22	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1695

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72067	538	0	0	0	0	0	0	541	0	809	1	616	3	76	71612	800	2	0	71591	25	50765	40624	10132	40106	10007	676374	2717225	0	49	68799	71766	71816	65277	7	65605	50113	40232	10008	70256	10008	71586	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10876	0	151	507	10649	242	10	896	120	37	10926	123	5	119	0	0	3	1	1	1	2620	1	16	1	1	71794	40556	914	944	959	10000	40100	71637	71754	71849	71867	71885
50204	71882	537	0	0	0	0	0	0	512	0	788	1	696	3	100	71938	751	3	0	71273	25	50825	40644	10122	40106	10007	675638	2718040	1	98	68599	71782	71705	65126	3	65483	50100	40200	10000	70200	10000	71788	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10898	0	154	461	10616	280	10	906	70	43	10871	116	3	125	0	27	4	0	0	0	2611	2	51	2	2	71533	40536	918	928	889	10000	40100	71680	71655	71556	71806	71801
50204	71804	538	0	0	0	0	0	0	546	0	837	1	656	4	84	71693	782	3	0	71360	25	50765	40660	10124	40252	10000	676270	2719722	1	49	68601	71519	71810	65001	3	65413	50100	40200	10000	70200	10000	71654	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10866	0	145	498	10665	245	11	888	120	42	10949	124	3	112	0	0	3	0	0	0	2611	2	63	2	2	71495	40536	850	900	817	10000	40100	71682	71851	71597	71754	71715
50204	71647	538	0	0	0	0	0	0	622	0	823	1	704	3	124	71596	817	3	0	71443	25	50745	40664	10119	40100	10000	676976	2709808	0	49	68642	71813	71715	65283	3	65438	50100	40200	10000	70200	10000	71674	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10876	0	159	528	10633	231	9	887	36	38	10898	122	4	135	0	0	5	0	0	0	2611	2	51	2	2	71450	40540	830	906	937	10000	40100	71685	71780	71762	71964	71628
50204	71797	538	0	0	0	1	0	0	508	0	808	1	680	1	100	71583	776	4	0	71389	25	50745	40652	10136	40100	10000	676016	2711540	0	49	68876	71892	71724	65241	3	65470	50100	40200	10000	70536	10000	71769	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10890	0	172	480	10622	221	12	894	138	43	10932	128	4	128	0	36	3	0	0	0	2611	2	51	2	2	71673	40595	958	996	934	10000	40100	71681	71773	71695	71481	71800
50204	71724	537	0	0	0	1	0	0	543	0	795	1	704	3	108	71649	790	5	0	71533	25	50730	40616	10121	40100	10000	675403	2712744	0	49	68701	71766	71590	65000	3	65417	50100	40200	10000	70200	10000	71829	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10880	0	146	492	10658	248	9	898	78	39	10917	134	3	117	0	0	4	0	0	0	2611	2	51	2	2	71504	40552	958	844	924	10000	40100	71752	71667	71765	71728	71663
50204	71680	537	0	0	1	0	0	0	515	0	829	1	664	2	104	71582	785	4	0	71670	25	50730	40620	10126	40100	10000	675545	2714674	1	49	68603	71771	71788	65100	3	65399	50100	40200	10000	70200	10000	71660	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10890	0	115	475	10661	234	10	872	36	37	10890	124	5	117	0	0	3	0	0	0	2611	2	51	2	2	71640	40512	900	824	832	10000	40100	71890	71627	71667	71817	71799
50204	71663	538	0	0	0	0	0	0	533	0	803	1	680	3	156	71736	802	4	0	71578	25	50805	40664	10124	40100	10000	677737	2715731	1	49	68598	71794	71726	65073	3	65254	50100	40399	10000	70200	10000	71720	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10898	0	125	516	10648	257	8	916	84	32	10933	132	4	117	0	0	4	0	0	0	2611	2	51	2	2	71695	40572	888	858	945	10000	40100	71810	71797	71679	71885	71675
50204	71680	537	0	0	0	0	0	0	555	0	804	1	688	0	56	71810	779	6	0	71592	25	50745	40584	10133	40100	10000	678086	2713415	0	49	68485	71722	71703	65078	3	65459	50100	40200	10000	70200	10000	71692	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10878	0	136	516	10651	251	14	890	136	46	10881	124	4	134	0	0	7	0	0	0	2611	2	50	2	2	71580	40520	998	926	944	10000	40100	71729	71864	71756	71839	71651
50204	71684	537	0	0	0	0	0	0	550	0	802	1	680	2	112	71699	772	5	0	71539	25	50710	40604	10129	40100	10000	677185	2709316	0	49	68643	71709	71950	65150	3	65374	50100	40200	10000	70200	10000	71775	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10898	0	133	502	10665	258	13	886	36	1851	10926	124	4	114	0	0	4	0	0	0	2653	2	79	2	2	71582	40516	994	956	839	10000	40100	71803	71848	71649	71659	71689

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1835

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72232	538	2	1	2	0	1	0	540	0	851	1	736	1	104	71727	837	4	3	71491	25	50685	40602	10121	40010	10000	612930	2729530	1	49	68601	72048	71808	65341	3	65571	50010	40020	10000	70020	10000	71741	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10929	1	148	490	10613	261	10	922	48	38	10939	142	5	141	1	3	9	0	2520	4	85	4	3	71680	40552	952	970	1000	10000	40010	71958	71884	71793	71786	71942
50024	71998	538	1	1	0	0	0	0	502	0	806	1	704	1	108	71954	795	5	3	71366	25	50710	40526	10123	40010	10000	612281	2725762	0	49	68802	71909	71849	65266	3	65236	50010	40020	10000	70020	10000	71876	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10924	3	148	445	10674	291	10	918	74	27	10956	126	5	131	1	0	9	0	2520	4	17	3	3	71612	40480	1008	958	1012	10000	40010	71912	71895	71628	71823	71899
50024	71741	538	1	0	1	0	0	0	519	0	830	1	720	1	132	71861	796	3	2	71563	25	50675	40562	10135	40172	10000	613667	2717953	0	49	68830	71948	71705	65344	3	65611	50010	40020	10000	70020	10000	71860	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10916	1	131	502	10652	254	9	932	38	39	10933	144	5	123	1	4	9	0	2520	4	85	4	4	71653	40552	876	988	1000	10000	40010	71873	71845	71900	71848	71856
50024	71910	538	1	0	0	0	0	0	548	0	821	1	712	1	132	71919	821	4	2	71525	25	50775	40514	10133	40010	10000	610143	2722168	0	49	68831	71982	71948	65323	3	65411	50010	40020	10000	70020	10000	71765	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10913	2	145	493	10662	276	11	926	34	32	10949	130	6	127	1	0	5	0	2520	4	71	4	3	71568	40560	988	970	906	10000	40010	71763	71984	71871	71929	71811
50024	71648	538	1	1	0	0	0	0	553	0	844	1	744	1	108	71849	804	3	2	71623	25	50715	40542	10137	40010	10000	612479	2723606	1	49	68622	71958	71866	65459	3	65551	50010	40020	10000	70020	10000	71740	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10903	1	154	508	10674	266	10	952	78	26	10952	144	6	121	1	4	3	0	2520	4	71	5	4	71594	40576	944	946	1020	10000	40010	71846	71969	71929	71891	71723
50024	71765	539	1	0	0	0	0	0	600	0	831	1	784	1	112	71839	807	3	2	71576	25	50680	40562	10129	40010	10000	611334	2718889	0	49	68684	71707	71916	65052	3	65578	50010	40020	10000	70020	10000	71756	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10899	2	148	487	10663	251	12	931	46	39	10939	123	6	127	1	7	9	0	2520	4	85	3	4	71657	40576	866	966	1022	10000	40010	71975	71608	71879	71759	71689
50024	71871	538	1	1	0	1	0	0	528	0	822	1	712	1	108	71777	789	4	2	71608	25	50690	40534	10138	40010	10000	612596	2726606	0	49	68804	71781	71770	65364	3	65452	50010	40020	10000	70020	10000	72065	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10900	1	146	508	10626	250	8	893	50	38	10964	134	6	140	1	0	3	0	2520	3	71	5	4	71629	40484	992	992	972	10000	40010	71947	71822	71900	71648	71779
50024	71768	538	1	0	0	0	0	0	546	0	832	1	712	1	132	71853	805	4	3	71464	25	50750	40562	10139	40010	10000	612308	2713278	0	49	68670	71770	71848	65412	3	65413	50010	40020	10000	70020	10000	71699	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10925	3	134	498	10637	286	9	916	78	34	10926	147	4	130	1	0	3	0	2520	4	85	4	3	71497	40580	920	1034	880	10000	40010	71715	71930	71968	71734	71665
50024	71775	538	1	1	1	0	0	0	543	0	812	1	704	1	108	71823	825	3	2	71674	25	50695	40530	10135	40010	10000	612425	2717711	0	49	68683	71904	71824	65312	3	65321	50010	40020	10000	70020	10000	71780	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10908	2	123	501	10649	277	12	924	48	41	10929	141	5	141	1	3	3	0	2520	4	57	4	4	71687	40584	934	1030	924	10000	40010	71797	71732	71837	71860	71793
50024	71922	538	1	0	0	0	0	0	500	0	834	1	728	1	124	71845	818	5	2	71543	25	50685	40594	10144	40010	10000	610011	2718984	0	49	68793	72070	71905	65321	3	65545	50010	40020	10000	70020	10000	71789	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10945	2	135	506	10665	257	13	930	74	35	10935	139	4	136	1	0	3	0	2520	5	71	4	4	71845	40580	964	1006	954	10000	40010	71989	71977	71786	71849	71878

Test 3: throughput

Count: 8

Code:

  ldr w0, [x6, #8]!
  ldr w0, [x7, #8]!
  ldr w0, [x8, #8]!
  ldr w0, [x9, #8]!
  ldr w0, [x10, #8]!
  ldr w0, [x11, #8]!
  ldr w0, [x12, #8]!
  ldr w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3661

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29430	220	0	0	0	0	6557	843	1	704	107	100	29359	811	447	1892	2349	2083	25	160167	80163	80000	80100	80000	400789	1286714	0	53	49	26117	29221	29279	9089	3	9157	160100	80200	80000	80200	80000	29333	35	1	1	80201	100	99	22	100	80000	100	80000	100	80925	446	5298	85166	755	11	925	42	4844	85857	715	119	4944	5588	0	4	5110	1	16	1	1	29468	32	80057	430	468	78	80000	80100	29440	29270	29363	29399	29234
160204	29164	220	0	0	0	0	6663	811	1	768	117	144	29148	814	479	1908	2092	2080	56	160460	80162	80000	80100	80000	400764	1275005	0	60	49	26106	29443	29272	9366	3	9308	160100	80200	80000	80200	80000	29312	35	1	1	80201	100	99	14	100	80000	100	80000	100	80914	464	5225	85015	801	8	909	52	5207	85787	805	136	4939	4679	0	19	5110	1	16	1	1	29219	29	80074	407	536	66	80000	80100	29188	29326	29328	29375	29318
160204	29218	220	0	0	0	0	5807	833	1	728	120	124	29403	810	485	2063	2185	1988	25	160158	80152	80000	80100	80000	400766	1289710	1	57	49	26260	29476	29234	9287	3	9400	160100	80200	80000	80200	80000	29375	35	1	1	80201	100	99	9	100	80000	100	80000	100	80925	477	5500	84921	756	9	880	84	4816	85905	813	129	4958	5284	3	4	5110	1	17	1	1	29141	31	80046	427	423	71	80000	80100	29254	29117	29324	29303	29097
160204	29448	218	0	0	0	0	6794	854	1	728	135	184	28965	827	441	2047	2006	2078	25	160146	80343	80000	80100	80000	400845	1291241	1	57	49	25871	29246	29214	9345	3	9291	160100	80200	80000	80200	80000	29114	35	1	1	80201	100	99	15	100	80000	100	80000	100	80938	439	5074	84637	756	13	964	78	5271	85601	764	138	5037	5216	0	7	5110	1	16	1	1	29138	49	80058	435	381	68	80000	80100	29348	29318	29362	29196	29282
160204	29420	220	0	0	0	0	6735	880	1	744	122	104	29064	797	462	2221	2189	2025	25	160155	80153	80000	80100	80000	400774	1291686	1	46	49	26230	29694	29223	9216	3	9243	160100	80200	80000	80200	80000	29208	35	1	1	80201	100	99	18	100	80000	100	80000	100	80906	492	5138	85363	775	11	979	42	4417	85735	794	126	4491	5144	0	3	5110	1	17	1	1	29216	28	80053	359	397	81	80000	80100	29171	29305	29330	29165	29339
160204	29270	218	0	0	0	0	6699	846	1	784	112	152	29295	790	465	1905	2046	2090	25	160170	80154	80000	80100	80000	400766	1287864	0	51	49	26265	29068	29140	9191	25	9209	160100	80200	80000	80200	80000	29365	35	1	1	80201	100	99	21	100	80000	100	80000	100	80924	422	4896	85440	779	10	976	56	4889	85697	793	134	4937	5062	0	3	5110	1	16	1	1	29491	34	80074	389	431	91	80000	80100	29326	29321	29357	29374	29312
160204	29258	220	0	0	0	0	6655	803	1	736	132	108	29186	818	485	2139	2014	1815	25	160147	80158	80000	80100	80000	400764	1285705	0	64	49	26226	29296	29372	9392	3	9180	160100	80200	80000	80200	80000	29306	35	1	1	80201	100	99	19	100	80000	100	80000	100	80923	475	5113	85093	753	9	956	36	4992	85565	768	127	4803	5257	3	5	5110	1	16	1	1	29267	34	80055	379	478	89	80000	80100	29360	28954	29210	29396	29390
160204	29246	220	0	0	0	0	6529	856	1	744	112	148	29146	800	486	1888	2015	1891	25	160159	80161	80000	80100	80000	400754	1290470	0	70	49	25969	29251	29204	9337	3	8986	160100	80200	80000	80200	80000	29102	35	1	1	80201	100	99	10	100	80000	100	80000	100	80921	471	5375	84553	741	3	976	30	4883	85511	796	132	5094	5185	0	8	5110	1	16	1	1	29194	37	80054	410	462	63	80000	80100	29134	29197	29164	29238	29225
160204	29443	220	0	0	0	0	6600	809	1	752	92	128	29086	815	468	1850	1892	2030	25	160160	80153	80000	80100	80000	400741	1294008	1	63	49	26182	29307	29319	9096	3	9451	160100	80200	80000	80200	80000	29248	35	1	1	80201	100	99	13	100	80000	100	80000	100	80903	480	5634	85193	777	11	980	56	4791	85769	758	133	5341	4787	0	4	5110	1	16	1	1	29406	34	80034	398	380	74	80000	80100	29457	29675	29342	29388	29458
160204	29434	220	0	1	0	1	6804	844	1	688	134	120	29080	850	455	2273	1920	2018	25	160154	80160	80000	80100	80000	400779	1293925	0	61	49	26049	29293	29230	9092	3	9183	160100	80200	80000	80200	80000	29317	35	1	1	80201	100	99	17	100	80000	100	80000	100	80921	505	5894	85012	788	7	993	40	4758	86316	813	133	5095	5474	3	3	5110	1	16	1	1	29273	37	80052	364	433	91	80000	80100	29249	29217	29148	29395	29245

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3687

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	l2 tlb miss data (0b)	0e	0f	18	19	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29805	220	2	0	0	1	0	0	6912	829	1	504	120	132	29542	806	521	1730	1677	2326	25	160071	80065	80000	80010	80000	400372	1318806	55	49	26681	29322	29305	9635	0	3	9546	160010	80020	80000	80020	80000	29636	35	1	1	80021	10	9	55	10	80000	10	80000	0	10	80933	349	5420	85300	689	12	924	44	5510	86144	776	128	5184	5833	0	9	5020	4	16	2	4	29560	30	80059	591	585	104	80000	80010	29462	29514	29478	29277	29626
160024	29544	221	1	0	0	0	0	0	7046	845	1	704	126	120	29459	795	446	1819	1864	2132	156	160077	80066	80000	80010	80000	400364	1309339	62	49	26416	29448	29341	9608	0	3	9441	160010	80020	80526	80020	80000	29438	35	1	1	80021	10	9	40	10	80000	10	80000	0	10	80938	409	5858	85576	691	12	915	50	5012	85812	774	140	5232	5582	6	2	5020	3	16	1	3	29509	32	80060	507	614	102	80000	80010	29531	29637	29582	29437	29485
160024	29445	220	2	0	0	0	0	0	7054	825	1	712	119	140	29347	794	441	1860	1967	2373	25	160077	80087	80000	80010	80000	400365	1308390	64	49	26389	29425	29626	9597	0	3	9552	160010	80020	80000	80020	80000	29512	35	1	1	80021	10	9	49	10	80000	10	80000	0	10	80940	345	5236	85495	656	14	908	72	4908	86836	884	127	5308	5421	0	7	5020	3	16	3	1	29568	35	80047	609	611	106	80000	80010	29308	29553	29482	29417	29575
160024	29529	222	2	0	0	0	0	0	6926	808	1	744	121	112	29846	793	449	1856	2043	2182	25	160090	80076	80000	80010	80000	400379	1310273	64	49	26598	29300	29611	9505	0	3	9422	160010	80020	80000	80020	80000	29413	35	1	1	80021	10	9	59	10	80000	10	80000	0	10	80906	388	5875	85678	649	10	930	48	6129	86561	813	141	5433	5853	0	3	5020	4	16	4	3	29560	28	80074	610	535	121	80000	80010	29392	29461	29527	29549	29703
160024	29519	221	2	0	0	0	0	0	6830	846	1	608	114	96	29676	823	457	1899	1906	2275	25	160073	80077	80000	80010	80000	400385	1316380	70	49	26385	29445	29467	9463	0	3	9526	160010	80020	80000	80020	80000	29615	35	1	1	80021	10	9	40	10	80000	10	80000	1	10	80911	383	5317	86145	637	12	936	70	5264	87089	798	140	5129	5264	6	4	5020	6	16	4	2	29597	37	80067	635	583	101	80000	80010	29382	29498	29439	29475	29419
160024	29795	221	1	0	0	0	0	0	6710	838	1	768	114	116	29191	803	510	1913	1734	2320	25	160066	80080	80000	80010	80000	400351	1310227	61	49	26223	29720	29282	9345	0	3	9559	160010	80020	80000	80020	80000	29406	35	1	1	80021	10	9	35	10	80000	10	80000	0	10	80911	420	5545	84912	651	12	925	72	5356	86282	833	132	5037	5429	0	9	5020	3	16	4	3	29547	32	80062	561	601	97	80000	80010	29511	29391	29694	29437	29416
160024	29253	219	1	0	0	0	0	0	6980	863	1	744	122	108	29618	767	465	1915	1783	2308	25	160068	80072	80000	80010	80000	400357	1315037	76	49	26339	29308	29616	9386	0	3	9637	160010	80020	80000	80020	80000	29545	35	1	1	80021	10	9	39	10	80000	10	80000	0	10	80910	407	6307	86035	636	8	922	74	5376	86489	781	143	5567	5860	0	8	5020	1	16	3	5	29444	32	80076	568	603	104	80000	80010	29400	29540	29569	29462	29617
160024	29430	220	1	0	0	0	0	0	7170	840	1	728	124	208	29478	819	490	1700	1941	2180	25	160081	80067	80000	80010	80000	400320	1311277	63	49	26476	29426	29585	9310	0	3	9480	160010	80020	80000	80020	80000	29470	35	1	1	80021	10	9	50	10	80000	10	80000	0	10	80912	443	5604	85291	644	10	980	48	5502	86719	710	134	5204	5605	0	3	5020	5	16	5	2	29714	39	80056	555	608	105	80000	80010	29653	29357	29594	29555	29552
160024	29475	222	1	1	0	0	0	0	6882	905	1	720	112	120	29724	805	476	2004	1854	2112	25	160067	80075	80000	80010	80000	400341	1315199	62	49	26699	29438	29701	9400	0	3	9502	160010	80020	80000	80020	80000	29688	35	1	1	80021	10	9	61	10	80000	10	80000	0	10	80949	373	5757	85281	646	11	928	50	5110	85887	786	136	5078	5294	6	3	5020	2	16	2	4	29426	30	80057	605	576	101	80000	80010	30029	29384	29571	29690	29580
160024	29673	220	1	0	0	0	0	0	7255	845	1	704	137	100	29336	849	471	1835	1745	2346	25	160084	80079	80000	80010	80000	400336	1298872	63	49	26423	29273	29552	9453	0	3	9579	160010	80020	80000	80020	80000	29510	35	1	1	80021	10	9	46	10	80000	10	80000	1	10	80905	440	5491	85401	654	13	973	40	5782	86247	773	139	5318	5278	0	0	5020	3	15	2	3	29628	32	80073	621	612	128	80000	80010	29413	29453	29525	29550	29642

LDR (pre-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations