Firestorm: LDR (32-bit) measurements

Code:

  ldr w0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	1	0	0	45	0	0	1	379	2	0	12	0	25	1000	1000	1000	14219	1	394	397	217	3	252	1000	1000	1000	394	56	1	1	1001	1000	1000	1	1000	43	1039	39	1000	6	1	39	43	73	1	16	2	1	399	10	10	4	1000	395	395	375	375	376
1004	374	3	0	1	1	45	0	0	0	379	0	0	0	16	25	1000	1000	1000	14060	1	394	374	217	3	232	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	0	1000	39	1039	0	1	39	43	73	2	16	2	1	391	0	10	4	1000	395	395	375	396	375
1004	394	3	0	0	0	0	1	0	1	359	0	12	12	16	25	1000	1000	1000	15037	0	394	394	217	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	1	1000	0	1039	39	1039	6	0	0	0	73	1	16	1	1	371	10	10	0	1000	375	375	395	395	375
1004	374	3	1	0	0	45	0	0	1	359	2	0	0	16	25	1000	1000	1000	14989	0	378	374	217	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1039	39	1039	6	1	0	43	73	2	16	2	2	391	0	10	4	1000	395	395	395	395	375
1004	374	3	0	0	0	0	0	0	0	379	2	12	0	16	25	1000	1000	1000	15018	1	394	374	218	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1039	39	1039	0	0	39	43	73	2	16	2	2	391	10	0	0	1000	395	395	375	395	395
1004	394	2	0	0	0	45	0	0	0	360	2	0	0	16	25	1000	1000	1000	14989	0	374	394	197	3	232	1000	1000	1000	374	77	1	1	1001	1000	1000	0	1000	43	1039	39	1000	0	1	39	43	73	1	16	1	1	391	10	10	0	1000	375	375	395	395	375
1004	394	2	0	0	0	45	1	0	0	359	0	0	0	16	25	1000	1000	1000	14060	0	374	374	197	3	232	1000	1000	1000	374	77	1	1	1001	1000	1000	0	1000	0	1039	39	1039	0	1	39	0	73	2	16	2	2	391	0	0	4	1000	395	395	395	395	395
1004	394	3	0	0	0	45	1	0	1	359	0	12	0	0	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	0	1039	0	1039	6	1	39	0	73	1	16	1	2	371	0	0	0	1000	395	375	395	395	376
1004	394	3	0	0	0	45	0	0	0	379	2	12	12	0	25	1000	1000	1000	15037	0	394	374	197	3	232	1000	1000	1000	374	77	1	1	1001	1000	1000	0	1000	43	1000	39	1039	0	1	0	43	73	2	16	2	2	391	10	10	4	1000	395	395	375	375	399
1004	394	3	1	1	0	0	0	1	1	379	0	0	12	0	25	1000	1000	1000	14060	0	396	374	217	3	252	1000	1000	1000	394	56	1	1	1001	1000	1000	1	1000	43	1000	0	1000	6	0	0	43	73	2	16	2	2	371	10	10	4	1000	395	395	375	395	375

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	0	0	0	0	0	0	1	0	0	0	0	70032	69735	59745	25	40100	30103	10001	30111	10007	615540	3342375	49	66970	70047	70047	64699	6	64986	40118	30230	10010	60260	10010	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	1	0	0	10000	1	0	0	2610	3	71	1	1	69810	30003	0	6	6	10000	30100	70049	70040	70406	70042	70036
40204	70035	525	0	0	0	1	0	0	1	0	1	0	0	70032	69735	59706	25	40100	30103	10007	30100	10000	616015	3342062	49	66955	70047	70035	64631	3	64958	40100	30696	10000	60200	10000	70036	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	2610	1	71	1	1	69946	30003	0	6	0	10000	30100	70036	70048	70036	70048	70048
40204	70047	525	0	0	0	0	0	0	0	0	0	0	0	70020	69764	59707	25	40160	30103	10001	30100	10000	616015	3342062	49	66967	70047	70047	64643	3	64985	40100	30200	10000	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	2610	1	71	1	1	69810	30003	6	6	0	10000	30100	70038	70048	70048	70049	70048
40204	70035	524	0	0	1	1	0	0	39	0	1	0	0	70032	69735	59706	25	40100	30103	10001	30100	10000	616015	3342254	49	66956	70050	70217	64777	3	64989	40100	30200	10000	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	2610	1	71	1	1	69798	30000	6	6	6	10000	30100	70038	70395	70050	70048	70048
40204	70047	525	0	1	0	0	0	0	1	0	1	0	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3342062	49	66967	70047	70035	64643	3	64978	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	0	10012	1	1	0	2610	1	71	1	1	70089	30003	6	6	6	10000	30100	70048	70048	70036	70048	70048
40204	70047	524	0	0	0	0	0	0	1	0	1	0	0	70020	69781	59695	25	40100	30103	10001	30100	10000	616015	3342062	49	66970	70035	70035	64646	3	64990	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	1	0	0	10000	1	0	0	2610	1	71	1	1	69813	30000	9	6	0	10000	30100	70051	70054	70133	70178	70051
40204	70050	524	0	0	0	0	0	0	16	0	1	0	0	70025	69781	59695	25	40100	30103	10000	30100	10000	616005	3342206	49	66970	70050	70035	64646	3	64957	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	18	10000	1	1	0	2610	1	71	1	1	69810	30003	0	6	6	10000	30100	70048	70048	70036	70048	70048
40204	70035	525	0	0	0	1	0	0	1	0	0	0	0	70024	69735	59706	25	40104	30100	10000	30100	10000	616015	3342062	49	66967	70035	70047	64750	3	64975	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	4	2	0	10000	1	1	2	2610	1	71	1	2	69816	30003	6	0	6	10000	30100	70051	70048	70055	70315	70051
40204	70050	524	0	0	1	0	0	0	15	264	1	0	0	70020	69764	59826	25	40104	30100	10001	30100	10000	616175	3342062	49	66967	70035	70047	64631	3	65005	40100	30200	10000	60200	10164	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	2610	1	71	1	1	69798	30003	0	6	6	10000	30100	70048	70048	70036	70048	70048
40204	70047	524	1	0	0	1	0	0	0	0	1	0	0	70035	69764	59696	25	40104	30100	10001	30100	10000	616015	3342062	49	66967	70035	70035	64643	3	64956	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	2610	1	71	1	1	69813	30003	0	6	6	10000	30100	70048	70048	70036	70048	70048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	524	1	0	0	0	0	235	0	1	0	70032	69728	59709	25	40014	30013	10002	30010	10000	616982	3341470	0	1	49	66967	70035	70050	64768	3	64975	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	2	71	1	1	69813	30003	9	6	0	10000	30010	70036	70051	70051	70051	70036
40024	70035	525	0	1	1	0	0	42	0	1	0	70035	69743	59695	25	40014	30010	10001	30010	10000	616982	3341470	0	0	49	66970	70050	70050	64659	3	64960	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	3	10000	1	0	0	2520	2	71	1	1	69798	30003	9	0	9	10000	30010	70051	70048	70036	70051	70048
40024	70047	524	0	0	0	0	0	549	0	1	0	70020	69760	59695	48	40022	30022	10001	30010	10000	617068	3342206	0	0	49	66970	70050	70035	64746	3	64960	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	0	2520	1	71	1	1	69855	30003	0	6	9	10000	30010	70051	70051	70051	70036	70048
40024	70050	524	0	0	0	0	0	46	0	1	0	70035	69743	59695	25	40014	30013	10001	30010	10000	616982	3342206	0	0	49	66970	70050	70035	64668	3	64975	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	1	69813	30003	9	6	9	10000	30010	70051	70051	70051	70051	70051
40024	70050	524	0	0	0	0	0	36	0	1	0	70035	69760	59709	25	40014	30013	10001	30010	10000	616982	3341470	0	0	49	66970	70050	70035	64665	3	64972	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2554	1	71	1	1	69810	30003	9	0	9	10000	30010	70048	70051	70051	70038	70090
40024	70050	525	0	0	0	0	0	61	0	1	0	70035	69760	59709	25	40010	30013	10000	30010	10000	617068	3342206	0	0	49	66955	70050	70035	64665	3	64960	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	0	2520	1	71	1	1	69813	30003	9	6	9	10000	30010	70051	70051	70051	70051	70051
40024	70035	525	0	0	0	0	0	34	0	1	0	70035	69728	59709	25	40010	30013	10001	30010	10000	616982	3342206	0	0	49	66955	70047	70050	64665	3	64975	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	0	0	2520	2	71	1	1	69798	30003	6	6	9	10000	30010	70051	70051	70036	70051	70051
40024	70050	525	0	0	0	0	0	550	0	1	0	70035	69792	59706	25	40010	30013	10001	30010	10000	616982	3342206	0	0	49	66970	70035	70050	64766	3	64975	40010	30020	10000	60020	10066	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	3	10000	1	1	0	2520	1	71	1	1	69798	30003	0	6	9	10000	30010	70039	70048	70044	70056	70051
40024	70050	524	0	1	0	0	0	717	0	1	0	70035	69743	59709	25	40014	30013	10001	30010	10000	617068	3342206	0	0	98	66955	70053	70035	64666	3	64978	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	1	69810	30003	9	0	9	10000	30010	70036	70051	70051	70051	70036
40024	70047	524	0	1	1	0	0	34	0	1	0	70020	69760	59695	25	40014	30013	10001	30010	10000	616982	3342206	0	0	49	66955	70050	70050	64668	3	64975	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	1	69813	30000	9	9	9	10000	30010	70051	70051	70036	70051	70036

Test 3: throughput

Count: 8

Code:

  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26740	200	1	1	0	0	0	66	1	0	3	26721	0	7	7	20	25	80100	100	80000	100	80000	500	1167555	1	49	23657	26715	26736	16637	3	16694	80100	200	80000	200	80000	26737	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	20	43	0	80059	1	0	1	64	80039	6	1	59	0	19	1	5110	2	16	2	2	26711	0	0	13	5	80000	100	26737	26737	26737	26715	26715
80204	26736	200	1	1	1	1	0	67	0	0	3	26721	3	7	0	19	25	80100	100	80000	100	80000	500	1172437	0	49	23657	26736	26736	16659	3	16672	80100	200	80000	200	80000	26714	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	21	43	0	80019	1	0	1	21	80039	6	0	19	43	19	1	5110	2	16	2	2	26711	0	13	0	5	80000	100	26737	26737	26715	26737	26738
80204	26737	200	1	0	0	1	0	67	0	0	0	26699	3	7	7	19	25	80100	100	80000	100	80000	500	1167142	1	49	23656	26714	26736	16637	3	16695	80100	200	80000	200	80000	26736	64	1	1	80201	100	99	0	100	80000	100	80000	0	100	80021	19	43	0	80058	1	0	1	61	80039	0	1	19	43	19	1	5110	2	16	2	2	26734	0	13	13	5	80000	100	26715	26737	26715	26737	26738
80204	26714	200	1	1	0	1	0	67	0	0	2	26721	2	7	9	0	25	80100	100	80000	100	80000	500	1166519	1	49	23634	26714	26736	16637	3	16672	80100	200	80000	200	80000	27016	64	1	1	80201	100	99	0	100	80000	100	80000	0	100	80021	19	43	0	80059	1	0	1	60	80040	6	0	59	43	19	0	5110	2	16	2	2	26733	0	13	7	0	80000	100	26737	26737	26715	26737	26715
80204	26767	200	1	0	1	1	0	21	1	0	3	26699	2	7	9	20	25	80100	100	80000	100	80000	500	1167224	0	49	23656	26714	26736	16659	3	16694	80100	200	80000	200	80000	26737	64	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	19	43	0	80058	1	0	1	60	80040	6	1	19	0	19	2	5110	2	16	2	2	26711	0	0	13	5	80000	100	26738	26737	26715	26737	26737
80204	26736	200	1	1	1	0	0	66	1	0	2	26699	3	7	7	18	25	80100	100	80000	100	80000	500	1167388	1	49	23656	26714	26736	16658	3	16672	80100	200	80000	200	80000	26736	64	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	21	43	0	80059	0	0	2	64	80000	6	1	59	0	19	1	5110	2	16	2	2	26733	0	13	0	5	80000	100	26737	26715	26737	26715	26737
80204	26736	200	1	0	0	0	0	21	1	0	2	26721	0	0	9	19	25	80100	100	80000	100	80000	500	1167142	0	49	23646	26736	26736	16661	3	16672	80100	200	80000	200	80000	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	43	0	80059	1	0	1	61	80000	6	1	58	43	19	2	5110	2	16	2	2	26711	0	13	13	5	80000	100	26737	26737	26715	26737	26737
80204	26736	200	1	1	1	1	0	67	0	0	0	26722	3	0	7	20	25	80100	100	80000	100	80000	500	1169868	0	49	23656	26736	26714	16658	3	16695	80100	200	80000	200	80000	26736	64	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	0	0	80058	1	0	1	21	80040	6	1	19	43	19	0	5110	2	16	2	2	26733	0	13	13	5	80000	100	26715	26737	26737	26737	26737
80204	26714	201	1	1	1	0	0	67	0	0	3	26699	2	7	15	19	25	80100	100	80000	100	80000	500	1168432	1	49	23675	26736	26737	16659	3	16696	80100	200	80000	200	80000	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	20	0	0	80019	0	1	0	61	80041	6	1	59	0	19	0	5110	2	16	2	2	26733	0	13	7	5	80000	100	26737	26715	26737	26737	26738
80204	26737	200	1	1	1	1	0	67	0	0	3	26721	2	7	0	19	25	80100	100	80000	100	80000	500	1169868	0	49	23656	26714	26736	16658	3	16695	80100	200	80000	200	80000	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	19	0	0	80058	0	0	0	61	80040	6	0	19	43	18	1	5110	2	16	2	2	26733	0	0	13	5	80000	100	26737	26737	26737	26737	26737

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26722	200	1	1	0	1	0	0	65	0	0	0	26717	2	18	18	16	25	80010	10	80000	10	80000	50	1169485	0	1	0	49	23642	26722	26722	16667	3	16694	80010	20	80000	20	80000	26732	64	1	1	80021	10	9	10	80000	10	80000	1	10	80020	19	42	80057	1	0	1	59	80039	6	1	19	42	19	1	0	5020	5	0	5	16	2	3	26729	9	9	2	80000	10	26734	26734	26734	26733	26733
80024	26715	200	0	0	0	0	1	0	0	0	0	2	26693	0	0	12	16	25	80010	10	80000	10	80000	50	1171143	0	1	5	49	23647	26722	26728	16672	3	16688	80010	20	80000	20	80000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80000	0	0	0	39	80000	6	0	0	0	0	0	0	5020	5	0	3	16	3	3	26724	10	0	2	80000	10	26709	26723	26723	26709	26729
80024	26722	200	0	0	0	0	0	0	0	0	0	0	26693	2	12	0	0	25	80010	10	80000	10	80000	50	1167605	0	1	5	49	23648	26708	26727	16672	3	16688	80010	20	80000	20	80000	26727	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	0	80000	0	0	0	42	80038	6	0	39	43	0	0	0	5020	5	0	3	16	3	3	26724	10	10	0	80000	10	26709	26723	26723	26723	26728
80024	26730	200	0	0	0	0	1	1	41	0	0	0	26712	0	0	0	0	25	80010	10	80000	10	80000	50	1172690	0	1	5	49	23647	26722	26708	16672	3	16688	80010	20	80000	20	80000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80039	0	0	0	35	80000	6	1	39	0	0	0	0	5020	5	1	2	16	2	3	26724	6	10	0	80000	10	26723	26709	26728	26709	26723
80024	26708	200	1	1	0	0	0	0	21	1	0	1	26717	1	18	0	0	25	80010	10	80000	10	80000	50	1167605	0	1	5	49	23648	26708	26708	16672	3	16707	80010	22	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80039	0	0	0	0	80035	6	1	0	43	0	0	0	5020	5	1	3	16	2	3	26705	10	10	0	80000	10	26729	26729	26709	26728	26729
80024	26728	200	0	0	0	0	1	0	41	1	0	0	26707	2	0	18	0	25	80010	10	80000	10	80000	50	1172954	0	1	5	49	23642	26708	26727	16652	3	16702	80010	20	80000	20	80000	26722	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80000	0	0	0	35	80035	6	1	35	39	0	0	0	5020	5	1	3	16	3	3	26719	6	10	2	80000	10	26723	26723	26723	26709	26723
80024	26708	200	0	0	0	0	0	0	41	0	0	1	26693	2	12	18	0	25	80010	10	80000	10	80000	50	1170455	0	1	5	49	23628	26727	26728	16672	3	16707	80010	20	80000	20	80000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80039	0	1	0	39	80035	6	0	35	39	0	0	0	5020	5	1	3	16	2	3	26719	6	6	2	80000	10	26709	26723	26726	26709	26736
80024	26722	200	1	0	0	0	0	0	45	1	0	2	26712	2	12	0	0	25	80010	10	80000	10	80000	50	1171390	0	1	5	49	23653	26732	26732	16677	3	16712	80010	20	80000	20	80000	26732	64	1	1	80021	10	9	10	80000	10	80000	0	10	80021	19	0	80057	1	0	2	62	80035	6	0	39	43	0	0	1	5020	5	1	3	16	3	3	26724	6	10	4	80000	10	26729	26709	26728	26728	26709
80024	26727	200	0	0	0	0	0	0	45	0	0	1	26712	2	12	0	16	25	80010	10	80000	10	80000	50	1171423	0	1	5	49	23628	26727	26727	16655	3	16707	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80039	0	0	0	35	80000	6	1	0	43	0	0	0	5020	5	1	3	16	3	3	26725	0	10	0	80000	10	26729	26729	26729	26729	26728
80024	26727	200	1	0	0	0	0	1	45	0	0	2	26713	0	12	0	16	25	80010	10	80000	10	80000	50	1167298	0	1	5	49	23648	26728	26727	16781	3	16707	80010	20	80000	20	80000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80039	0	0	0	39	80037	6	0	35	43	0	0	0	5020	5	1	3	16	3	2	26724	10	10	2	80000	10	26729	26728	26728	26729	26709

LDR (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations